JPH0575124A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] To suppress the occurrence of parasitic bipolar operation and realize a steep on / off characteristic exceeding the theoretical value of a bulk FET in a MOS field effect transistor having a thin film SOI structure. A p-type channel region 11, an n-type source diffusion layer 24, and an n-type drain diffusion layer are formed in a single crystal silicon substrate formed on a buried oxide film 16, and are formed on the channel region 11. With the first gate electrode 19
The thin film SOI structure MOS type field effect transistor is constructed. A p-type diffusion layer 27 is formed in contact with the n-type source diffusion layer in the single crystal silicon substrate, and a second gate electrode 15 is formed in the buried oxide film 16 below the source diffusion layer 24. .. p-type channel region 11, n-type source diffusion layer 24, p-type diffusion layer 27, and second gate electrode 15
A second thin film SOI structure MOS field effect transistor is constituted by.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a thin film SOI structure MOS field effect transistor and a method for manufacturing the same.

In recent years, the improvement in the performance of semiconductor devices has largely depended on the improvement in the performance of a single transistor due to the miniaturization of the transistor. As one of the high performance transistors, a MOS type field effect transistor having a thin film SOI structure has recently been attracting attention.

[0003]

2. Description of the Related Art FIG. 11 is a diagram showing a conventional example, and shows an example of a conventional MOS type field effect transistor having a thin film SOI structure.

In the figure, 41 is a silicon support substrate, 42 is a buried oxide film, 43 is an element isolation oxide film, 44 is a gate electrode,
45 is a channel region, 46 is a source diffusion layer, 47 is a drain diffusion layer, 48 is an interlayer insulating film, 49 is a source contact, and 50 is a drain contact.

The MOS type field effect transistor of the thin film SOI structure shown in FIG. 11 has a MOSF formed in the bulk.
It has the following advantages over ET. Short channel effects such as a decrease in threshold Vth and punch through are small.

The drain current can be increased by increasing the field effect mobility by increasing the vertical electric field and by increasing the pinch-off voltage. Since complete element isolation is possible, it is possible to prevent the latch-up phenomenon in CMOS and realize high integration.

In the linear region (subthreshold characteristic) of the drain current-gate voltage characteristic shown in FIG. 12, for example, when the drain voltage is 0.1 V, a theoretical ideal value which cannot be obtained by the bulk FET shown in the left side of FIG. There is 6
A characteristic close to 0 mV / dec is obtained. Furthermore, FIG.
As shown in the center, characteristics of 60 mV / dec or less of the theoretical value may be obtained at a relatively low drain voltage of about 2 to 3V.

[0008]

In the conventional MOS type field effect transistor having the thin film SOI structure shown in FIG. 11, when the drain voltage is a relatively low voltage of about 2 to 3 V, as shown in the center of FIG. The characteristics below the theoretical value of 60 mV / dec are obtained because the charges (holes in NMOS, electrons in PMOS) generated by impact ionization in the vicinity of the drain diffusion layer 47 of the channel region 45 are accumulated in the channel region 45. This is because the threshold value Vth changes in synchronization with the drain current in order to increase the potential of the region 45.

However, when the drain voltage becomes higher, impact ionization becomes stronger than the limit, and the lateral NPN bipolar transistor composed of the source diffusion layer 46-channel region 45-drain diffusion layer 47 is turned on. As shown on the right, there is a problem that the MOS transistor does not operate.

Although the above discussion has been made on the case of the DC characteristic, the mechanism becomes more complicated in the actual dynamic AC characteristic of the device, and the transistor characteristic varies depending on the operating frequency even if the power supply voltage is the same, and the circuit There was also a problem that it hindered the design.

The present invention solves the above problems, suppresses the occurrence of parasitic bipolar operation, and realizes steep on / off characteristics exceeding the theoretical value of a bulk FET, and is a MOS field effect of a thin film SOI structure. The purpose is to provide a transistor.

[0012]

In order to achieve the above-mentioned object, a semiconductor device according to the present invention has a single conductivity type channel region and an opposite conductivity type in a single crystal semiconductor layer formed on an insulating film. A thin film SOI structure MOS field-effect transistor having a first gate electrode on a channel region, in which a source diffusion layer and a drain diffusion layer are formed in the single crystal semiconductor layer. Alternatively, a second diffusion layer formed in contact with the drain diffusion layer and having a conductivity type opposite to that of the source / drain diffusion layer, and a second insulating layer formed under the source diffusion layer and / or the drain diffusion layer. And a gate electrode thereof.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a MOS field effect transistor having a thin film SOI structure, which comprises forming a groove for element isolation in a semiconductor substrate of one conductivity type and then A step of forming an element isolation oxide film by burying an oxide film on the substrate, a step of forming a gate oxide film on the substrate surface, then depositing a polycrystalline semiconductor and patterning it to form a second gate electrode, After depositing the insulating film, a step of flattening the insulating film to a predetermined thickness, a step of adhering the semiconductor substrate to a supporting substrate with the surface of the flattened insulating film facing down, and using the element isolation oxide film as a stopper , A step of polishing the semiconductor substrate from the back surface to form a thin film, and after forming a gate oxide film on the surface, depositing a polycrystalline semiconductor or an alloy of a refractory metal and a semiconductor and patterning the first gate electrode. Form And a step of performing ion implantation using the first gate electrode as a mask to form a source diffusion layer and a drain diffusion layer, and after covering the first gate electrode, the source diffusion layer and the drain diffusion layer with a resist, Ion implantation using the resist as a mask, and contacting the source diffusion layer and / or the drain diffusion layer to form a diffusion layer having a conductivity type opposite to the conductivity type of the source / drain diffusion layer.

[0014]

In the present invention, a double gate structure is adopted in a MOS field effect transistor having a thin film SOI structure,
A second gate electrode is provided in the buried insulating film below the source diffusion layer and serves as a drain of the second MOSFET constituted by the second gate electrode, and has a conductivity type opposite to that of the source diffusion layer. A diffusion layer is formed adjacent to the source diffusion layer.

In the above structure, the channel resistance of the second MOSFET is changed by changing the voltage of the second gate electrode in synchronism with ON / OFF of the first gate electrode, which is generated by impact ionization. The potential fluctuation of the channel region of the first MOSFET due to electric charge is controlled. This suppresses the occurrence of parasitic bipolar operation in the first MOSFET and realizes a steep on / off characteristic exceeding the theoretical value of the bulk device.

[0016]

1 is a diagram showing an embodiment of the present invention, showing an example of a MOS type field effect transistor having a thin film SOI structure according to the present invention.

In the figure, 11 is a p-type channel region, 13 is an element isolation oxide film, 15 is a second gate electrode, 16 is a buried oxide film, 17 is a silicon supporting substrate, 19 is a first gate electrode,
24 is an n-type source diffusion layer, 25 is an n-type drain diffusion layer,
27 is a p-type drain diffusion layer of the second MOSFET, 28 is an interlayer insulating film, 29 is a substrate contact, 30 is a source contact, 31 is a drain contact, and 32 is an inversion layer.

In this embodiment, the n-type source diffusion layers 24, p
The first thin film SOI structure MO is formed by the type channel region 11, the n type drain diffusion layer 25, and the first gate electrode 19.
The SFET is formed, and the p-type channel region 11, the n-type source diffusion layer 24, the p-type diffusion layer 27, and the second gate electrode 15 form a second thin film SOI structure MOSFET.

When the voltage of the second gate electrode 15 is changed in synchronization with the on / off of the first gate electrode 19, the channel resistance of the second thin film SOI structure MOSFET can be changed. As a result, holes generated in the channel region 11 of the first thin film SOI structure MOSFET due to impact ionization cause the first thin film SOI structure MOSF to be generated by the voltage applied to the second gate electrode 15.
Inversion layer 32 formed on the bottom of the source diffusion layer 24 of ET
Through to the drain diffusion layer 27 of the second thin film SOI structure MOSFET.

As a result of the above, since it is possible to prevent the accumulation of holes generated in the channel region 11 of the first thin film SOI structure MOSFET by impact ionization, it is possible to prevent the parasitic bipolar operation of the first thin film SOI structure MOSFET. In addition to being able to suppress, it is possible to realize a steep on / off characteristic that exceeds the theoretical value of the bulk FET.

Next, a method of manufacturing the thin film SOI structure MOS type field effect transistor shown in FIG. 1 will be described step by step. [Step 1, FIG. 2] On the p-type element formation silicon substrate 11, grooves 12a and 1 for element isolation having a depth of 0.1 to 0.2 μm are formed.
2b is formed.

The trenches 12a and 12b are filled with an oxide film to form element isolation oxide films 13a and 13b. [Step 2, FIG. 3] The gate oxide film 14 having a thickness of 200 to 500 Å is formed by thermally oxidizing the surface of the p-type element formation silicon substrate 11.
To form.

Polycrystalline silicon is deposited on the surface by CVD to a thickness of 0.2 to 0.5 μm, and then patterned to form a second gate electrode 15. [Step 3, FIG. 4] A silicon oxide film 16 having a thickness of 1 to 5 μm is deposited on the entire surface by a CVD method.

[Step 4, FIG. 4, FIG. 5] CVD-SiO ₂
The film 16 is polished to a thickness of 0.5 to 1 μm from the surface of the element formation silicon substrate 11.

[Step 5, FIG. 5, FIG. 6] CVD-SiO ₂
After the surface of the film 16 is brought into contact with the surface of the silicon supporting substrate 17, heat treatment at 1000 to 1200 ° C. is applied to bond the both.

The element-formed silicon substrate 11 is polished from the back surface to form a thin film. At this time, the element isolation oxide film 13a,
13b is used as a stopper. [Step 6, FIG. 7] Thinned element-formed silicon substrate 1
The surface of No. 1 is thermally oxidized to form a gate oxide film 18 having a thickness of 200 to 500Å.

Polycrystalline silicon or refractory metal citrate is deposited on the surface to a thickness of 1000 to 3000 Å by the CVD method and then patterned to form the first gate electrode 1.
9 is formed.

Using the first gate electrode 19 as a mask, P
(Phosphorus) is ion-implanted at a dose of about 10 ¹³ cm ^-2 to form the low-concentration diffusion layers 20 and 21 of the LDD structure. [Step 7, FIG. 8] After depositing a silicon oxide film on the entire surface to a thickness of about 0.2 μm, sidewalls 22 are formed by RIE.

After applying a resist on the entire surface, patterning is performed so that a portion where the first thin film SOI structure MOSFET is formed is exposed to form a first resist 23. Using the first resist 23 as a mask, As (arsenic) is added 10 ¹⁵
Ions are implanted with a dose amount of about cm ⁻² to form high-concentration diffusion layers 24 and 25 of LDD structure.

At this time, if necessary, the second thin film SO
In order to control the threshold value Vth of the I-structure MOSFET, a dose amount of 10 is formed in the deep portion of the device forming silicon substrate 11.
^By implanting B (boron) ions of about ¹³ to 10 ¹⁴ cm ^-2 or by making the ion implantation acceleration energy of As extremely low, the high-concentration diffusion layers 24 and 25 are formed on the element forming silicon substrate 1.
Do not reach the depth of 1.

The first resist 23 is peeled off. [Step 8, FIG. 9] After applying a resist on the entire surface, patterning is performed so as to cover a portion where the first thin film SOI structure MOSFET is formed to form a second resist 26.

Using the second resist 26 as a mask, B (boron) is ion-implanted at a dose amount of about 10 ¹⁵ cm ^-2 ,
Drain diffusion layer 2 of second thin film SOI structure MOSFET
Form 7.

The second resist 26 is peeled off. [Step 9, FIG. 1] After depositing the interlayer insulating film 28 on the entire surface,
A via hole is opened at a predetermined position.

After depositing Al (aluminum) on the entire surface, patterning is performed to form a substrate contact 29, a source contact 30, and a drain contact 31. Through the above steps, the MOS field effect transistor having the thin film SOI structure according to the present invention shown in FIG. 1 is completed.

Next, another embodiment of the present invention shown in FIG. 10 will be described. In FIG. 10, 11 is a p-type channel region,
13 is an element isolation oxide film, 15 is a second gate electrode, 16 is a buried oxide film, 17 is a silicon support substrate, 19 is a first gate electrode, 24 is an n-type source diffusion layer, 25 is an n-type drain diffusion layer, 27 is a p-type drain diffusion layer of the second MOSFET, 28 is an interlayer insulating film, 33 is a source substrate contact,
34 is a drain contact.

In this embodiment, the first thin film SOI structure MO is used.
Source diffusion layer 24 of SFET and second thin film SOI
The contact of the drain diffusion layer 27 of the structure MOSFET is taken as a common source substrate contact 33 by using one via hole. This is the source of the first thin film SOI structure MOSFET and the second thin film SOI structure MOS
This is effective when the drain of the FET can be kept at the same potential, and the area occupied by the aluminum wiring can be reduced.

In the above embodiments, the case where the second gate electrode 15 is formed in the buried oxide film 16 below the source diffusion layer 24 of the first thin film SOI structure MOSFET has been described. 15 may be formed under the entire element formation region or under the source diffusion layer 24 and the drain diffusion layer 25 as long as it is separated so that it can operate independently of other transistors.

The second thin film SOI structure MOSFET
The drain diffusion layer 27 may be formed not only in the area adjacent to the source diffusion layer 24 but also in the area adjacent to the drain diffusion layer 25, or in both areas.

[0039]

According to the present invention, the MO of the thin film SOI structure is
In the S-type field effect transistor, it is possible to suppress the occurrence of parasitic bipolar operation and realize a sharp on / off characteristic exceeding the theoretical value of the bulk FET.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing one step of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a diagram showing one step of a method of manufacturing a semiconductor device according to the present invention.

FIG. 4 is a diagram showing a step of the method of manufacturing the semiconductor device according to the invention.

FIG. 5 is a diagram showing a step of the method of manufacturing the semiconductor device according to the invention.

FIG. 6 is a diagram showing a step of the method of manufacturing the semiconductor device according to the invention.

FIG. 7 is a diagram showing a step of the method of manufacturing the semiconductor device according to the invention.

FIG. 8 is a diagram showing a step of the method of manufacturing the semiconductor device according to the invention.

FIG. 9 is a diagram showing a step of the method of manufacturing the semiconductor device according to the invention.

FIG. 10 is a diagram showing another embodiment of the present invention.

FIG. 11 is a diagram showing a conventional example.

FIG. 12 is a diagram showing drain current-gate voltage characteristics.

[Explanation of symbols]

 11 p-type channel region 13 element isolation oxide film 15 second gate electrode 16 buried oxide film 17 silicon support substrate 19 first gate electrode 24 n-type source diffusion layer 25 n-type drain diffusion layer 27 p-type drain diffusion layer of second MOSFET 28 interlayer insulating film 29 substrate contact 30 source contact 31 drain contact 32 inversion layer

Claims (3)

[Claims] 1. A single conductivity type channel region, and a source diffusion layer and a drain diffusion layer of opposite conductivity type are formed in a single crystal semiconductor layer formed on an insulating film, and a first gate is formed on the channel region. MO of thin film SOI structure with electrodes
An S-type field effect transistor, comprising: a diffusion layer having a conductivity type opposite to that of a source / drain diffusion layer, formed in the single crystal semiconductor layer in contact with the source diffusion layer and / or the drain diffusion layer. A second gate electrode formed in the insulating film below the source diffusion layer and / or the drain diffusion layer. 2. The diffusion layer having a conductivity type opposite to that of the source / drain diffusion layer, which is formed in contact with the source diffusion layer and / or the drain diffusion layer, and the source diffusion layer and / or A semiconductor device, wherein the drain diffusion layer and the drain diffusion layer are contacted using the same via hole. 3. A method of manufacturing a MOS field effect transistor having a thin film SOI structure, which comprises forming a groove for element isolation in a semiconductor substrate of one conductivity type,
A step of forming an element isolation oxide film by embedding an oxide film in the groove; a step of forming a gate oxide film on the substrate surface, then depositing a polycrystalline semiconductor and patterning it to form a second gate electrode. , A step of depositing an insulating film on the entire surface and then flattening it to a predetermined thickness, a step of adhering a semiconductor substrate to a supporting substrate with the surface of the flattened insulating film facing down, the element isolation oxide film Using the as a stopper, the step of polishing the semiconductor substrate from the back surface to thin the film, and after forming the gate oxide film on the surface, depositing a polycrystalline semiconductor or an alloy of refractory metal and semiconductor and patterning A step of forming a gate electrode, a step of forming a source diffusion layer and a drain diffusion layer by performing ion implantation using the first gate electrode as a mask, and a step of forming the first gate electrode, the source diffusion layer and the drain diffusion layer. After covering with a resist, ions are implanted using the resist as a mask to contact the source diffusion layer and / or the drain diffusion layer to form a diffusion layer having a conductivity type opposite to that of the source / drain diffusion layer. A method of manufacturing a semiconductor device, comprising: