JPH053294A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve element characteristics and to realize high integration and fast speed by realizing compactness of the resistance element connected to a field-effect transistor and a source of the field-effect transistor and by reducing resistance of a power source wiring part whereto the field-effect transistor source and the resistance element are connected. CONSTITUTION:Insulating films 16, 17 are formed which cover an upper side and a side of a wiring layer which constitutes a gate electrode 6a and a lead out electrode 6b whereto a drain is connected. A resistance layer 12 which is formed of polysilicon is formed through the insulating films 16, 17, and a silicide alloy layer 20 are formed in a power supply wiring part 13 at one end of the resistance layer 12 and a drain; thereby compactness and high performance are realized, and fast speed and high integration of a semiconductor integrated circuit is realized in this way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit using a resistance load type N channel MOSFET.

[0002]

2. Description of the Related Art As semiconductor integrated circuits have become faster and more highly integrated, the dimensions of constituent elements have been miniaturized.

Conventional resistance load type N-channel MOSFET
A circuit using is described with reference to FIG.

The output signal line Out is an adjacent N channel M
It is composed of first polysilicon that forms the gate electrode of the OSFET.

V _CC is a power supply line, and I is an input signal line.

A resistance load type N channel MO according to the prior art
A semiconductor integrated circuit using SFET is shown in FIG.
This will be described with reference to (c).

First, as shown in FIG. 4A, a thickness of 150 to 350 A is formed on a semiconductor substrate 1 in a predetermined transistor region including a P well 2, a field insulating film 3 for element isolation, and a channel stopper 4 for preventing inversion. The gate oxide film 5 made of the silicon oxide film is selectively formed.

Next, first polysilicon is deposited on the entire surface, and, for example, phosphorus is thermally diffused and then selectively etched to form the gate electrode 6a of the transistor and the output signal line Out.
The lead-out wiring 6b is formed. At the same time, an N-type diffusion layer 7 is formed by being doped with polysilicon.

Next, as shown in FIG. 4 (b), phosphorus, which is an N-type impurity, is selectively ion-implanted using the gate electrode 6a as a mask to form a low concentration source / drain 8 of 1 × 10 ¹⁸ cm ^-3. Form.

A silicon oxide film having a thickness of 100 to 300 nm is vapor-deposited on the entire surface, and then etched back by anisotropic etching to form a gate electrode 6a and a lead wiring 6.
A side wall oxide film 9 made of a silicon oxide film is formed on the side surface of b.

Next, the gate electrode 6a and the sidewall oxide film 9 are formed.
Is used as a mask to selectively select N in the N-channel MOS planned region.
Type impurity of arsenic is ion-implanted at 1 × 10 20 cm -3
Forming a high-concentration second source and drain 10.

Next, a first interlayer insulating film 11 is deposited on the entire surface, and openings are selectively formed on the source or drain of the transistor and the lead wiring 6b of the output signal line.

Next, the high resistance load element R and the power supply wiring V
_In order to form _CC , second polysilicon is deposited on the entire surface and then selectively etched to form a pattern of the resistor 12 and the power supply wiring 13.

After that, arsenic is ion-implanted only in the region of the power supply wiring V _{CC using} the silicon nitride film 14 selectively covering the region of high resistance R as a mask. The resistance of one end of the resistor 12 is lowered to form the power supply wiring 13.

Next, as shown in FIG. 4 (c), an electrode made of, for example, aluminum is formed as a highly conductive metal film by depositing a second interlayer insulating film 15 and then selectively forming openings. 21 is formed to complete the element portion.

[0016]

In order to speed up and highly integrate a semiconductor integrated circuit, it is essential to reduce the element size and improve the performance.

In order to reduce the size of the field effect transistor, it is necessary to reduce the area of the element region, shallow the junction between the source and the drain, and reduce the resistance. In the resistance load element, it is necessary to make the resistance portion as short as 2 μm or less to reduce the size.

It is necessary to miniaturize the power supply wiring connected to the resistance element and further reduce the layer resistance of the wiring to 1 to 10 Ω / □.

The width of the resistance element is W (μm) and the length is L (μm).
m) and the layer resistance is ρ _S (MΩ / □), the resistance value of the resistance element is represented by R (MΩ) = L / W × ρ _S.

However, in the conventional semiconductor integrated circuit, diffusion occurs that shortens the length of the resistance element from the power supply wiring portion connected to one end of the resistance element in which the impurities are diffused.

When the diffusion distance in the lateral direction is α (μm), R (MΩ) = (1−α) / W × ρ _S.

Generally, the power consumption of a semiconductor integrated circuit is constant even if the speed is increased and the integration is increased. For example, if the integration degree is increased by 4 times, the resistance value needs to be increased by 1.25 times according to a simple calculation. There is.

Therefore, in the method of simply reducing the length L and the width W of the resistance element, the manufacturing tolerance of the resistance element becomes stricter by the amount of the lateral diffusion α, and the yield decreases.
There is a problem that the semiconductor integrated circuit itself cannot be realized.

Further, in order to miniaturize the field effect transistor, the size of the element region must be reduced and the junction between the source and the drain must be shallow. As a result, there has been a problem that the layer resistance of the source and drain is increased and the performance of the field effect transistor is degraded.

As described above, in the prior art, there has been a major obstacle to speeding up and highly integrating the semiconductor integrated circuit.

[0026]

A semiconductor integrated circuit according to the present invention comprises a plurality of field effect transistors and a plurality of resistance elements on a semiconductor substrate, and the gate electrode of the field effect transistor is made of first polysilicon. The resistance element is made of second polysilicon, the drain of the first field effect transistor is connected to the gate electrode of the second field effect transistor and the resistance element, and the gate of the second field effect transistor is formed. The first polysilicon forming the electrode is connected to the drain of the first field effect transistor, an insulating film covering the upper surface and the side surface of the first polysilicon is formed, and the first polysilicon is formed via the insulating film. Second polysilicon forming a resistance element is formed on the first polysilicon, and one end of the second polysilicon has the first polysilicon. A silicide layer made of a refractory metal is formed on the other end of the second polysilicon and the source of the first field effect transistor, the silicide layer being connected to the drain of the first field effect transistor along the capacitor. It is a thing.

[0027]

EXAMPLE FIG. 1A shows a first example of the present invention.
This will be described with reference to (c).

First, as shown in FIG. 1A, a P well 2, an element isolation field insulating film 3, and a channel stopper 4 are selectively formed on a semiconductor substrate 1 to isolate an element region. A gate insulating film 5 made of a silicon oxide film having a thickness of 15 to 25 nm is formed in the element region.

Next, the gate insulating film 5 in the source region is selectively etched, and then phosphorus-doped first polysilicon and a vapor-grown oxide film having a thickness of 100 to 500 nm are deposited on the entire surface. Next, the vapor grown oxide film and the first polysilicon are selectively etched to form the lead wiring 6b connected to the gate electrode 6a and the source or the drain, and then the insulating film 16 is formed thereon.

Next, arsenic, which is an N-type impurity, is ion-implanted into the source and drain regions using the gate electrode 6a as a mask to form a high-concentration N-type source and drain 10 of 1 × 10 ₂₀ cm _-3 .

Next, an oxide film having a thickness of 300 to 1000 nm is vapor-deposited on the entire surface, and then the entire surface is etched back by anisotropic etching to form a side wall oxide film 17 on the side surfaces of the gate electrode 6a and the lead wiring 6b. Form.

Next, as shown in FIG. 1B, a thin silicon oxide film 18 having a thickness of 20 nm is formed on the source and drain regions, and then the thin silicon oxide film 18 on the source or drain region is formed. Portions are selectively etched to form openings 19.

A second polysilicon is deposited on the entire surface and selectively etched so as to cover the lead wiring 6b and the opening 19 to form a resistor 12 and a power supply wiring 13. Next, the silicon nitride film 14 is selectively formed only in the resistance region.

Next, as shown in FIG. 1C, the thin silicon oxide film 18 in the source and drain regions is removed, and titanium, which is a refractory metal having a thickness of 100 nm, is deposited on the entire surface. Next, annealing is performed at 600 ° C. to form the titanium silicide layer 20 in the source / drain regions and the power supply wiring region 13 in a self-aligned manner, and then excess unreacted titanium is removed.

Next, a second interlayer insulating film 15 is deposited and then openings are selectively formed, and an electrode 21 made of, for example, aluminum is formed as a highly conductive metal film to complete the element portion.

In this embodiment, since the impurity is not ion-implanted into the power supply wiring connected to the resistor, the distance α for diffusing the impurity in the resistance layer is set to 0 μm, and the resistance element is easily shortened. be able to.

By forming a silicide layer on the power supply wiring, the layer resistance can be reduced to around 5Ω / □. Similarly, since the silicide layer is formed also in the source and drain regions, the layer resistance is reduced to around 5Ω / □.

As a result, the field effect transistor and the resistance element can be miniaturized and improved in performance. We were able to realize high speed and high integration of semiconductor integrated circuits.

Next, a second embodiment of the present invention will be described with reference to FIGS.

The steps up to the point of forming the gate electrode 6a and the lead wiring 6b in the source region on the semiconductor substrate 1 are the same as in the first embodiment.

Next, as shown in FIG. 2A, phosphorus is ion-implanted by using the gate electrode 6a as a mask to implant 1 × 10 ¹⁸ c.
A first source / drain 8 having a low concentration of m ⁻³ is formed. Next, a 100-300 nm first vapor-phase oxide film is deposited on the entire surface and then etched back by anisotropic etching to form a sidewall oxide film 9 on the side surfaces of the gate electrode 6a and the lead wiring 6b. Then, using the gate electrode 6a and the sidewall oxide film 9 as a mask, arsenic is ion-implanted to form 1 ×.
A second source-drain 10 having a high concentration of 10 ²⁰ cm ⁻³ is formed. Due to the two-layer structure of the first source / drain 8 and the second source / drain 10, generation of hot carriers is suppressed and a highly reliable field effect transistor is realized.

Next, a second vapor growth oxide film having a thickness of 500 to 1000 nm is deposited on the entire surface, and then etched back by anisotropic etching to form a second film on the side surface of the gate electrode 6a.
Side wall oxide film 17 is formed.

Next, as shown in FIG. 2B, a second polysilicon is deposited on the entire surface and is selectively etched to cover the drain region sandwiched between the gate electrode 6a and the lead-out wiring 6b with a resistor. 12 and power supply wiring 13 are formed. Next, the silicon nitride film 14 is selectively formed only in the region of the resistor 12.

Next, as shown in FIG. 2C, the silicide alloy layer 20 is formed in a self-aligned manner on the power supply wiring 13 and the source region in the same manner as in the first embodiment. And second
The interlayer insulating film 15 and the electrode 21 are formed to complete the element portion.

In the present invention, the connection hole between the drains 8 and 10 of the first field effect transistor and the resistor 12 is formed by the gate electrode 6a of the first field effect transistor and the gate extraction electrode 6b of the second field effect transistor. Form consistently. The size of the connection hole can be reduced to 1 μm or less.

Since the drain region can also be miniaturized, the size can be further reduced as compared with the first embodiment, and high integration of the semiconductor integrated circuit can be achieved.

[0047]

EFFECT OF THE INVENTION An insulating film is provided to cover the upper surface and the side surface of the first polysilicon forming the gate electrode of the field effect transistor.

Further, it is provided with a second polysilicon forming a resistance element via an insulating film. One end of the second polysilicon is connected to the drain, and a silicide alloy layer is formed in a self-aligned manner on the power supply wiring portion and the source region at the other end.

Therefore, a silicide alloy layer can be simultaneously formed in the power supply wiring portion and the source region, and the layer resistance can be reduced to 5Ω / □ or less.

Moreover, since the power supply wiring portion is not doped with impurities, the impurities do not diffuse from the power supply wiring portion to the resistance portion. The resistance length can be shortened to 2 μm or less.

As described above, the performance of the field effect transistor can be improved, and the miniaturization and miniaturization can be achieved.
Further, the resistance element / power supply wiring region can be downsized, and high speed and high integration of the semiconductor integrated circuit can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.

FIG. 2 is a cross-sectional view showing a second embodiment of the present invention in process order.

FIG. 3 is a circuit diagram of a conventional resistance load type N-channel MOSFET.

FIG. 4 is a sectional view showing a semiconductor integrated circuit according to a conventional technique in order of steps.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 P-type well 3 Field oxide film 4 Channel stopper 5 Gate insulating film 6a Gate electrode 6b Lead wiring 7 N-type diffusion layer 8 First low-concentration source-drain 9 Source-drain 2 layer structure Side wall oxide film 10 Second source-drain 11 First interlayer insulating film 12 Resistor made of second polysilicon 13 Power supply wiring 14 Silicon nitride film 15 Second interlayer insulating film 16 Interlayer insulating film formed on gate electrode 17 Sidewall oxide film to be an interlayer insulating film 18 Thin silicon oxide film 19 Opening 20 Silicide alloy layer 21 Electrode

Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (1)

Claim: What is claimed is: 1. A semiconductor substrate comprising a plurality of field effect transistors and a plurality of resistance elements, wherein the gate electrode of the field effect transistor is made of first polysilicon, and the resistance elements are Made of a second polysilicon, the first
The gate electrode of the second field effect transistor and the resistance element are connected to the drain of the field effect transistor of
The first polysilicon forming the gate electrode of the second field effect transistor is connected to the drain of the first field effect transistor, and an insulating film covering the upper surface and the side surface of the first polysilicon is formed. Second polysilicon forming a resistance element is formed on the first polysilicon via the insulating film, and one end of the second polysilicon is formed on the first polysilicon along the first polysilicon. 1. A semiconductor integrated circuit connected to the drain of a first field effect transistor, wherein a silicide layer made of a refractory metal is formed on the other end of the second polysilicon and the source of the first field effect transistor.