JPH0530084B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital filter that obtains a binary output digital signal by adding frequency characteristics to a binary input digital signal.

Conventional configurations and their problems Recently, the digitalization of home VTRs, especially the servo system, has been active, and digital servo systems have already been developed.
It has been commercialized and introduced as an IC (integrated circuit). The aim of this digitalization is to reduce the number of adjustment parts and peripheral parts, reduce power consumption, improve reliability, and support multi-functionality, and a fairly large scale digitalization is being planned. However, only the phase compensation circuit (hereinafter referred to as a filter) that determines the characteristics of a servo system such as a rotary servo system is still composed of a resistor and a large electrolytic capacitor.

As a conventional example of such a filter, an analog integration circuit is shown in FIG. FIG. 2 is a waveform diagram for explaining the operation.

The components of the analog integrating circuit are an operational amplifier 1, an input resistor 2, and a feedback capacitor 3. now,
When a potential difference occurs between input voltages E ₁ and E ₂ , input resistance 2
A current flows through the capacitor 3, and the output voltage E ₀ changes. The potential of the output voltage E ₀ drops when E ₁ > E ₁ (~t ₁ , t ₄ ~ _{t 5} ), and stops when E ₁ = E ₂ (t ₁ ~ t ₂ , t ₅ ~) However, when E ₁ <E ₂ , the potential increases (t ₂ to _{t 3} ). The transfer function G(s) of this circuit is G(s)=1/ST ₁ ...(1) However, T ₁ = C ₁ R ₁ , C ₁ is the capacitance of the feedback capacitor 3, and R ₁ is the input resistance 2. is the resistance value of That is, it functions as an integral element.

In Figure 3, a feedback resistor 4 is added to the components in Figure 1, and the transfer function Gs is G(s) = 1 + ST ₂ /ST ₁ ... (2) However, T ₁ = C ₁ R ₁ , T ₂ = C ₁ R ₂ , R ₂ is the feedback resistor 4
is the resistance value of When formula (2) is transformed, it becomes G(s)=1/ST ₁ +T ₂ /T ₁ (3), which has an integral element and a proportional element.

Note that since the magnitude of the current flowing through the input resistor 2 is proportional to the potential difference between the input voltages E ₁ and E ₂ , charging and discharging of the charge in the feedback capacitor 3 is also proportional. However,
The slope of the potential of the output voltage E ₀ shown in Fig. 2 is E ₁ , E ₂
It changes in proportion to the potential difference between.

In addition, in the specific circuit examples shown in FIGS. 1 and 3,
Input voltage E ₁ is an input analog signal, input voltage E ₂ is a reference analog signal, output voltage E ₀ is an output analog signal, and the output analog signal is a signal with integral or proportional integral characteristics added to the input analog signal. .

When integrating the integral circuit in Figure 1 and the proportional + integral circuit in Figure 3 explained above, the operational amplifier 1
3 input/output pins and 2 to 3 external CR components
There was a problem that the number of external parts and pins could not be reduced.

Purpose of the Invention The present invention solves the above-mentioned conventional problems.
The object of the present invention is to provide a digital filter in which all components are digitized.

Structure of the Invention The present invention includes a reference signal generating means for generating and outputting an N-bit (N is a natural number) reference digital signal, and a means for comparing the N-bit input digital signal with the reference digital signal to determine the magnitude thereof. a first switching signal representing _" large" and a second switching signal representing "small";
a frequency dividing means for outputting a number of pulses proportional to the absolute value of the difference between the input digital signal and the reference digital signal for each unit period, and one of the two switching signals; reversible counting means which switches the up counting direction with one and the down counting direction with the other, counts the output of the frequency dividing means, and obtains an output digital signal of M bits (M is a natural number). This digital filter is characterized by the following, and a digital integration circuit can be realized with a relatively simple configuration.

The present invention also provides a reference signal generating means for generating and outputting an N-bit (N is a natural number) reference digital signal, and a means for comparing the N-bit input digital signal with the reference digital signal to determine whether it is large or small. ”
a first switching signal representing "small" and a second switching signal representing "^small"; a frequency dividing means for outputting a number of pulses proportional to the absolute value of the difference from the reference digital signal; one of the two switching signals switches an up counting direction and the other switches a down counting direction; reversible counting means for counting the output of the frequency dividing means and obtaining a digital output of M bits (M is a natural number); multiplication means for multiplying the input digital signal by a coefficient; an output of the reversible counting means; and an output of the multiplication means. This digital filter is characterized in that it is equipped with an addition or subtraction means for adding or subtracting and obtaining an output digital signal, and it is possible to realize a digital proportional-integral circuit with a relatively simple configuration.

As described above, by completely digitalizing the device, external components such as capacitors and resistors can be eliminated, and by incorporating the circuit into the IC, the number of input and output pins can also be reduced.

DESCRIPTION OF EMBODIMENTS FIG. 4 shows a first embodiment of the present invention, and FIG. 5 is an operating waveform diagram thereof.

In Fig. 4. 5 is N bits (N is a natural number)
a reference signal generating means for generating an N-bit reference digital signal based on the input digital signal;
6 is a size discrimination means, 7 is a frequency dividing means, 8 is a reversible counting means (referred to as an up-down counter),
_D1 is a binary input digital signal, _D2 is a reference digital signal generated by the reference signal generating means 5, _D3 is the output of the up-down counter 8, _S1 ,
S ₂ is the digital signal D ₁ of the size determining means 6.
An output representing the largeness or smallness of _D2 (this output is a switching signal that switches the up/down counting direction of the up-down counter 8), _S3 is a clock pulse, and _S4 is the output of the frequency dividing means 7. . The binary input digital signal R ₁ and the reference digital signal D ₂ are inputted to a size determining means 6 for size determination. The outputs S ₁ and S ₂ corresponding to the magnitude of the digital signals D ₁ and D ₂ of the magnitude determining means 6 are used as inputs for switching the counting direction of the up-down counter 8, and the outputs of the frequency dividing means 7
_S4 is used as a clock input, and an M-bit (M is a natural number) output digital signal _D3 is obtained from the up-down counter 8. The frequency dividing means 7 divides the input clock pulse S ₃ to create a number of pulses proportional to the absolute value of the difference between the reference digital signal D ₂ and the input digital signal D ₁ and outputs them. It is used as a clock input. Here, the reference digital signal is
The purpose of creating a number of pulses proportional to the absolute value of the difference between D ₂ and the input digital signal D ₁ is to make the output digital signal D ₃ proportional to the input digital signal D ₁ . This operation corresponds to the fact that the current flowing through the input resistor 2 in the conventional example is proportional to the potential difference between _E1 and _E2 .

To explain the operation in FIG. 4 with reference to FIG. 5, the magnitude determining means 6 determines whether the input digital signal D ₁ and the reference digital signal D ₂ are large or small, and whether the value of D ₁ is larger or smaller than that of D ₂ . The operation of the up-down counter 8 is switched between up and down (or down and up). From the relationship between D ₁ and D ₂ , D ₁
> D ₂ (or D ₁ < D ₂ ), up count (t ₂ ~
t ₃ ), if D ₁ = D ₂ , stop counting (t ₁ ~ _{t 2} , t ₃ ~ _{t 4} ,
t ₅ ), and if D ₁ < D ₂ (or D ₁ > D ₂ ), the count is down (~t ₁ , t ₄ ~ _{t 5} ). Note that the operation of the output D ₃ of the up-down counter 8 shown in the figure is _as follows when D ₁ ≠ D _2
This shows a specific case where the absolute value of the _{difference between} changes. As a result, the first embodiment of the present invention shown in FIG. 4, which is completely digitalized, makes it possible to realize a digital filter having the function of an integral element. Time constant corresponding to equation (1)
T ₁ is T ₁ = 1/fck ... (4) However, fck is the lowest frequency of the clock pulse S4 which is the output of the frequency dividing means 7, that is, when the absolute value of the difference between D ₂ and D ₁ is 1. is the frequency of It can be found as

FIG. 6 shows a specific circuit example of the up-down counter 8 shown in FIG. 4. 9 is a clock pulse input terminal;
0 is an up signal input terminal, 11 is a down signal input terminal, and 12 to 15 are digital signal output terminals. A composite gate consisting of AND gates 16, 17 and OR gate 18 and a flip-flop 19 form a unit bit of an up-down counter, and the up-down counter 8 can be constructed by connecting the required number of bits. When the input terminal 10 is "H" and the input terminal 11 is "L", this circuit operates as an up counter that uses the Q-bar output of the previous stage flip-flop as the clock input, and when the input terminal 10 is "L" and the input terminal 11 is "L". When it is "H", it operates as a down counter that receives the Q output of the previous stage flip-flop as an input. Further, when both input terminals 10 and 11 are at "L", no clock is input to each flip-flop and the counter stops. Digital signal outputs can be obtained from output terminals 12-15.

FIG. 7 shows a specific circuit example of the frequency dividing means 7 shown in FIG. 4, and FIG. 8 is a waveform diagram for explaining its operation.

In FIG. 7, 20 is the input terminal of the clock pulse _S3 , and 21 to 24 are the LSB of the absolute value of the difference between the input digital signal _D1 and the reference digital signal _D2 .
MSB input terminal, 25 is the output terminal of the divided clock pulse _S4 , 26 to 29 are flip-flops forming a frequency division counter, 30 is the clock pulse
Inperter that inverts S ₃ , 31 to 34 are D ₁ and D ₂
An AND gate 35 decodes the absolute value of the difference between the outputs of the inverter 30 and the flip-flops 26 to 29; 35 is an AND gate 31 to 3;
This is an OR gate that calculates the sum of the outputs of 4.

The operation shown in FIG. 7 will be explained with reference to FIG. _S3 is a clock pulse input to frequency division counters 26-19, and _Q1 - _Q4 are Q outputs, respectively. _G1〜
G ₂ is when input terminals 21 to 24 are all “H”
These are the outputs of AND gates 31-34. Now, assuming that the reference digital signal D ₂ is "1000" and the input digital signal D ₁ is "1101" or "0011", the absolute value of the difference between D ₁ and D ₂ |D ₁ −D ₂ | is "0101". ”
Therefore, AND gates 31 and 33 open, and 3
2 and 34 are closed, and five clock pulses can be output as the output _S4 of the OR gate 35 in one cycle of the frequency division counter. That is, a number of pulses proportional to the absolute value |D ₁ −D ₂ | of the difference between D ₁ and D ₂ can be obtained as the frequency-divided output S ₄ .

Here, the frequency dividing means 7 will be explained more generally.
When the number of bits of the reference digital signal and the input digital signal is N, the number of bits of the frequency division counter needs to be N bits. Then, the clock pulse _S3 and the output of the frequency division counter are decoded (AND
gates 31 to 34), 2 ^A pulses (A = 0, 1, ..., N-1) of N types (G ₁ to G ₄ ) are created, and the N types of pulses are selected (AND gates 31 to 34 and OR gate 35) according to the absolute value of the difference (|D ₁ −D ₂ |) to form an output S ₄ configuration. . As a result, the frequency dividing means takes 2 _N periods of clock pulses as a unit period, and outputs a number of pulses in proportion to the absolute value of the difference between the input digital signal and the reference digital signal for each unit period. be able to.

FIG. 9 shows a second embodiment of the present invention, in which multiplication means 36 and addition means 37 are added to the first embodiment shown in FIG. That is, the output D ₄ obtained by multiplying the input digital signal D ₁ by the coefficient K in the multiplication means 36 is added to the output D ₃ of the up-down counter 8 in the addition means 37, and the obtained output D ₅ is used as the output digital signal. It is. This makes it possible to realize a proportional+integral circuit in which a proportional element is added to the integral element of the first embodiment. T ₂ /T ₁ in equation (3) can be obtained as T ₂ /T ₁ =K (5).

Note that the multiplication means 36 does not require a particularly complicated multiplication circuit as long as it is a power of 2 multiplication, and can be handled by simply shifting the bits of the input digital signal _D1 . In addition, when the polarity of the up-down counter 8 is negative, that is, when D ₁ < D ₂ , the up-down counter 8 counts up;
When counting down when D ₁ >D ₂ , the addition means 37 may be used as a subtraction means to subtract D ₄ from D ₃ . Further, the reference signal generating means 5 does not require any particular gate circuit, and simply changes "H" to "L".
All that is required is to generate a fixed binary digital signal.

Effects of the Invention The digital filter of the present invention can configure an integrating circuit with a relatively simple configuration using only a reference signal generation means, a magnitude discrimination means, a frequency division means, and a reversible counting means (up-down counter), and further includes a multiplication means,
By using addition means (or subtraction means), a proportional + integral circuit can be realized, no peripheral components are required, and the circuit can be used as an internal IC circuit, eliminating the need for pins, which has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one example of a conventional filter, FIG. 2 is an operating waveform diagram thereof, FIG. 3 is a block diagram showing another example of a conventional filter, and FIG. 4 is a diagram of a digital filter of the present invention. FIG. 5 is a block diagram showing one embodiment, FIG. 5 is an operation waveform diagram thereof, FIG. 6 is a specific circuit diagram showing one example of an up-down counter, and FIG.
FIG. 8 is a specific circuit diagram showing one example of the frequency dividing means, FIG. 8 is an operating waveform diagram thereof, and FIG. 9 is a block diagram showing a second embodiment of the digital filter of the present invention. 5... Reference signal generating means, 6... Size determining means, 7... Frequency dividing means, 8... Up/down counter, 36... Multiplying means, 37... Adding means (or subtracting means).

Claims (1)

[Claims] 1. Reference signal generating means for generating and outputting a reference digital signal of N bits (N is a natural number); a size discrimination means for outputting a first switching signal representing "large" and a second switching signal representing "small"; a unit period of ^2N clock pulses;
frequency dividing means for outputting a number of pulses proportional to the absolute value of the difference between the input digital signal and the reference digital signal for each unit period; and switching the up counting direction of one of the two switching signals; On the other hand, a digital filter comprising reversible counting means for switching the down counting direction and counting the output of the frequency dividing means to obtain an M-bit (M is a natural number) output digital signal. 2. a reference signal generating means for generating and outputting an N-bit (N is a natural number) reference digital signal; a switching signal indicating "small" and a second switching signal representing " ^small ";
frequency dividing means for outputting a number of pulses proportional to the absolute value of the difference between the input digital signal and the reference digital signal for each unit period; and switching the up counting direction of one of the two switching signals; on the other hand, reversible counting means for switching the down counting direction and counting the output of the frequency dividing means to obtain a digital output of M bits (M is a natural number); and multiplication means for multiplying the input digital signal by a coefficient; A digital filter comprising: an addition or subtraction means for adding or subtracting the output of the reversible counting means and the output of the multiplication means to obtain an output digital signal.