JPH0142434B2 - - Google Patents
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- Publication number
- JPH0142434B2 JPH0142434B2 JP58004481A JP448183A JPH0142434B2 JP H0142434 B2 JPH0142434 B2 JP H0142434B2 JP 58004481 A JP58004481 A JP 58004481A JP 448183 A JP448183 A JP 448183A JP H0142434 B2 JPH0142434 B2 JP H0142434B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- digital signal
- proportional
- down counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/64—Digital differential analysers, i.e. computing devices for differentiation, integration or solving differential or integral equations, using pulses representing increments; Other incremental computing devices for solving difference equations
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Pulse Circuits (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は２進数の入力デイジタル信号に比例積
分特性を付加した出力デイジタル信号を得るデイ
ジタル式比例積分回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital proportional-integral circuit that obtains an output digital signal by adding proportional-integral characteristics to a binary input digital signal.
従来例の構成とその問題点
第１図はアナログ式比例積分回路の従来例のブ
ロツク図、第２図はその動作説明に供する波形図
である。Configuration of Conventional Example and Its Problems FIG. 1 is a block diagram of a conventional example of an analog proportional-integral circuit, and FIG. 2 is a waveform diagram for explaining its operation.
アナログ式比例積分回路の構成要素は、オペア
ンプ１、入力抵抗２、帰還コンデンサ３、帰還抵
抗４である。今、入力電圧E1、E2に電位差が生
じると入力抵抗２に電流が流れ、帰還コンデンサ
３に電荷が充電されて出力電圧E0が変化する。
出力電圧E0は、E1＞E2のとき電位が下降（〜t1、
t4〜t5）し、E1＝E2のとき電位が停止（t1〜t2、t5
〜）し、E1＜E2のとき電位が上昇（t2〜t3）する
特性を持つている。この回路の伝達関数GSは、
ＧＳ＝１＋ST2／ST1 ……(1)
となる。但し、T1＝CR1、T2＝CR2、Ｃは帰還
コンデンサ３の容量、R1は入力抵抗２の抵抗値、
R2は帰還抵抗４の抵抗値、Ｓはラプラス演算子
である。(1)式を展開すると、
GS＝１／ST1＋T2／T1 ……(2)
となる。即ち、積分と比例の比例積分特性を有し
ている。 The components of the analog proportional-integral circuit are an operational amplifier 1, an input resistor 2, a feedback capacitor 3, and a feedback resistor 4. Now, when a potential difference occurs between the input voltages E 1 and E 2 , a current flows through the input resistor 2 , charges the feedback capacitor 3 , and the output voltage E 0 changes.
The potential of the output voltage E 0 decreases when E 1 > E 2 (~t 1 ,
t 4 to t 5 ), and the potential stops when E 1 = E 2 (t 1 to t 2 , t 5
), and has the characteristic that when E 1 <E 2 , the potential increases (t 2 -t 3 ). The transfer function GS of this circuit is GS=1+ST 2 /ST 1 (1). However, T 1 = CR 1 , T 2 = CR 2 , C is the capacitance of feedback capacitor 3, R 1 is the resistance value of input resistor 2,
R 2 is the resistance value of the feedback resistor 4, and S is the Laplace operator. When formula (1) is expanded, G S =1/ST 1 +T 2 /T 1 ...(2). That is, it has proportional-integral characteristics of integral and proportional.
なお、入力抵抗２を流れる電流の大きさは、入
力電圧E1、E2の電位差に比例するため、帰還コ
ンデンサ３の電荷の充放電も比例する。しかる
に、第２図に示す出力電圧E0の電位の傾きは、
E1、E2の電位差に比例して変化する。 Note that since the magnitude of the current flowing through the input resistor 2 is proportional to the potential difference between the input voltages E 1 and E 2 , charging and discharging of the charge in the feedback capacitor 3 is also proportional. However, the slope of the potential of the output voltage E 0 shown in FIG.
It changes in proportion to the potential difference between E 1 and E 2 .
係る比例積分回路を集積回路（ic）化する場合
には、入出力用のピン３個と外付けのCR部品３
個を必要とし、ic化による外付け部品の削減及び
ピン数削減の妨げとなつていた。また、アナログ
回路であるため電源電圧の変動を受け易い等の問
題点があつた。 When converting such a proportional-integral circuit into an integrated circuit (IC), three input/output pins and three external CR components are required.
This was an obstacle to reducing the number of external parts and pins required by converting to ICs. In addition, since it is an analog circuit, it has problems such as being susceptible to fluctuations in power supply voltage.
発明の目的
本発明は前記従来の問題点を解消するもので、
全ての構成要素をデイジタル化したデイジタル式
比例積分回路を提供するものである。Purpose of the Invention The present invention solves the above-mentioned conventional problems.
The present invention provides a digital proportional-integral circuit in which all components are digitalized.
発明の構成
本発明は、クロツクパルスを入力デイジタル信
号と所定値との差の絶対値に比例した周波数に分
周する分周手段と、前記入力デイジタル信号の最
上位の少なくとも１ビツトをアツプダウン信号入
力とし、前記分周手段の出力をクロツク入力とす
るアツプダウンカウンタと、前記入力デイジタル
信号に係数を乗じる乗算手段と、前記アツプダウ
ンカウンタの出力と前記乗算手段の出力とを加算
（減算）する加算（減算）手段とを具備し、前記
加算（減算）手段より出力デイジタル信号を得る
デイジタル式比例積分回路であり、全ての構成要
素をデイジタル化したため、外付け部品を不要に
できると共に、icの内蔵回路として用いることに
より入出力ピンも不要にできるものであり、さら
に電源電圧の依存性を皆無にできる等の特長を有
するものである。Structure of the Invention The present invention comprises frequency dividing means for dividing a clock pulse into a frequency proportional to the absolute value of the difference between an input digital signal and a predetermined value, and at least one most significant bit of the input digital signal as an up-down signal input. , an up-down counter which uses the output of the frequency dividing means as a clock input, a multiplication means which multiplies the input digital signal by a coefficient, and an addition (subtraction) which adds (subtracts) the output of the up-down counter and the output of the multiplication means. This is a digital proportional-integral circuit that obtains an output digital signal from the addition (subtraction) means, and since all the components are digitalized, external parts are not required, and the built-in IC circuit By using the device as a device, input/output pins can be eliminated, and dependence on power supply voltage can be completely eliminated.
実施例の説明
第３図は本発明の一実施例のブロツク図であ
り、第４図はその動作波形図である。DESCRIPTION OF THE EMBODIMENT FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is an operational waveform diagram thereof.
第３図において、５は分周手段、６はアツプダ
ウンカウンタ、７は乗算手段、８は加算手段であ
り、D0は所定値、D1は入力デイジタル信号、D2
はアツプダウンカウンタ６の出力、D3は乗算手
段７の出力、D4は出力デイジタル信号、S1はク
ロツクパルス、S2は分周出力である。 In FIG. 3, 5 is a frequency dividing means, 6 is an up-down counter, 7 is a multiplication means, 8 is an addition means, D 0 is a predetermined value, D 1 is an input digital signal, and D 2
is the output of the up-down counter 6, D3 is the output of the multiplication means 7, D4 is the output digital signal, S1 is the clock pulse, and S2 is the frequency divided output.
入力デイジタル信号D1は、クロツクパルスS1
と共に分周手段５の入力とし、クロツクパルスS1
を入力デイジタル信号D1と所定値D0との差の絶
対値に比例した周波数に分周する。一方、入力デ
イジタル信号D1の最上位の少なくとも１ビツト
をアツプダウン信号とし、分周手段５の分周出力
S2をクロツク信号としてアツプダウンカウンタ６
に入力する。また、入力デイジタル信号D1は乗
算手段７に入力し、係数Ｋを乗じる。さらに、ア
ツプダウンカウンタ６の出力D2と乗算手段７の
出力D3を加算手段８に入力し、加算出力D4を出
力デイジタル信号として得る構成にしている。 Input digital signal D 1 is clock pulse S 1
and the input of the frequency dividing means 5, and the clock pulse S 1
is divided into a frequency proportional to the absolute value of the difference between the input digital signal D1 and the predetermined value D0 . On the other hand, at least one most significant bit of the input digital signal D1 is used as an up-down signal, and the frequency division output of the frequency division means 5 is
Up-down counter 6 using S2 as a clock signal
Enter. Further, the input digital signal D1 is input to the multiplication means 7 and multiplied by a coefficient K. Further, the output D 2 of the up-down counter 6 and the output D 3 of the multiplication means 7 are input to the addition means 8, and the addition output D 4 is obtained as an output digital signal.
第４図により第３図の動作を説明すれば、入力
デイジタル信号D1が所定値D0より大か小かによ
りアツプダウンカウンタ６の動作をアツプかダウ
ン（またはダウンかアツプ）に切換えている。即
ち、出力D2はD1とD0の関係が、D1＞D0（または
D1＜D0）のときアツプカウント（t2〜t3）、D1＝
D0のときカウント停止（t1〜t2、t3〜t4、t5〜）、
D1＜D0（またはD1＞D0）のときダウンカウント
（〜t1、t4〜t5）させる構成にしている。 To explain the operation of FIG. 3 with reference to FIG. 4, the operation of the up-down counter 6 is switched between up and down (or down and up) depending on whether the input digital signal D1 is larger or smaller than a predetermined value D0 . . That is, the output D 2 has a relationship between D 1 and D 0 such that D 1 > D 0 (or
When D 1 < D 0 ), up count (t 2 to t 3 ), D 1 =
Counting stops when D 0 (t 1 ~ t 2 , t 3 ~ t 4 , t 5 ~),
It is configured to count down (~ t1 , t4 ~ t5 ) when D1 < D0 (or D1 > D0 ).
ここで、D1＞D0かD1＜D0かの検出は、入力デ
イジタル信号D1の最上位の少なくとも１ビツト
を利用すればよい。即ち、入力デイジタル信号
D1が６ビツトで、所定値D0が100000の場合を例
にとり、入力デイジタル信号D1の最上位の１ビ
ツトが１のときD1＞D0とし、０のときD1＜D0と
すれば簡単に大か小かの検出が可能である。な
お、この場合、所定値D0を011111としても同様
の検出が可能である。 Here, to detect whether D 1 >D 0 or D 1 <D 0 , it is sufficient to use at least one most significant bit of the input digital signal D 1 . That is, the input digital signal
Taking as an example the case where D 1 is 6 bits and the predetermined value D 0 is 100000, when the most significant bit of the input digital signal D 1 is 1, D 1 >D 0 , and when it is 0, D 1 <D 0 . If you do this, you can easily detect whether it is large or small. Note that in this case, similar detection is possible even if the predetermined value D 0 is set to 011111.
上記の例は、所定値D0を入力デイジタル信号
D1の1/2の値に設定する場合であるが、1/4、3/4
の値に設定することも可能である。まず、1/4の
場合は、D0を010000（または001111）とし、D1の
最上位の２ビツトの論理和が１のときD1＞D0と
し、０のときD1＜D0とすればよい。また、3/4の
場合は、D0を110000（または101111）とし、D1の
最上位の２ビツトの論理積が１のときD1＞D0と
し、０のときD1＜D0とすればよい。また、D0を
他の値、例えば3/8、5/8の値に設定することも可
能である。但し、検出のための論理回路が多少複
雑となるのは否めない。 In the above example, input digital signal with predetermined value D 0
D is set to 1/2 of 1 , but 1/4, 3/4
It is also possible to set the value to . First, in the case of 1/4, set D 0 to 010000 (or 001111), and when the logical sum of the two most significant bits of D 1 is 1, D 1 > D 0 , and when it is 0, D 1 < D 0 . do it. In addition, in the case of 3/4, D 0 is 110000 (or 101111), and when the logical product of the two most significant bits of D 1 is 1, D 1 > D 0 , and when it is 0, D 1 < D 0 . do it. It is also possible to set D 0 to other values, such as 3/8 or 5/8. However, it cannot be denied that the logic circuit for detection is somewhat complicated.
次に、分周手段５において、クロツクパルスS1
を入力デイジタル信号D1と所定値D0との差の絶
対値に比例した周波数に分周し、その分周出力S2
をアツプダウンカウンタ６のクロツク入力として
いるため、入力デイジタル信号D1の大きさに比
例したアツプカウント、ダウンカウントが可能で
ある。これは、丁度第１図の従来例で入力の電位
差に比例して帰還コンデンサの充放電を行なうの
をデイジタル的に具現したものである。ここで、
(2)式の時定数T1を、
T1＝１／ck ……(3)
として求めることができる。但し、ckは分周手
段５の分周出力S2の最低周波数、即ち、D1とD0
の差の絶対値が１のときの周波数である。 Next, in the frequency dividing means 5, the clock pulse S 1
is divided into a frequency proportional to the absolute value of the difference between the input digital signal D 1 and the predetermined value D 0 , and the divided output S 2
is used as the clock input of the up-down counter 6, so it is possible to perform up-counting and down-counting in proportion to the magnitude of the input digital signal D1 . This is a digital implementation of the conventional example shown in FIG. 1 in which the feedback capacitor is charged and discharged in proportion to the input potential difference. here,
The time constant T 1 in equation (2) can be determined as T 1 =1/ ck (3). However, ck is the lowest frequency of the divided output S 2 of the frequency dividing means 5, that is, D 1 and D 0
This is the frequency when the absolute value of the difference is 1.
分周手段５、アツプダウンカウンタ６で成る積
分回路の出力D2に入力デイジタル信号D1に係数
Ｋを乗じた乗算手段７の出力D3を加算手段８に
おいて加算すれば、(2)式の比例要素T2／T1を付
加することができる。即ち、
T2／T1＝Ｋ ……(4)
となる。 If the output D 2 of the integrating circuit consisting of the frequency dividing means 5 and the up-down counter 6 is added to the output D 3 of the multiplication means 7, which is the input digital signal D 1 multiplied by the coefficient K, in the adding means 8, the equation (2) can be obtained. A proportional element T 2 /T 1 can be added. That is, T 2 /T 1 =K (4).
なお、アツプダウンカウンタ６の動作を、D1
＞D0のときダウンカウント、D1＜D0のときアツ
プカウントする構成とするときは、加算手段８を
減算手段とすることで入力デイジタル信号D1に
対する出力デイジタル信号D4を負極性とするこ
とができる。 Note that the operation of the up-down counter 6 is expressed as D 1
If the configuration is such that the count is down when >D 0 and the count is up when D 1 <D 0 , the adding means 8 is used as a subtracting means so that the output digital signal D 4 with respect to the input digital signal D 1 has negative polarity. be able to.
さらに、アツプダウンカウンタ６には、計数出
力D2をデコードしてD2が最大値及び最小値のと
きに入力されるクロツク、即ち、分周手段５の分
周出力S2の入力を禁止する機能を付加する。これ
により、アツプダウンカウンタ６のオーバーフロ
ー及びアンダーフローを防止できる。クロツク入
力の禁止は、D2のデコード出力によりアツプダ
ウンカウンタ６のクロツク入力部で行なつても良
いし、分周手段５で行なつてもよい。またD2が
最大値でクロツク禁止した場合は、次のダウン指
令で、最小値でクロツク禁止した場合は、次のア
ツプ指令でクロツク禁止を解除する構成にするこ
とは言うまでもない。 Furthermore, the up-down counter 6 is inhibited from receiving the clock that is input when the count output D2 is decoded and D2 is at the maximum and minimum values, that is, the divided output S2 of the frequency dividing means 5. Add functionality. Thereby, overflow and underflow of the up-down counter 6 can be prevented. The clock input may be inhibited by the clock input section of the up-down counter 6 using the decoded output of D2 , or by the frequency dividing means 5. Needless to say, if D2 is at its maximum value and the clock is inhibited, the next down command is used to inhibit the clock, and if it is at the minimum value, the next up command is used to cancel the clock inhibition.
発明の効果
本発明のデイジタル式比例積分回路は、分周手
段５、アツプダウンカウンタ６、乗算手段７、加
算（減算）手段８を用いるだけの極めて簡単な構
成で済み、かつ周辺部品を何ら必要とせず、ic内
部回路として用いるやピン数を不要にでき、さら
に電源電圧の依存性を皆無にできる等、その実用
的効果は大である。Effects of the Invention The digital proportional-integral circuit of the present invention has an extremely simple configuration that only uses a frequency dividing means 5, an up-down counter 6, a multiplication means 7, and an addition (subtraction) means 8, and does not require any peripheral components. When used as an IC internal circuit, the number of pins can be eliminated, and dependence on power supply voltage can be completely eliminated, which has great practical effects.
第１図はアナログ式比例積分回路の従来例のブ
ロツク図、第２図はその動作波形図、第３図は本
発明によるデイジタル式比例積分回路の一実施例
のブロツク図、第４図はその動作波形図である。
５……分周手段、６……アツプダウンカウン
タ、７……乗算手段、８……加算（減算）手段。
Fig. 1 is a block diagram of a conventional analog proportional-integral circuit, Fig. 2 is its operating waveform diagram, Fig. 3 is a block diagram of an embodiment of a digital proportional-integral circuit according to the present invention, and Fig. 4 is its operational waveform diagram. It is an operation waveform diagram. 5... Frequency division means, 6... Up-down counter, 7... Multiplication means, 8... Addition (subtraction) means.
Claims (1)
値との差の絶対値に比例した周波数に分周する分
周手段と、前記入力デイジタル信号の最上位の少
なくとも１ビツトをアツプダウン信号入力とし、
前記分周手段の出力をクロツク入力とするアツプ
ダウンカウンタと、前記入力デイジタル信号に係
数を乗じる乗算手段と、前記アツプダウンカウン
タの出力と前記乗算手段の出力とを加算（減算）
する加算（減算）手段とを具備し、前記加算（減
算）手段より出力デイジタル信号を得ることを特
徴とするデイジタル式比例積分回路。 ２ 所定値の最上位ビツトを１または０とし、他
のビツトを全て０または１とすることを特徴とす
る特許請求の範囲第１項記載のデイジタル式比例
積分回路。 ３ アツプダウンカウンタの最大、最小値を検出
した信号とアツプダウン信号とによりアツプダウ
ンカウンタのクロツク入力を制御することを特徴
とする特許請求の範囲第１項記載のデイジタル式
比例積分回路。[Claims] 1. Frequency dividing means for dividing a clock pulse into a frequency proportional to the absolute value of the difference between an input digital signal and a predetermined value, and at least one most significant bit of the input digital signal as an up-down signal input. ,
an up-down counter that uses the output of the frequency dividing means as a clock input; a multiplication means that multiplies the input digital signal by a coefficient; and addition (subtraction) of the output of the up-down counter and the output of the multiplication means.
1. A digital proportional-integral circuit comprising: addition (subtraction) means for adding (subtraction), and obtaining an output digital signal from said addition (subtraction) means. 2. The digital proportional-integral circuit according to claim 1, wherein the most significant bit of the predetermined value is set to 1 or 0, and all other bits are set to 0 or 1. 3. The digital proportional-integral circuit according to claim 1, wherein the clock input of the up-down counter is controlled by the signal detecting the maximum and minimum values of the up-down counter and the up-down signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58004481A JPS59128635A (en) | 1983-01-14 | 1983-01-14 | Digital type proportional integrating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58004481A JPS59128635A (en) | 1983-01-14 | 1983-01-14 | Digital type proportional integrating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59128635A JPS59128635A (en) | 1984-07-24 |
| JPH0142434B2 true JPH0142434B2 (en) | 1989-09-12 |
Family
ID=11585290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58004481A Granted JPS59128635A (en) | 1983-01-14 | 1983-01-14 | Digital type proportional integrating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59128635A (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50114277A (en) * | 1974-02-16 | 1975-09-08 | ||
| JPS5636456B2 (en) * | 1974-02-16 | 1981-08-24 | ||
| JPS5731045A (en) * | 1980-08-01 | 1982-02-19 | Hitachi Ltd | Digital integrator for bipolar signal |
| JPS5773454A (en) * | 1980-10-23 | 1982-05-08 | Ushio Inc | Integration network using voltage-to-frequency converter |
-
1983
- 1983-01-14 JP JP58004481A patent/JPS59128635A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59128635A (en) | 1984-07-24 |
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