JPH052899A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide the semiconductor integrated circuit capable of maintaining the secrecy of data written in a memory. CONSTITUTION:At the time of data writing, an internal data bus 21 and an external data bus 22 are connected through a bi-directional buffer 14. In this case, an input buffer 12 makes a write signal WRB valid and an input buffer 13 makes a read signal RDB invalid. Accordingly, data can be written in a memory 11, but can not be read from it. On the other hand, in a test mode testing whether or not the data is written in the memory 11 correctly, a bidirectional buffer 14 becomes invalid. A comparison circuit 16 compares the data written in the memory 11 with the data written in the external data bus 22, outputting the result. Thus, whether or not the data is written properly can be tested.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit which has a rewritable memory and has a function of switching between a normal operation state and a test state and which externally writes and reads data to and from the memory.

[0002]

2. Description of the Related Art Conventionally, this type of semiconductor integrated circuit has been constructed, for example, as shown in FIG. A semiconductor integrated circuit having a rewritable memory
"C" is a memory (hereinafter, simply referred to as "memory") 51 in the IC 5 with a built-in memory and an address bus 52.
And a data bus 53. The memory built-in IC 5 has a clock signal CLK and an active “LOW” signal (hereinafter referred to as “write signal”) WR _B for writing data in the memory 51 (hereinafter, the subscript B is an active “LOW”). Signal (indicated as a signal), and an active "LO" for reading data from the memory 51.
W "signal (hereinafter referred to as" read signal ") RD _B ,
An active "HIGH" signal (hereinafter referred to as "test signal") TEST and address for switching between a normal operation state (hereinafter referred to as "normal mode") and a test operation state (hereinafter referred to as "test mode") A _{0 to} A ₁₅ and data D _{0 to} D ₇ are input / output.

The operation of the conventional memory built-in IC 3 as shown in FIG. 13 will be described with reference to the timing chart shown in FIG.

When the test signal TEST is "HIGH", it is a test mode, and when it is "LOW", it is a normal mode.
The address is 16 bits long and the data is 8 bits long.

First, the writing of data from the outside of the memory IC 5 to the memory 51 will be described with reference to the write cycle portion in the timing chart of FIG. Data write addresses A _{0 to} A ₁₅ are set via the address bus 52, write data D _{0 to} D ₇ are input via the data bus 53, and a write signal WR _B is input to the memory 51 from outside the memory IC 5. By inputting, data is written in the memory 51.

Next, reading of data from the memory 51 to the outside of the memory IC 5 will be described with reference to the read cycle portion in the timing chart of FIG. Addresses A _{0 to} A ₁₅ for reading data are set via the address bus 52, and the memory 51 has a built-in memory IC.
Read from 5 outside through the data bus 53 the data D ₀ to D ₇ by inputting the read signal RD _B.

These data read and write operations are completely independent of whether the test mode or the normal mode is used.

[0008]

However, the above-described conventional memory built-in IC is capable of writing data to the memory and reading data from the memory regardless of the test mode or the normal mode. Therefore, there is a drawback that the confidentiality of the data in the memory cannot be maintained.

Further, if the data in the memory is simply made unreadable in order to maintain the confidentiality, there is a problem that the memory cannot be inspected.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor integrated circuit capable of inspecting a memory while maintaining confidentiality.

[0011]

A semiconductor integrated circuit according to a first invention of the present application is a semiconductor integrated circuit having a rewritable memory and having a function of switching between a normal operation state and a test operation state. A circuit for controlling a control signal for the rewritable memory and a bus connected to the rewritable memory so that data of the rewritable memory is not output to the outside of the semiconductor integrated circuit in a normal operation state. And a circuit for comparing external input data input from the outside of the semiconductor integrated circuit with the data of the rewritable memory in a test operation state, and a comparison result of the comparing circuit is output to the outside of the semiconductor integrated circuit. And a circuit for performing the same.

A semiconductor integrated circuit according to the second invention of the present application is
In a semiconductor integrated circuit having a rewritable memory and having a function of switching between a normal operation state and a test operation state, in the semiconductor integrated circuit, the data of the rewritable memory in the normal operation state is the semiconductor integrated circuit. A circuit for controlling a bus connected to the rewritable memory so as not to be output to the outside, a circuit for controlling a control signal connected to the rewritable memory, and a predetermined timing when the control signal is in a normal operation A circuit for erasing data in the rewritable memory when given at a different timing, external input data input from outside the semiconductor integrated circuit in the test operation state, and the data in the rewritable memory And a comparison result of the comparison circuit are output to the outside of the semiconductor integrated circuit. And having a circuit.

[0013]

In the first invention of the present application, a circuit for controlling a control signal for the memory and a bus connected to the memory so that the data in the memory is not output to the outside of the semiconductor integrated circuit in the normal mode, and the test mode A semiconductor integrated circuit is sometimes provided with a circuit that determines whether data input from outside the memory and data in the memory match, and a circuit that outputs a comparison result to the outside. As a result, the memory can be tested without outputting the data in the memory to the outside of the IC with a built-in memory.

Further, in the second invention of the present application, there is provided a circuit for erasing the data in the rewritable memory when the control signal given to the rewritable memory during the normal operation is given at a timing different from a predetermined timing. It is provided. Therefore, if the data in the memory is illegally read, the data in the memory is erased. As a result, the confidentiality of the data written in the memory can be further ensured.

[0015]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the structure of a memory built-in IC according to the first embodiment of the present invention.

The memory built-in IC1 shown in FIG. 1 has a memory (rewritable memory) 11 in the memory built-in IC1 and a write signal WR _B only in the memory test of the test mode.
One-way input buffer to disable (hereinafter, referred to as the "input buffer") 12, one-way input buffer to enable only read signal RD _B at the time of the memory test of the test mode (hereinafter referred to as the "input buffer") 13, a bidirectional buffer 14 that electrically disconnects the internal data bus and the external data bus during a memory test in the test mode, a latch 15 for holding data ED _{0 to} ED ₇ of the external data bus, an internal data bus ID _{0 to} ID ₇ and latch 1
5, the comparison circuit 16 for comparing and judging the data ED _{0 to} ED ₇ held in 5, the latch 17 for holding the result of comparison and judgment by the comparison circuit 16, and the flip-flop (hereinafter, referred to as “ "F / F") 1
8. A unidirectional output buffer (hereinafter referred to as “output buffer”) 19 for outputting the result of the F / F 18 when the memory test is completed, a 16-bit address bus of addresses A _{0 to} A ₁₅ (hereinafter referred to as “ "Address bus") 2
0, 8-bit data bus of data ID _{0 to} ID ₇ (hereinafter referred to as “internal data bus”) 21 and ED _{0 to} E
D ₇ 8-bit data bus (hereinafter referred to as “external data bus”)
22).

The memory built-in IC 1 has the same clock signal CLK as the conventional one, a write signal WR _B for writing data to the memory 11, a read signal RD _B for reading data from the memory 11, and a test mode. In addition to the test signal TEST and the addresses A _{0 to} A ₁₅ , a signal for performing a memory test in the test mode (hereinafter referred to as “memory test signal”) MEMT
EST, external data ED _{0 to} ED ₇ , internal data ID ₀
~ Reset signal RST _B for resetting ID ₇ and F / F 18 is input / output.

To simplify the explanation, consider only the address 8000h (h is a hexadecimal number) of the memory 11 and assume that the correct data at the memory 8000h is 7Fh. In the operation of, 8
000h, 8001h, 8002h and so on, but the principle is the same). Therefore, the address bus 20 is 16 bits, the external data bus 22 is 8 bits, and the internal data bus 2 is
1 is also assumed to be 8 bits. In addition, the bidirectional buffer 14,
The latch 15 and the comparison circuit 16 also process 8-bit data.

Referring to FIG. 1, first, the operation for writing the data 7Fh to the address 8000h of the memory 11 in the normal mode will be described.

Since the test signal TEST and the memory test signal MEMTEST are "LOW", the bidirectional buffer 14 is enabled and the internal data bus 21 and the external data bus 22 are connected. At this time, the input buffer 12 validates the write signal WR _B , and the input buffer 13
Invalidates the read signal RD _B. Therefore, in the normal mode, the data can be written in the memory 11, but the data cannot be read.

In this state, the address 8000h is designated via the address bus 20 and the data 7Fh
Is designated from the external data bus 22 via the internal data bus 21, and 8000 of the memory 11 is specified by the write signal WR _B.
Write data 7Fh to address h.

Next, switch to the test mode state,
The operation for confirming whether the data has been written correctly will be described with reference to FIG.

The test signal TEST is set to "HIGH" to switch to the test mode, and the memory test signal MEMTEST is set to "HIGH" for the memory test.
The bidirectional buffer 14 is disabled and the internal data bus 21
And the external data bus 22 are separated from each other. At this time, the input buffer 12 invalidates the write signal WR _B and the input buffer 13 validates the read signal RD _B , so that the data in the memory 11 can be read out, and the test is started in this state.

First, in the normal mode, an operation of writing 55h different from the data written in the memory 11 is performed. Since the bidirectional buffer 14 is disabled and the write signal WR _B is not input to the memory 11 by the input buffer 12, no data is written to the memory 11, but the write signal WR _B is input to the latch 15. Then, the data 55h is latched.

Next, in order to read data from the address 8000h of the memory 11, 800
Specify the address 0h, enter the read signal RD _B. Since the data 7Fh has already been written in the address 8000h of the memory 11, the data 7Fh is transferred via the internal data bus 21.
h is read. The data 55h latched in the latch 15 and the data 7Fh read out to the internal data bus 21 are compared and determined by the comparison circuit 16 (the comparison circuit 16 in this case "HIG" when the comparison result does not match).
H "is output.) Since the comparison and determination results do not match," HIGH "is latched in the latch 17 by the rising edge of the read signal RD _{B. Since} the output of the latch 17 becomes" HIGH ", F due to rising edge
The output of / F18 also becomes "HIGH".

Therefore, when the memory test is completed and the memory test signal MEMTEST becomes "LOW", "HIGH" is stored in the memory built-in I as a result of the memory test.
It is output to the outside of C1.

When the data 7Fh is latched in the latch 15, the comparison result of the comparison circuit 16 is the same as shown in the timing chart of FIG.
The rising edge of _B latches "LOW" in the latch 17. Since the output of the latch 17 becomes "LOW", the output of the F / F 18 also becomes "LOW" at the rising edge.

Therefore, when the memory test is completed and the memory test signal MEMTEST becomes "LOW", "LOW" is output from the buffer 19 to the outside of the memory built-in IC1 as a result of the memory test.

FIG. 4 is a block diagram showing the configuration of a memory built-in IC according to the second embodiment of the present invention.

The memory built-in IC 2 shown in FIG.
1, input buffer 13, F / F 18, output buffer 1
9, address bus 20 for addresses A _{0 to} A ₁₅ , data I
An internal data bus 21 of D _{0 to} ID ₇ , an external data bus 22 of ED _{0 to} ED ₇ , and a one-way buffer 2 that transfers data only from the external data bus 21 to the internal data bus 22.
3, latch 24 for holding data ID _{0 to} ID ₇ of internal data bus 21, data ED _{0 of} external data bus
~ ED ₇ and data ID _{0 to} ID held in the latch 24
_It is provided with a comparison circuit 25 for comparing and judging ₇ and a latch 26 for holding the result of comparison and judgment by the comparison circuit 25. F /
F18 determines the output according to the result of the latch 26.

Similar to the case of the first embodiment described above,
Address 8000 of memory 11 for brevity
Consider only address h, and assume that the correct data at address 8000h in the memory is 7Fh (in the actual operation, 80
00h, 8001h, 8002h, etc., but the principle is the same). Therefore, the address bus 20 has 16 bits,
It is assumed that the external data bus 22 has 8 bits and the internal data bus 21 also has 8 bits. The one-way buffer 23, the latch 24, and the comparison circuit 25 also process 8-bit data.

Referring to FIG. 4, first, the operation for writing the data 7Fh to the address 8000h of the memory 11 in the normal mode will be described.

[0034] Since the test signal TEST and a memory test signal MEMTEST is "LOW", the input buffer 13 is disabled and the read signal RD _B, but in the normal mode may be writing data to the memory 11, reads the data It will not be possible. At this time,
The data bus is also in a state of transferring data only from the external data bus 22 to the internal data bus 21 by the unidirectional buffer 23. In this state, the address 8000h is designated via the address bus 20 and data 7
Fh is designated from the external data bus 22 via the internal data bus 21, and 80 of the memory 11 is specified by the write signal WR _B.
Data 7Fh will be written to address 00h.

Then, switch to the test mode state,
The operation for confirming whether the data has been written correctly will be described with reference to FIG.

The test signal TEST is set to "HIGH" to switch to the test mode, and the memory test signal MEMTEST is set to "HIGH" for the memory test.
Start the test in this state.

First, in order to read data from the address 8000h of the memory 11, 80
Designate address 00h and input read signal RD _B. Since the data 7Fh has already been written to the address 8000h of the memory 11, the data 7Fh is written via the internal data bus 21.
Fh is read. Since the one-way buffer 23 is in a state of transferring data only from the external data bus 22 to the internal data bus 21, the data 7Fh is not output to the external data bus 22, but the read signal RD _B is output to the latch 24. Is input and the data 7Fh is latched.

Next, it is assumed that the data 55h is written at the address 8000h of the memory 11. In this case, the address 8000h is specified via the address bus 20, 5h is input from the external data bus 22 and the write signal WR _B is input. Although the data 7Fh has already been written to the address 8000h of the memory 11, the data 55h is written because the data is transferred only from the external data bus 22 to the internal data bus 21 by the one-way buffer 23. The data 7Fh previously latched in the latch 24 and the data 55h written in the external data bus 22 are compared and determined by the comparison circuit 25 (in this case, the comparison circuit 25 outputs "HIGH" when the comparison results do not match. Shall be done). Since the comparison determination results do not match, "HIGH" is latched in the latch 26 at the rising edge of the write signal WR _B. The output of the latch 26 is "H
Since it becomes “IGH”, the output of the F / F 18 also becomes “HIGH” at the rising edge.

When the memory test is completed and the memory test signal MEMTEST becomes "LOW", "HIGH" is output from the buffer 19 to the outside of the memory IC 2 as a result of the memory test.

When the data written from the external data bus 22 is 7Fh, as shown in the timing chart of this operation in FIG. 6, the comparison judgment result of the comparison circuit 25 is a coincidence, so that the rising edge of the write signal WR _B. Thus, "LOW" is latched in the latch 26. Since the output of the latch 26 becomes "LOW", F / F1
The output of 8 also becomes "LOW".

Therefore, when the memory test is completed and the memory test signal MEMTEST becomes "LOW", "LOW" is output from the buffer 19 to the outside of the memory integrated IC 2 as a result of the memory test.

As described above, the memory built-in IC of the present invention is
A circuit for controlling a control signal for the memory and a bus connected to the memory so that the data in the memory is not output to the outside of the IC with the built-in memory in the normal mode, and data input from the outside of the IC with the built-in memory in the test mode. And a circuit for comparing and judging whether the data of the memory coincides with each other and outputting the judgment result to the outside. Therefore, since the data in the memory is not output to the outside of the semiconductor integrated circuit, the confidentiality can be maintained. In addition, if the data written to the memory is unknown, the memory cannot be inspected. If the data written to the memory is known, the memory can be inspected, so the memory can be inspected while maintaining confidentiality. can do.

FIG. 7 is a block diagram showing the structure of a memory built-in IC according to the third embodiment of the present invention.

The memory built-in IC 3 shown in FIG. 7 generates the rewritable memory 31 in the memory built-in IC 3, the timing of generating the address of the memory 31 and the signal for writing the data in the memory 31 to erase the data in the memory 31. Circuit (hereinafter referred to as "timing generation circuit") 3
2. A counter (hereinafter referred to as “counter”) 121 that increments (or decrements) the designated address to the memory 31 for each address 121, a register for storing the memory size of the memory 31 (hereinafter referred to as “register”). 122), a latch (hereinafter referred to as “latch”) 33 for holding that the memory test in the test mode is being performed, a latch for holding data ID _{0 to} ID ₇ of the internal data bus (hereinafter, “latch”). (Referred to as a "latch") 34, a comparison circuit (hereinafter referred to as "comparison circuit") 35 for comparing and judging the data ED _{0 to} ED ₇ of the external data bus and the data ID _{0 to} ID ₇ held in the latch 34, a comparison A latch (hereinafter, referred to as “latch”) 3 for holding the result of comparison and determination by the circuit 35
6, a flip-flop (hereinafter referred to as "F / F") 37 that determines an output value based on the output result of the latch 36, and a gate circuit that outputs an error signal based on the output result of the latch 33 and the output result of the F / F 37 ( Hereinafter, referred to as a "gate circuit" 38, a gate circuit that electrically disconnects the external data bus from the internal data bus, and sets the data of the internal data bus to 0 by an error signal output from the gate circuit 38 (hereinafter, referred to as "gate circuit"). 39, a "gate circuit"), and a 3-state buffer (hereinafter referred to as "buffer") that controls the output of the counter 121 inside the timing generation circuit 32 according to the error signal output from the gate circuit 38.
40, a three-state buffer (hereinafter referred to as “buffer”) 41 that disconnects the address bus from the outside of the memory-embedded IC 3 when an error is determined, 41 A 3-state buffer (hereinafter, referred to as a “buffer”) 42 that separates a signal for writing data, a memory 3 from outside the memory-embedded IC 3 when performing a memory test.
3-state buffer (hereinafter referred to as "buffer") 43 for separating a signal for reading 1 data, F / F
A three-state buffer (hereinafter,
A "buffer" 44, a 3-state buffer (hereinafter "buffer") 45 for controlling the output Q _B of the F / F 37, a 16-bit address bus of addresses A _{0 to} A ₁₅ (hereinafter "address bus") 46), an 8-bit data bus (hereinafter referred to as “external data bus”) 47 for data ED _{0 to} ED ₇ , and 8 of data ID _{0 to} ID ₇ .
A bit data bus (hereinafter referred to as “internal data bus”) 48 is provided.

The memory built-in IC 3 has a clock signal CLK, a write signal WR _B for writing data to the memory 31, a read signal RD _B for reading data from the memory 31, a test signal TEST for switching to a test mode, A memory test signal MEMTEST for performing a memory test in the test mode, addresses A _{0 to} A ₇ , external data ED _{0 to} ED ₇ , and internal data I.
D _{0 to} ID ₇ and the reset signal RST _B are input / output.

To simplify the explanation, it is assumed that the address size of the memory 31 is FFh bits, that is, 256 bits, and only the address B0h is considered, and the memory B
It is assumed that the correct data at address 0h is 7Fh (in the actual operation, B0h, B0h, B2h ... Are continuous, but the principle is the same). Therefore, it is assumed that the address bus 46 has 16 bits, the external data bus 47 has 8 bits, and the internal data bus 48 has 8 bits. Further, the gate circuit 39, the buffer 40, the buffer 41, the latch 34, and the comparison circuit 3
5 also processes 8-bit data.

Referring to FIG. 7, first, the operation for writing the data 7Fh to the address B0h of the memory 31 in the normal mode will be described.

The test signal TEST and the memory test signal MEMTEST are "LOW", the buffer 42 enables the write signal WR _B from the outside of the memory IC 3 and the buffer 43 the read signal RD _B from the outside of the memory IC 3. To enable. However, the output Q of the latch 33 is "HIGH" (initial value is "HIGH"), the buffer 44 invalidates the output Q of the F / F 37, and the buffer 45 outputs the output Q _B of the F / F 37. It is disabled. In this state, address B0h is set to address bus 4
6. The data 7Fh is designated from the external data bus 47 via the internal data bus 48, and the data 7Fh is written to the address B0h of the memory 31 by the write signal WR _B.

At this time, when the read signal WR _B is input to read the data of the memory 31, the output Q of the latch 33 is latched at “LOW” by the read signal RD _B , and the error signal ERR _B is input via the gate circuit 38. (Active “LOW”) is set to “LOW”. The error signal ERR _B output via the gate circuit 38 disconnects the address bus 46 by the buffer 41 so that no signal is input from the outside of the memory IC 3. Further, all the data on the internal data bus 48 is set to 0 via the gate circuit 39. However, only the buffer 40 enables the output of the counter 121 inside the timing generation circuit 32.

The timing signal generating circuit 32 is activated by the error signal ERR _B output via the gate circuit 38, and the data is written by the write signal WR _B to the address output from the counter 121 inside the timing generating circuit 32. Since the data on the internal data bus 48 is 0,
0 is written in the memory 31.

Counter 1 in timing generation circuit 32
21 increases the address of the memory 31 for each address, so that 0 is sequentially written in the memory 31 by the write signal WR _B. Then, the timing generation circuit 32
When the value of the address exceeds the value of the memory size of the internal register 122 of, the operation of the timing generation circuit 32 is completed. As a result, all the data in the memory 31 becomes zero.

Next, the operation for switching to the test mode and confirming whether the data has been written correctly will be described with reference to FIG.

The test signal TEST is set to "HIGH" to switch to the test mode, and the memory test signal is set to "HIGH" to perform the memory test. The buffer 44 enables the output Q of the F / F 37, and the buffer 4
5 enables the output Q _B of the F / F 37. Buffer 42
Is to disable the write signal WR _B from the external memory built IC3, buffer 43 is disabled and the read signal RD _B from the external memory built IC3, the gate and the external data bus 47 and the internal data bus 48 The circuit 39 is in the separated state, and the test is started in this state.

At this time, even if the read signal RD _B is input in an attempt to read the data of the memory 31, the output Q of the latch 33 is latched at “HIGH” by the read signal RD _B , and the error signal via the gate circuit 38 is output. Since ERR _B becomes "HIGH", the current state is maintained.

First, in order to read the data from the address B0h of the memory 31, the address B0h is designated via the address bus 46 and the read signal RD _B is input. Memory 31
Since the data 7Fh has already been written to the address B0h, the data 7Fh is latched via the internal data bus 48.
Latched to 4.

Next, 55h different from the data written in the memory 31 in the normal mode is written. However, buffer 4
2, the write signal WR from the outside of the memory built-in IC3
_{Since B} is separated and is not input to the memory 31, no data is written to the memory 31. The data 7Fh previously latched in the latch 34 and the data 55h written in the external data bus 47 are compared and judged by the comparison circuit 35 (the comparison circuit 35 outputs "HIGH" when the comparison result does not match). And). Since the comparison and determination results do not match, the read signal R
The latch 36 is "HIGH" by the rising edge of D _B.
Is latched. Since the output of the latch 36 becomes "HIGH", the output Q of the F / F 37 also becomes "H" at the rising edge.
IGH ”, and“ HIGH ”is output from the buffer 44 to the outside of the memory IC 3 as a result of the memory test. Since the output Q _B of the F / F 37 is“ LOW ”, an error signal is output via the gate circuit 38. ERR _B is "L
OW ", the timing generation circuit 32 is activated, and the same operation as above is performed.

FIG. 9 shows a timing chart when the same data as the previously written data is written. When the data 7Fh is written, the comparison circuit 3
Since the comparison judgment result of 5 is a match, the read signal RD _B
"LOW" is latched in the latch 36 by the rising edge of. Since the output of the latch 36 becomes "LOW", the output Q of the F / F 37 also becomes "LOW" at the rising edge, and "LOW" is output from the buffer 44 to the outside of the memory IC 3 as a result of the memory test. F / F
Since the output Q _B of 37 is “HIGH”, the error signal ERR _B output via the gate circuit 38 is “HIG”.
It becomes H ″, and the timing generation circuit 32 is not activated.

In this embodiment, the same effect as in the first and second embodiments can be obtained, and in addition, if the data written in the memory is illegally read out, the data in the memory can be read. Will be erased. Thereby, the confidentiality of the data can be further ensured.

FIG. 10 is a block diagram showing the configuration of an IC with a built-in memory according to the fourth embodiment of the present invention.

The memory built-in IC 4 shown in FIG. 10 includes a memory 31, a latch 33, a latch 34, a comparison circuit 35, a latch 36, an F / F 37, a gate circuit 38, a buffer 40, a buffer 41, a buffer 42, a buffer 43, and a buffer 4.
4, the buffer 45, the address bus 46 of addresses A ₀ to A _15, the external data bus 47 the data ED ₀ ~ED _7, the internal data bus 48 of the data ID ₀ ~ID _7, memory 31
Timing generating circuit (hereinafter referred to as "timing generating circuit") 49 for generating an address and a write signal of the memory 31 to erase the data of the memory 31, and the designated address to the memory 31 is increased (or decreased) for each address. Counter (hereinafter referred to as "counter") 291, a register for storing the memory size of the memory 31 (hereinafter referred to as "register") 292, a register for storing data to be written in the memory 31 (hereinafter referred to as "register") 2)
93 and a unidirectional buffer (hereinafter, referred to as “unidirectional buffer”) 50 for transferring data from the external data bus to the internal data bus.

The memory built-in IC 4 has the same clock signal CLK, write signal WR _B , read signal RD _B , test signal TEST, memory test signal MEMTEST, addresses A _{0 to} A ₁₅ , external data as in the third embodiment. ED
_{0 to} ED ₇ , internal data ID _{0 to} ID _7, and reset signal RST _B are input and output.

To simplify the explanation, it is assumed that the address size of the memory 31 is FFh bits, that is, 256 bits, only the address B0h is considered, and the memory B
It is assumed that the correct data at address 0h is 7Fh (in the actual operation, B0h, B1h, B2h, ... Are continuous, but the principle is the same). However, for convenience of explanation, it is assumed that the address bus 46 is 16 bits, the external data bus 47 is 8 bits, and the internal data bus 48 is 8 bits. Further, the buffer 40, the buffer 41, the buffer 50, the latch 34, and the comparison circuit 35 also process 8-bit data.

Referring to FIG. 10, first, the operation for writing the data 7Fh to the address B0h of the memory 31 in the normal mode will be described.

The test signal TEST and the memory test signal MEMTEST are "LOW", the buffer 42 validates the write signal WR _B from the outside of the memory IC 4 and the buffer 43 the read signal RD _B from the outside of the memory IC 4. However, the output Q of the latch 33 is "HIGH" (initial value is "HIGH"),
The buffer 44 invalidates the output Q of the F / F 37,
The buffer 45 invalidates the output Q _B of the F / F 37. In this state, address B0h is set to address bus 4
6, the data 7Fh is designated from the external data bus 47 via the internal data bus 48, and the data 7Fh is written to the address BOh of the memory 31 by the write signal WR _B.

At this time, when the read signal RD _B is input to read the data of the memory 31, the output Q of the latch 33 is latched at “LOW” by the read signal RD _B , and the error signal ERR _{B is} output via the gate circuit 38. To "LOW". The error signal ERR _B output via the gate circuit 38 disconnects the address bus 46 by the buffer 41 so that the signal is not input from the outside of the memory-incorporated IC 4. However, only the buffer 40 enables the output of the counter 291 inside the timing generation circuit 49.

The timing signal generating circuit 49 is activated by the error signal ERR _B output through the gate circuit 38, and the data is written by the write signal WR _B to the address output from the counter 291 inside the timing generating circuit 49. The data of the internal data bus 48 is written in the memory 31 with a value preset in the register 293 inside the timing generation circuit 49. The address of the memory 31 is incremented for each address by the counter 292 inside the timing generation circuit 49, and the write signal W
Value set in the internal register 293 of the timing generating circuit 49 by R _B are sequentially written. When the address value exceeds the memory size value of the register 291 inside the timing generation circuit 49, the operation of the timing generation circuit 49 is completed. Therefore, all the data in the memory 31 have the values set in the register 293 inside the timing generation circuit 49.

As for the operation for confirming whether the data is correctly written by switching to the test mode state, the external data bus 47 and the internal data bus 48 are connected to the buffer 5 as shown in the timing chart of FIG.
The third embodiment is the same as the third embodiment except that it is separated by 0.

FIG. 12 is a timing chart when the data written in the external data is the same as the date previously written. When data 7Fh is written,
For comparison decision result of the comparison circuit 35 is coincident, "the latch 36 by the rising edge of the read signal RD _B LO
W ”is latched. Since the output of the latch 36 becomes“ LOW ”, the output Q of the F / F 37 also becomes“ LOW ”due to the rising edge, and the memory built-in I
"LOW" is output to the outside of C4 as a result of the memory test. Since the output Q _B of the F / F 37 becomes “HIGH”, the error signal ERR _B output via the gate circuit 38 becomes “HIGH”, and the timing generation circuit 1
2 will not start.

Also in this embodiment, the same effect as that of the third embodiment can be obtained.

[0070]

As described above, in the first invention of the present application, the control signal for the memory and the bus connected to the memory are controlled so that the data in the memory is not output to the outside of the IC with the built-in memory in the normal mode. And a circuit for comparing and determining whether or not the data input from the IC with a built-in memory and the data in the memory are compared in the test mode and outputting the determination result to the outside of the memory while maintaining confidentiality. An IC with a built-in memory that enables inspection can be provided.

In the second invention of the present application, a circuit for controlling the bus connected to the memory, a circuit for controlling the control signal connected to the memory, and a circuit for controlling the control signal connected to the memory. And a circuit for erasing the data in the rewritable memory when a control signal is given at a timing different from a predetermined timing during normal operation, so that the data written in the memory is external to the semiconductor integrated circuit. If the data is not read out, the data in the memory is erased if the data is read out illegally, so that there is an effect that the confidentiality can be more surely maintained. Furthermore, since it has a circuit that compares and determines external data and memory data in the test mode and a circuit that outputs the comparison result to the outside, if the data written to the memory is unknown, it is written to the memory. If the data is unknown, the memory cannot be inspected, and if the data written in the memory is known, the memory can be inspected. Therefore, there is an effect that the memory can be inspected while maintaining confidentiality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart diagram showing the same operation.

FIG. 3 is a timing chart diagram showing the same operation.

FIG. 4 is a block diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a timing chart showing the same operation.

FIG. 6 is a timing chart showing the operation of the same.

FIG. 7 is a block diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 8 is a timing chart diagram showing the same operation.

FIG. 9 is a timing chart showing the operation of the same.

FIG. 10 is a block diagram showing a configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 11 is a timing chart showing the same operation.

FIG. 12 is a timing chart diagram showing the same operation.

FIG. 13 is a block diagram showing a configuration of an example of a conventional semiconductor integrated circuit.

FIG. 14 is a timing chart diagram showing the same operation.

[Explanation of symbols]

1, 2, 3, 4, 5; semiconductor integrated circuit 11, 31, 51; memory 12, 13; 3-state input buffer 14; Bidirectional buffer 15, 17, 24, 26; Latch 16, 25; comparison circuit 18; Flip-flop 19; 3-state output buffer 20; Address bus 21; Internal data bus 22; External data bus 23; one-way buffer

Claims (2)

[Claims] 1. A semiconductor integrated circuit having a rewritable memory and having a function of switching between a normal operation state and a test operation state, wherein data of the rewritable memory in the semiconductor integrated circuit is in the normal operation state. So as not to be output to the outside of the semiconductor integrated circuit and a circuit for controlling a control signal for the rewritable memory and a bus connected to the rewritable memory; A semiconductor integrated circuit comprising: a circuit for comparing external input data with data of the rewritable memory; and a circuit for outputting a comparison result of the comparing circuit to the outside of the semiconductor integrated circuit. 2. In a semiconductor integrated circuit having a rewritable memory and having a function of switching between a normal operation state and a test operation state, data of the rewritable memory in the semiconductor integrated circuit in the normal operation state. A circuit for controlling a bus connected to the rewritable memory so that is not output to the outside of the semiconductor integrated circuit; a circuit for controlling a control signal connected to the rewritable memory; A circuit for erasing data in the rewritable memory when given at a timing different from a predetermined timing, and external input data input from the outside of the semiconductor integrated circuit in a test operation state and the rewritable A circuit for comparing the data of the memory and a comparison result of the comparing circuit for the semiconductor integrated circuit A semiconductor integrated circuit having a circuit for outputting to the outside.