CN1315732A - Automatic test method and circuit for RAM - Google Patents
Automatic test method and circuit for RAM Download PDFInfo
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Abstract
本发明公开了一种随机存储器的自动检测方法及其检测电路,其特点是,采用先向随机存储器的所有存储单元写入数据,再读出比较的方法,包括对该随机存储器的数据线测试和地址线测试两个部分,保证了芯片与外部随机存储器RAM的连接和外部随机存储器RAM内部连接无故障。本发明经测试表明,其对大容量随机存储器RAM的检测速度快,故障检出率高,具有很好的应用价值。
The invention discloses an automatic detection method of a random access memory and a detection circuit thereof. The two parts of the test and the address line test ensure that the connection between the chip and the external random access memory RAM and the internal connection of the external random access memory RAM are free from failure. Tests show that the invention has fast detection speed for large-capacity random access memory RAM, high fault detection rate, and has good application value.
Description
The present invention relates to a kind of Automatic Measurement Technique of random access memory ram.
In the Computer and Its Application system, random access memory is to be used for writing down the core cell of depositing raw data, intermediate treatment result and other information.Can random access memory realize normal read/write operation, and in the storage/access process data distortion does not take place, very important for the operate as normal that guarantees total system.For this reason, be necessary before system starts working, random access memory to be diagnosed.
Along with the develop rapidly of semiconductor technology, the raising of silicon chip integrated level, the memory capacity that can realize on the silicon chip of unit area is also in rapid increase.The memory capacity of present monolithic memory has been increased to the 64Mbit of today by the 1Kbit at the beginning of the seventies, and is increasing apace.Therefore, how to realize that the high speed to the high capacity random access memory ram, the test of high coverage rate just are even more important.
To the diagnostic procedure of random access memory ram, check it to carry out the validity of read/write operation exactly.Test to storer at present comprises two basic sides: the one, to the test of storage unit; Another is the test to address decoder.And be exactly by certain test pattern to the detection of random access memory ram, the function of storage unit and address decoding circuitry is carried out rapidly and efficiently inspection.
Whether it is a lot of to carry out the method that random access memory ram detects, but its basic thought all is by each storage unit being write one by one " 0 " and " 1 ", and then reads one by one, detect correct.Common test operation is to write data earlier in random access memory ram, immediately reads to compare.Though this method can detect various bridging faults effectively, can't detect the open circuit fault on data or the control line, cause a hidden trouble for the normal reliable operation of system.
Fig. 1 is to be open circuit fault figure on the Data Control line of example with static RAM S-RAM.Open circuit fault takes place at a point in data line Di among the figure, when in unit, tested random access memory ram address, writing test data as test controller (TEST_CONTROL), because the capacity effect on the circuit, the data that write are deposited among the equivalent capacity Ci of Di line, and can not disappear immediately, this moment as controller at once this address location of retaking of a year or grade detect, and the data of then reading are real to be the data of storing among the Ci, just a open circuit fault of ordering can not detect like this.
The objective of the invention is existing to detect the shortcoming of random access memory ram method and a kind ofly can carrying out at a high speed of proposing, high coverage rate test and detect fault random access memory detection technique accurately to the high capacity random access memory ram in order to overcome.
In order to realize the above object, the technical scheme of proposition of the present invention is: the random access memory detection method, be characterized in, adopt elder generation to write data to all storage unit of random access memory, read-around ratio method again comprises the data line test and the address wire of this random access memory is tested two parts:
(1) step to the data line test is:
A, set up a reconfigurable test data table, the user is written in specific data in this test data table according to actual needs in advance;
B, the data in the test data table are written in each storage unit of random access memory;
C, carry out retaking of a year or grade and detect;
D, read value is compared with the value of writing successively, if data consistent is then thought inerrancy; Otherwise, then think wrong;
(2) step to the address wire test is:
A, with a different set of data, write each storage unit of random access memory respectively;
B, read this data, and itself and data before writing are compared, if data consistent is then thought inerrancy; Otherwise, then think wrong.
The automatic testing method of above-mentioned random access memory wherein, can divide several times to write by different lot data in the data that write described in the data line testing procedure b, and test respectively;
The automatic testing method of above-mentioned random access memory wherein, can adopt the default data to carry out dependence test.
The automatic testing method of above-mentioned random access memory, wherein, compare and be meant in these data of reading described in the b step of address wire test, after last data are written to each storage unit of random access memory, in the same time period of writing next number certificate, just the data of all address registers of retaking of a year or grade compare.
The automatic testing method of above-mentioned random access memory, wherein, the data of described each address register relatively are the data that write at the last time, write new data again after relatively finishing.
The automatic testing method of above-mentioned random access memory, wherein described in the data line test, when data to be written switch, before sense data, will export after the data step-by-step negate that write earlier.
The automatic testing method of above-mentioned random access memory, wherein, when data to be written switch in data line is tested, testing circuit has inserted a blank operation cycle, this blank operation cycle is, test data is outputed on the external random access memory data bus after by negate circuit step-by-step negate, but do not write in the external random access memory.
A kind of testing circuit that is exclusively used in above-mentioned random access memory detection method, this testing circuit is located at a control chip inside, it comprises cpu interface circuit, detects enable register, detected state register, comparing data latch, RAM read-write controller, be characterized in, also comprise an address register and a cyclic address change circuit and a test data table storer; Foregoing circuit interconnects by data line; Wherein:
The test data table is used to write each test data;
Cpu interface circuit can write data in the test data table, carry out the test data configuration; And can start random access memory and detect by writing control word triggering random access memory read-write controller to detecting enable register; CPU also can read content in the detected state register by this interface circuit, so that grasp detected state and result;
Detect enable register and be used for external random access memory is detected, it writes appointment data by cpu interface circuit in detecting enable register, and open the detection enables;
The detected state register is used for providing testing result to cpu interface circuit;
The cyclic address change circuit is used for adding one to being input to the address register data;
The comparing data latch is used to latch the data of each storage unit that is written to random access memory.
The testing circuit of above-mentioned random access memory detection method, wherein, described testing circuit is located at a control chip inside.
The testing circuit of above-mentioned random access memory detection method, wherein, described test data table storer is one 16 * 16 a test data table storer.
The testing circuit of above-mentioned random access memory detection method wherein, also comprises a negate circuit in the described RAM read-write controller, this negate circuit is used for when data to be written are switched the data step-by-step negate that writes.
Because the present invention has adopted above technical scheme, by a random access memory ram testing circuit, realize automatic detection by testing circuit by the preset detection algorithm when powering on to random access memory in system.Not only can test storage unit and the address decoding circuitry of static RAM RAM quickly and efficiently, and can avoid the influence of the capacity effect that produced because signal wire opens circuit.
Concrete feature of the present invention, performance and advantage thereof are further provided by following embodiment and accompanying drawing thereof.
Fig. 1 is to be open circuit fault figure on the Data Control line of example with static RAM S-RAM in the prior art.
Fig. 2 is the electrical block diagram of random access memory ram testing circuit of the present invention.
Fig. 3 is a register detected state synoptic diagram of the present invention.
Fig. 4 external random access memory RAM Data Detection sequential chart.
Fig. 5 external random access memory address ram detects sequential chart.
See also Fig. 2, Fig. 2 is the electrical block diagram that random access memory ram detects control circuit.The plug-in external random access memory RAM of each communication control chip is as the buffer memory of data.For guarantee that data do not make a mistake in access procedure, must before starting working, circuit detect outside random access memory ram by this control chip.The testing circuit of this control chip inside comprises cpu interface circuit, detects enable register, detected state register, comparing data latch, read-write controller, address register and adds a circuit and a test data table storer.
Below be that example describes one by one to each several part with the external random access memory RAM of 64K * 16:
Cpu interface circuit can write data in the test data table, carry out the test data configuration; And can start random access memory ram and detect by writing control word triggering random access memory ram read-write controller to detecting enable register; CPU also can read content in the detected state register by this interface circuit, so that grasp detected state and result.
Detect enable register: under the default setting, detection enables to close, and this moment, chip can operate as normal.If want outside random access memory ram is detected, must in detecting enable register, write appointment data such as 55H by cpu interface circuit, the open detection enables, and this moment, chip can not carry out operate as normal, and automatically outside random access memory ram was checked by detecting controller.If end of test (EOT) then writes AAH in detecting enable register, then chip stops outside random access memory ram is detected, and enters normal operating conditions.
The detected state register is one 4 a register, each bit implication as shown in Figure 3, wherein:
Bit0 represents the detected state position: when this position is ' 1 ', expression external random access memory RAM detects and carries out.
Bit1 represents the testing result position: when this position is ' 1 ', represent to detect and finish.
Bit2 presentation address line error bit:, illustrate that address wire has problem when this position is ' 1 '.
Bit3 represents the data line error bit: when this position is ' 1 ', illustrate that data line has problem.
During power-up initializing, each bit of detected state whole clear 0; When detecting not discovery mistake of end, detected state is 0010.
The test data table is one 16 * 16 an internal random memory RAM, and its 16 default values are as follows successively:
0000、FFFF、0F0F、F0F0、5555、AAAA、5A5A、A5A5、0A0A、A0A0、0505、5050、55FF、FF55、FFAA、AAFF。
The cyclic address change circuit is used for adding one to being input to the address register data;
The comparing data latch is used to latch the data of each storage unit that is written to random access memory;
Negate circuit in the RAM read-write controller is used for when data to be written are switched the data step-by-step negate that writes.
When chip enters the data line test, it reads each data in this table successively, write all storage unit of external random access memory RAM, read all storage unit of external random access memory RAM then, with read value successively with table in each value compare, if consistent, then think inerrancy, otherwise report an error.
CPU can read and write this table, revises its default value.When visit test data table, detection enables and must close, otherwise the data of reading are incorrect.
The present invention does not have to adopt the data method more once of writing, but writes data to all storage unit read-around ratio is more earlier.
Among the present invention,, guarantee that chip and being connected with external random access memory RAM inside of external random access memory RAM are connected non-fault with test of content measurement divided data line and address wire test.In when test, last data are write after all external random access memory RAM, writing next number according to the same time period, just all address location data of retaking of a year or grade compare.Therefore each address location relatively writes data at the last time, the relatively intacter new data that writes again afterwards.
Therefore, method of testing of the present invention comprises the test of the data line of random access memory and two parts of address wire test, and when testing, can first test data line, and back test address line; Also can first test address line, back test data line.Below do detailed explanation:
1, the step to the data line test is:
A, set up a reconfigurable test data table, the user is written in specific data in this test data table according to actual needs in advance;
B, the data in the test data table are written in each storage unit of random access memory;
C, carry out retaking of a year or grade and detect;
D, read value is compared with the value of writing successively, if data consistent is then thought inerrancy; Otherwise, then think wrong.
When CPU writes 55H in the inspection enable register, detect enable open, chip at first enters the data line test mode.Control circuit in the external random access memory RAM detection module is the data in the read test data table stores device successively, write in all storage unit of external random access memory RAM, read all storage unit of external random access memory RAM then, read value is compared with the value of writing successively, if it is consistent, then think inerrancy, otherwise, data line error flag position set in the detected state register.
External random access memory RAM Data Detection sequential as shown in Figure 4.
Fig. 4 is an external random access memory RAM Data Detection sequential chart, among the figure:
Two divided-frequency clock signal (MCLK2): the two divided-frequency signal of clock is used for the read-write control of external random access memory RAM.Read external random access memory RAM when high, write when low.
Test address (MEM_TEST_ADDR): the test address that the random access memory ram read-write controller produces forms the address signal (MEMA) of reading and writing external random access memory RAM.
Blank operation (NULL_OPERATE): blank operation sign.
The address signal (MEMA) of read-write RAM: the output of external random access memory RAM control circuit, the address signal of read-write external random access memory RAM.
The data-signal (MEMD) of read-write RAM: the two-way I/O of external random access memory RAM control circuit, the data-signal of read-write external random access memory RAM.
Test data table address (TTAB_ADDR): internal signal, test data table address.
Test data table data outputs (TTAB_DO): internal signal.
Test data (MEM_TEST_DATA): the test data that the random access memory ram read-write controller produces forms the data-signal (MEMD) of reading and writing external random access memory RAM.
Data are relatively controlled (READ_DATA_VALID): detect the controller internal signal, show that the data of reading in from random access memory ram are valid data when high, can carry out data relatively.
The data-signal (MEMD) of read-write RAM: the two-way I/O of external random access memory RAM control circuit, the data-signal of read-write external random access memory RAM.
RAM reads in data (READ_IN): input, the data of being read in by external random access memory RAM.
Correlation data (COMPARE_DATA): internal signal, during Data Detection with read in the data that data compare.
As shown in Figure 4, at first testing circuit when low, the data in the test data table memory cell that address register is pointed write each storage unit of external random access memory RAM, and latch in the inner comparing data latch at MCLK2.
Then, data add one in the address register, carry out aforesaid operations again.Simultaneously when two divided-frequency clock signal MCLK2 is high level, testing circuit reads the content in each storage unit of external random access memory RAM successively, compares with data com PARE_DATA in the comparing data latch, then reports the data line mistake as difference.
Test data table storage address adds one, repeats said process, changes a week until the test chart address by " 00 " to " FF ", till data are all surveyed and gone in the test chart.
Testing process is as follows specifically: when detecting beginning in the address register data be " 00 ", the data in the test data table memory cell of its sensing are (00).At first when two divided-frequency clock signal MCLK2 when low, (00) is write each storage unit of external random access memory RAM, and latchs in the comparing data latch of inside; Then, data add one in the address register, when two divided-frequency clock signal MCLK2 is high level, testing circuit reads the content (should be (00) under the normal condition this moment) that last time write in each storage unit of external random access memory RAM, make it with the comparing data latch in data (00) compare, then when two divided-frequency clock signal MCLK2 when low, (01) is write this storage unit, when two divided-frequency clock signal MCLK2 is high level once more, the content that testing circuit reads in next storage unit of external random access memory RAM compares with the data that last time write, and has so all carried out a test and has write new test data until the storage unit of all external random access memory RAM; Data add one again in the address register then, and (01) is latched in the inner comparing data latch, repeat aforesaid operations, and the data in the test data table have all been carried out till the once test.
As can be seen, when test data table storer face mutually in the unit data not simultaneously, the data of at every turn reading from data bus all are different from the data that write last time, have so just avoided the comparing data situation identical with last time writing data effectively.
As shown in Figure 4, when data to be written switched, testing circuit had inserted a blank operation cycle (blank operation sign NULL_OPERATE is for high).To output to after the test data step-by-step negate on the external random access memory RAM data bus this moment, but do not write among the external random access memory RAM, the purpose of doing like this is: prevent to open circuit or other reason because of data line, output data does not write the storage unit of external random access memory RAM, but because the capacity effect on the data line, output data can't disappear at once, as read data from external random access memory RAM immediately, what just might read in is the data of " storage " on the data line, compare just with these data and can not find fault, cause omission.Therefore, before sense data, will write data negate output earlier, eliminate of the influence of data line " storage " data detecting toward outside random access memory ram.
2, the step to the address wire test is:
A, with a different set of data, write each storage unit of random access memory respectively;
B, read this data, and itself and data before writing are compared, if data consistent is then thought inerrancy; Otherwise, then think wrong.
After finishing the data line test, chip enters the address wire test mode, it produces a different set of data automatically, write different external random access memory ram cells respectively, and it is read, compare with the data before writing, in case wrong, then put in the test state register address mismark position immediately and be " 1 ".
The external random access memory address ram detects sequential as shown in Figure 5.
Fig. 5 is that the external random access memory address ram detects sequential chart, among the figure:
Two divided-frequency clock signal (MCLK2): the two divided-frequency signal of clock is used for the read-write control of external random access memory RAM.
Test data table address (TTAB_ADDR): internal signal, test data table address.
Write and enable (WRITE_ENA): output, testing circuit enables writing of outside random access memory ram, and is effectively high.
Read to enable (READ_ENA): output, testing circuit to outside random access memory ram read enable, high effectively.
(DATA_ADDR_TEST) selected in data/address test: internal signal, data/address test is selected, and surveys data for " 0 ", is " 1 " geodetic location.
Test address (MEM_TEST_ADDR): the test address that the random access memory ram read-write controller produces forms the address signal (MEMA) of reading and writing external random access memory RAM.
Blank operation (NULL_OPERATE): blank operation sign.
The address signal (MEMA) of read-write RAM: the output of external random access memory RAM control circuit, the address signal of read-write external random access memory RAM.
The data-signal (MEMD) of read-write RAM: the two-way I/O of external random access memory RAM control circuit, the data-signal of read-write external random access memory RAM.
Test data (MEM_TEST_DATA): the test data that the random access memory ram read-write controller produces forms the data-signal (MEMD) of reading and writing external random access memory RAM.
RAM reads in data (READ_IN): input, the data of being read in by external random access memory RAM.
Address wire test data (ADDR_DATA): internal signal, during address detected with read in the data that data compare.
Data are relatively controlled (READ_DATA_VALID): detect the controller internal signal, show that the data of reading in from random access memory ram are valid data when high, can carry out data relatively.
As shown in Figure 5, when test data table address TEST_TAB_ADDR is " FF ", testing circuit enables WRITE_ENA to writing of outside random access memory ram and puts lowly, reads to enable READ_ENA and keeps high level, begins to read the data that write for the last time in each storage unit and compares.Afterwards, as blank operation sign NULL_OPERATE when being high once more, read to enable READ_ENA and put lowly, data/address test selects signal DATA_ADDR_TEST to put height, writes simultaneously to enable WRITE_ENA and put height, and start address detects.
At first, test circuit produces the test address MEM_TEST_ADD output of " 0000 "～" FFFF ", and, this address value " 0000 "～" FFFF " write in the MEM_TEST_ADD corresponding address unit successively by external random access memory RAM read-write control circuit.
Then, read the content in external random access memory RAM " 0000 "～" FFFF " address location, and compare with corresponding address value respectively, then report the address mistake as difference.
Relatively finish, and as blank operation sign NULL_OPERATE when be high once more, data/address test selection signal DATA_ADDR_TEST and read enable signal READ_ENA and put lowly restPoses again, finishes external random access memory RAM detection.
If the address wire width of random access memory ram can't guarantee then that less than the data line width data of each address location are different.Can handle in addition as required, as: press the data line figure place to the random access memory ram segmentation, adopt " ring shift method ", write data " 0000～FFFF " successively at " 0 section ", write data " FFFF; 0000～FFFE " successively at " 1 section ", the rest may be inferred, guarantees that the order that different sections write data is different.
The present invention and traditional random access memory ram detection method relatively, it has unique advantage:
1, adopt the hardware detection control circuit to finish the read-write of whole random access memory ram testing process Produce and the control function, saved the CPU time, improved the operating efficiency of whole system.
2, can be by in the test data table, writing the switching that different test datas is finished testing algorithm.
3, carry out targetedly memory cell test and address decoder test, make system can distinguish rapidly event The barrier type is taked corresponding processing policy.
4, write with readout sequence in the test data to random access memory ram and arrange cleverly, So that the data to be compared of reading from random access memory ram are different from the data that last time write at every turn, and Some can't avoid front and back to write in the situation identical with sense data for adjacent twice, elder generation before carrying out data readback To the radix-minus-one complement of data wire output data writing last time, guarantee on the data wire in the equivalent capacity institute's deposit data and write last time Enter the data difference in the random access memory ram, carry out again retaking of a year or grade and detect.
The present invention shows that after tested its detection speed to big capacity random access memory ram is fast, and fault detects The rate height has good using value.
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| CN1322423C (en) * | 2004-07-20 | 2007-06-20 | 华为技术有限公司 | Detection method for failure of chip |
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2000
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