JPH0521691A - Semiconductor device and assembling method thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor device which can reduce the resistance of a common current path such as a power supply and GND, and can freely reduce the resistance of this current path. In a semiconductor device, each of a signal pad of a semiconductor chip 51 and one end of a signal lead extending in a first direction intersecting one side of the semiconductor chip is electrically connected through a wire, The power supply pad adjacent to the signal pad in the second direction, the signal pad, and the power supply pad and the one end of the signal lead, and extending in the second direction. Each of the power supply leads formed of the same lead frame as the power supply leads is electrically connected via a wire.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, a power IC that requires a large current to flow, and a pad of a semiconductor chip on which a semiconductor integrated circuit including various drive circuits is mounted. The present invention relates to a technique effectively applied to a semiconductor device in which a lead and a lead are electrically connected by a wire. 2. Description of the Related Art There are various lead frame shapes used in semiconductor integrated circuits.
It is disclosed in Japanese Patent Laid-Open No. 5-107250. By the way, the pads provided on the IC chip and the inner leads are usually individually wire-bonded. For example, in a semiconductor integrated circuit incorporating a serial-parallel conversion driver circuit or a power circuit, a power source is used. There are some that use a plurality of external connection terminals for power supply and GND. This is because a large current flows through the power supply circuit and eventually the ground line, and the above method is adopted to reduce the resistance. For example, the present inventors have developed a 32-bit thermal head driver, and the bonding pad structure of the semiconductor chip is such that one output pad is provided with a GND pad. That is, the majority of GND pins in a 56-pin package. This means that the greater the bit capacity, the more G
This means that the number of ND pins will increase and the package body will also increase in size. However, as a technical trend of the package, miniaturization is advantageous in improving the packaging density.
Furthermore, realizing a large-capacity semiconductor device with a small package leads to cost reduction. The present invention has been made in view of the above. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which the resistance of a common current path such as a power supply and GND can be reduced and the resistance of this current path can be freely reduced. Another object of the present invention is to reduce the resistance of a common current path such as a power supply and GND independently of an increase in the number of external connection terminals, and further to freely reduce the resistance of this current path. It is to provide a semiconductor device. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings. SUMMARY OF THE INVENTION The outline of the invention disclosed in the present application will be briefly described as follows. (1) In a semiconductor device in which pads and leads of a semiconductor chip formed in a rectangular planar shape are electrically connected through wires, the first pad of the semiconductor chip and the semiconductor chip One end of each first lead extending in the first direction intersecting one side of the first side is electrically connected via a wire, and
A second pad disposed adjacent to the pad in a second direction intersecting the first direction, disposed between the first pad and the second pad and one end side of the first lead, and arranged in the second direction. Second leads extending from the same lead frame as the first leads are electrically connected via wires. The second lead is used for a common purpose such as a ground line and a power source. With this structure, the first semiconductor chip
Since the wire length connecting the second pad and the second lead, that is, the leads used for a common purpose, can be made shorter than the wire length connecting the pad and the one end of the first lead, respectively, this wire length can be reduced. The shortened part, the second pad,
The resistance of the current path including the wire and the second lead can be reduced, and the extending direction of the second lead intersects the extending direction of the wire connected to the second pad. Since the wire can be connected also in the region, the second pad and the second lead can be freely connected with the wire having the shortest length. (2) A plurality of leads extending in a first direction intersecting with one side of the semiconductor chip are arranged at predetermined intervals along one side of the semiconductor chip having a rectangular planar shape. A semiconductor device in which one end of each of the plurality of leads on the pad side is electrically connected to each of a plurality of pads arranged in a second direction along one side of a semiconductor chip by a wire, A lead used for a common purpose extending in the second direction is arranged between a plurality of pads of the chip and one end of a plurality of leads, and one end of the lead used for the common purpose, Among the plurality of leads, one end of the first lead on the array first stage side is integrally molded, and the other end of the lead and one end of the second lead on the array end stage side are integrally molded to form the common Used for the purpose of And some pads of the plurality of pads of the semiconductor chip are electrically connected to each other via wires, and between the first lead and the second lead of the plurality of leads. One end of the arranged third leads and each of the pads of the other part of the plurality of pads of the semiconductor chip are electrically connected through the wire. The plurality of leads are arranged on each of the four sides of the semiconductor chip. With this configuration, in addition to the means (1),
The wire length connecting between the lead used for the common purpose and a part of the plurality of pads of the semiconductor chip is fixedly set to the shortest distance, and the wire between the first lead and the second lead is fixed. Even if the length of the wire connecting between the third lead and the other part of the plurality of pads changes due to an increase or decrease in the number of the third leads arranged in, the same purpose is always used. The wire length between the lead and the pad connected thereto can be set to the shortest distance regardless of increase or decrease in the number of third leads. (3) In the method of assembling a semiconductor device, a tab to which a semiconductor chip is to be attached, a plurality of leads whose ends are arranged along the sides of the tab, and the sides of the tab and the ends of the leads. Preparing a lead frame having another lead arranged along the side of the tab between the part and the tab, the tab, the plurality of leads and the other lead being integrally molded, Attaching a semiconductor chip having a plurality of pads to the tab, selecting the selected pad of the plurality of pads and the ends of the plurality of leads, and selecting the other pad and the other lead. And a wire, and the step of resin-sealing the semiconductor chip, the wires, the ends of the plurality of leads, and the other leads. An embodiment of a lead frame to which the present invention is applied will be described below with reference to FIG. The feature of this embodiment resides in that the number of external connection terminals for GND and the number of signal input / output pins in the semiconductor integrated circuit are increased. The feature of this embodiment is that the resistance of the current path through which a large current such as GND flows can be reduced, and the resistance of this current path can be freely reduced. As shown in FIG. 1, the lead frame 10
0 indicates the case of 44 pins. Same frame 1
00 inner leads 23, 29, 3 for GND
9 are integrally connected as shown by the diagonal lines. And, even though as many as nine connections are made from the GND pads of the IC chip 51, the package (not shown)
Only three terminals (outer leads) are provided outside. That is, the inner leads 25, 27, 3 originally used as the inner leads for GND.
All of 1, 33, 35, and 37 are unnecessary, and the inner leads are correspondingly opened. So in practice,
The inner leads 25 to 37 can be used for other purposes such as signal input / output pins. As a result, the lead frame 100 can be used even if the degree of integration of IC chips is increased and a capacity of 32 bits or more can be achieved in one IC chip. The lead frame 100 has one dam 54 facing one side of the tab 52 having a rectangular planar shape.
A plurality of inner leads 28 to 39 extending in a direction intersecting the extending direction of the dam 54 are integrally molded at a predetermined interval. That is, a plurality of inner leads 28 to 39
Extend in a direction intersecting with one side of the IC chip 51. Among the plurality of inner leads 28 to 39, the inner lead 29 for GND is provided on the first stage side of the array, and the GND lead is provided on the last stage side of the array.
The respective inner leads 39 for D are arranged. This G
The inner leads 30 to 38 arranged between the inner leads 29 and 39 for ND are arranged along one end side of a region connected to the pad of the IC chip 51 of the inner leads 30 to 38 and are separated by a predetermined distance, and have a common purpose, that is, for GND The inner lead used for the inner lead is extended, and one end of this inner lead is integrally formed with the inner lead 29 for GND on the first stage side of the array, and the other end is integrally formed with the inner lead 39 for GND on the last stage side of the sequence. To be done. As a result, the inner leads used for a common purpose are arranged between the plurality of pads arranged along one side of the IC chip 51 and the plurality of inner leads 30 to 38. The tab 54 is the tab lead 5
A part of the lead frame is supported by 3a and 53b. Further, the intervals from the inner leads 23 to 39 are made uniform, and especially, the inner leads 23 for GND,
The lead width dimension of the shaded portions of 29 and 39 may be made wider than the lead width dimension of the other inner leads 30 and the like to reduce the electric resistance and allow a large current to flow.
Also, in this way, the inner leads 23, 2 for GND are
When the lead width dimensions of 9 and 39 are expanded, the thermal resistance can be reduced, so that the heat generated from the IC chip 51 can be efficiently radiated to the outside. Further, the inner lead 2 for GND described above
Inner leads that are molded integrally with each of 3, 29, and 39 and are used for a common purpose are the pads of the IC chip 51 and the inner leads 24 to 28 and 30 to 3 for input / output signals.
8, the length of the gold wire (W) connecting the inner lead used for this common purpose and the GND pad of the IC chip 51 is the same as the inner lead for signal input / output. The length is shorter than the length of the gold wire connecting between 24 and the like and the signal input / output pad. That is, the resistance of the current path including the GND pad, the gold wire, and the inner lead used for a common purpose can be reduced. Moreover, since the gold wire connected to the GND pad can be connected in any region of the inner lead used for a common purpose, it can be freely connected in the shortest length. As a result, the amount of gold wire used can be reduced,
Also, the cost can be reduced. Further, the inner lead used for the common purpose has one end side which is the GND inner lead 29.
, And the other end is integrally molded with the inner lead 39 for GND, and the GND of the preliminary IC chip 51 is formed.
It is fixedly set at a position where the distance between the pad and the pad is the shortest. In this case, the GND inner leads 29, 39
Inner leads 3 for signal input / output arranged between the respective
When the number of wires such as 0 is increased, it is necessary to secure a distance between the inner leads adjacent to each other in the arrangement direction, for example, 30 and 31, so that the area to which the gold wire is connected is I.
The C chip 51 moves in a direction away from the pad, resulting in a shorter lead length. This means that the length of the gold wire connecting between the signal input / output inner lead 30 and the pad and the pad of the IC chip 51 becomes long. However, even when the lengths of the signal input / output inner leads 30 and the like change in this way, the distance between the inner leads used for a common purpose and the GND pad of the IC chip 51 is the shortest. Since the distance is set, the length of the gold wire can always be shortened. In particular, the arrangement of inner leads used for a common purpose is effective when a plurality of inner leads are arranged along each of the four sides of the IC chip 51. FIG. 2 shows the lead frame 100 of FIG.
The form of the IC package using is shown. As shown in the figure, since there are only three GND pins 23, 29 and 39, the other pins can be effectively used for power supply, signal input and signal output. Although not shown, the present invention is effective even when there are many power supply pins. An assembling method for obtaining the semiconductor device of the present invention will be briefly described below with reference to FIG. (1) Lead frame 10 integrally molded
Prepare 0. (2) The IC chip 51 having a plurality of pads arranged on the outer periphery is attached to the tab 52. (3) The predetermined pads arranged on the IC chip 51 and the ends of the predetermined inner leads are electrically connected by the wires W. (4) The IC chip 51, the wire W and the lead surrounded by the tab 54 are resin-sealed by a known sealing technique. (5) The tab 54 is cut, and then leads are molded to complete the semiconductor device, that is, the IC package shown in FIG. (1) It is possible to provide a semiconductor device in which the resistance of a common current path such as a power supply and GND can be reduced and the resistance of this current path can be freely reduced. (2) It is possible to provide a semiconductor device in which the resistance of a common current path such as a power supply and GND can be reduced independently of the increase in the number of external connection terminals, and the resistance of this current path can be freely reduced. .. Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, although the present invention is applied to the GND pin in the above embodiment, it may be applied to the power supply circuit. Further, although the number of GND pins is three in the above embodiment, the inner leads 34, 44 may be formed as the same GND inner lead so that wire bonding can be performed well. In the above description, the invention mainly made by the present inventor was applied to the lead frame which is the field of application which was the background of the invention. However, the present invention is not limited to this. It can also be used for an analog IC that incorporates a drive circuit, a power amplifier circuit, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing an embodiment of a lead frame to which the present invention is applied. FIG. 2 is a perspective view of an IC package using the lead frame of the present invention. [Explanation of Codes] 1 to 44 ... Inner lead, 51 ... IC chip, 52 ...
Tabs, 53a, 53b ... Tab suspension leads, 54 ... Dam,
100 ... Lead frame.

Claims (1)

[Claims] 1. In a semiconductor device in which pads and leads of a semiconductor chip formed in a rectangular planar shape are electrically connected to each other through wires, a first pad of the semiconductor chip and a first pad intersecting one side of the semiconductor chip One ends of the first leads extending in one direction are electrically connected to each other via wires, and are arranged in a second direction adjacent to the first pad of the semiconductor chip and intersecting the first direction. A second pad, a second pad that is disposed between the first pad and the second pad and one end side of the first lead, extends in the second direction, and is formed from the same lead frame as the first lead.
A semiconductor device in which each of the leads is electrically connected via a wire. 2. The semiconductor device according to claim 1, wherein the second lead is a lead used for a common purpose such as an earth line and a power supply. 3. A plurality of leads extending in a first direction intersecting one side of the semiconductor chip are arranged at a predetermined interval along one side of the semiconductor chip formed in a rectangular planar shape, and the leads extend along one side of the semiconductor chip. A plurality of pads of the semiconductor chip, in which a plurality of pads arranged in the second direction are electrically connected to respective pad-side ends of the plurality of leads via wires. A lead used for a common purpose extending in the second direction between one end of the plurality of leads, and one end of the lead used for the common purpose. And one end of the first lead on the first stage side of the array are integrally molded, and the other end of the first lead and one end of the second lead on the final stage side of the array are integrally molded and used for the common purpose. Lead, semiconductor chip Each part of the pad of the plurality of pads are electrically connected by interposing a wire,
Among the plurality of leads, one end of the third lead arranged between the first lead and the second lead and the pad of the other part of the plurality of pads of the semiconductor chip respectively have a wire interposed therebetween. A semiconductor device characterized by being electrically connected to each other. 4. The third lead is arranged on each of the four sides of the semiconductor chip.
The semiconductor device according to the item. 5. A tab to which a semiconductor chip is to be attached, a plurality of leads whose ends are arranged along the side of the tab, and between the side of the tab and the ends of the plurality of leads and along the side of the tab. The other tabs arranged according to
Preparing a lead frame in which a plurality of leads and other leads are integrally molded; attaching a semiconductor chip having a plurality of pads to the tab; selecting a plurality of pads from the plurality of pads; Electrically connecting each of the ends of the lead of the book with the other pad and the selected other pad by the wire, the semiconductor chip, the wire, the ends of the plurality of leads and the other A method of assembling a semiconductor device, comprising a step of resin-sealing leads.