JPH05166815A - Plated bump forming method and wafer plating jig used therefor - Google Patents
Plated bump forming method and wafer plating jig used thereforInfo
- Publication number
- JPH05166815A JPH05166815A JP3331681A JP33168191A JPH05166815A JP H05166815 A JPH05166815 A JP H05166815A JP 3331681 A JP3331681 A JP 3331681A JP 33168191 A JP33168191 A JP 33168191A JP H05166815 A JPH05166815 A JP H05166815A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- semiconductor wafer
- plating
- electrode
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H10W72/01255—
-
- H10W72/019—
-
- H10W72/29—
-
- H10W72/9415—
Landscapes
- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
(57)【要約】
【目的】 半導体ウエーハ内に均一に電流を与えること
によって、バンプ電極高さのばらつきを著しく減少する
ことができる、メッキバンプ形成方法及び、それに用い
るウエーハメッキ用治具を提供する。
【構成】 スクライブライン５ａにおいて導体層である
バリアメタル層９と接する半導体ウエーハ５の裏面全面
に、治具の電極層１１が密着するように治具で固定す
る。またスクライブライン５ａは半導体ウエーハ５の表
面全面において均一に分布している。したがって電源１
４と接続している電極層１１より、半導体ウエーハ５の
内部を通じ、バリアメタル層９に均一に電流を与えるこ
とができ、開口部９ａにバンプ電極高さのばらつきを減
少することができる。
(57) [Summary] [Object] To provide a plating bump forming method and a wafer plating jig used therefor capable of remarkably reducing variations in bump electrode height by uniformly applying a current to a semiconductor wafer. To do. [Structure] A jig is fixed so that an electrode layer 11 of the jig is in close contact with the entire back surface of the semiconductor wafer 5 in contact with the barrier metal layer 9 which is a conductor layer in the scribe line 5a. The scribe lines 5a are evenly distributed over the entire surface of the semiconductor wafer 5. Therefore power supply 1
An electric current can be uniformly applied to the barrier metal layer 9 through the inside of the semiconductor wafer 5 from the electrode layer 11 connected to the electrode 4 and the variation of the bump electrode height in the opening 9a can be reduced.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体ウエーハ上に電
解メッキ法にて、バンプ電極を形成するメッキバンプ形
成方法及びそれに用いるウエーハメッキ用治具に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plating bump forming method for forming bump electrodes on a semiconductor wafer by an electrolytic plating method and a wafer plating jig used therefor.
【０００２】[0002]
【従来の技術】半導体ウエーハにバンプ電極を形成する
手法のひとつとして、電解メッキを施す技術がある。以
下その構成について図９〜図１１を参照にしながら説明
する。2. Description of the Related Art As one of the methods of forming bump electrodes on a semiconductor wafer, there is a technique of electrolytic plating. The configuration will be described below with reference to FIGS. 9 to 11.
【０００３】図９及び図１０に示すように、半導体ウエ
ーハ４はウエーハメッキ用治具１により固定されてい
る。その半導体ウエーハ４の表面には何種類かの金属で
形成されたバリアメタル層が設けられ、写真蝕刻技術に
てバンプ電極を形成する箇所のみを開口したフォトレジ
ストパターンを形成している（図示せず）。As shown in FIGS. 9 and 10, the semiconductor wafer 4 is fixed by a wafer plating jig 1. A barrier metal layer made of some kind of metal is provided on the surface of the semiconductor wafer 4, and a photoresist pattern is formed by photolithography technique in which only the portions where bump electrodes are to be formed are opened (not shown). No).
【０００４】また、ウエーハメッキ用治具１は、テフロ
ン等の絶縁物で外形を成し、半導体ウエーハ４の表面に
接触する側には、電源２と半導体ウエーハ４の表面に設
けられたバリアメタル層とを接続するための導電性の高
い電極層３（例えば白金等）が露出している。この露出
した電極層３を半導体ウエーハ４の表面のバリアメタル
層とが完全に接触する様に半導体ウエーハ４のオリエン
テーションフラット部４ａをウエーハメッキ用治具１に
て固定する。The wafer plating jig 1 has an outer shape made of an insulating material such as Teflon. The highly conductive electrode layer 3 (for example, platinum) for connecting to the layer is exposed. The orientation flat portion 4a of the semiconductor wafer 4 is fixed by the wafer plating jig 1 so that the exposed electrode layer 3 is completely in contact with the barrier metal layer on the surface of the semiconductor wafer 4.
【０００５】次に図１１に示すようにメッキ液１８中の
半導体ウエーハ４の対面には白金メッキを施したＴｉ等
で形成された対向電極１７が設けられている。この対向
電極１７は、半導体ウエーハ４の外径よりも大きく、一
部が電源２に接続している。Next, as shown in FIG. 11, a counter electrode 17 made of platinum-plated Ti or the like is provided on the opposite side of the semiconductor wafer 4 in the plating solution 18. The counter electrode 17 is larger than the outer diameter of the semiconductor wafer 4 and is partially connected to the power supply 2.
【０００６】上記構成においてウエーハメッキバンプ形
成を施すために、半導体ウエーハ４に適切な電流密度
（例えば０．１〜０．４Ａ／ｄｍ2）を与える様に印加
電流を調整し、適切な時間（例えば６０分〜１２０分）
電源２を稼動させると、高さ１０〜２０μｍ程度のバン
プ電極を形成することとなる。In order to form the wafer-plated bumps in the above structure, the applied current is adjusted so that an appropriate current density (for example, 0.1 to 0.4 A / dm 2 ) is applied to the semiconductor wafer 4, and an appropriate time ( (For example, 60 minutes to 120 minutes)
When the power supply 2 is operated, bump electrodes having a height of about 10 to 20 μm are formed.
【０００７】[0007]
【発明が解決しようとする課題】以上述べたような従来
の構造では、ウエーハメッキ用治具１は、半導体ウエー
ハ４のオリエンテーションフラット部４ａを固定してい
るため、電源に接続している電極層３は半導体ウエーハ
のオリエンテーションフラット部４ａのみで半導体ウエ
ーハ４の表面のバリアメタル層と接触する構造となり、
半導体ウエーハ４内の電極層３近傍Ａと電極層３と離れ
た箇所Ｂ、すなわちオリエンテーションフラット部近傍
Ａとオリエンテーションフラット部から離れた箇所Ｂの
間で、電流密度に差違が生じバンプ電極高さがウエーハ
面内でばらつくという問題が生じた。In the conventional structure as described above, since the wafer plating jig 1 fixes the orientation flat portion 4a of the semiconductor wafer 4, the electrode layer connected to the power source is fixed. 3 is a structure in which only the orientation flat portion 4a of the semiconductor wafer is in contact with the barrier metal layer on the surface of the semiconductor wafer 4,
A difference in current density occurs between the vicinity A of the electrode layer 3 in the semiconductor wafer 4 and a portion B separated from the electrode layer 3, that is, between the vicinity A of the orientation flat portion and the portion B separated from the orientation flat portion, and the bump electrode height increases. The problem of variation on the wafer surface arose.
【０００８】本発明はこのような課題を解決したメッキ
バンプ形成方法及びそれに用いるウエーハメッキ用治具
の提供を目的としている。An object of the present invention is to provide a plating bump forming method and a wafer plating jig used therefor which solves the above problems.
【０００９】[0009]
【課題を解決するための手段】本発明のメッキバンプ形
成方法は上記目的を達成するために、半導体ウエーハ表
面に、前記半導体ウエーハ表面の全領域にわたり実質的
に均一な分布をもって前記半導体ウエーハと接する導体
層を設け、前記半導体ウエーハの裏面全面より前記半導
体ウエーハを通じ前記導体層に電流を与え、前記導体層
上の絶縁膜の開口部にバンプ電極を形成するものであ
る。In order to achieve the above object, the method of forming a plating bump of the present invention contacts a surface of a semiconductor wafer with the semiconductor wafer with a substantially uniform distribution over the entire area of the surface of the semiconductor wafer. A conductor layer is provided, and a current is applied to the conductor layer from the entire back surface of the semiconductor wafer through the semiconductor wafer to form bump electrodes in the openings of the insulating film on the conductor layer.
【００１０】また、本発明のウエーハメッキ用治具は上
記目的を達成するためにウエーハ裏面に接触する側に、
実質的に前記ウエーハ裏面全面と接続するための電極層
をもち、前記ウエーハ裏面と前記電極層とが完全に接触
するように固定する手段を備えたものである。In order to achieve the above-mentioned object, the wafer plating jig of the present invention is provided on the side contacting the back surface of the wafer,
It has an electrode layer for connecting to substantially the entire back surface of the wafer, and is provided with a means for fixing the back surface of the wafer and the electrode layer so as to make complete contact with each other.
【００１１】[0011]
【作用】本発明は上記した構成により、裏面全面より導
体層に均一に電流を与えるので、半導体ウエーハ内の電
流密度の差違を小さくすることができ、バンプ電極の高
さのばらつきを著しく減少することができるものであ
る。According to the present invention, since the current is uniformly applied to the conductor layer from the entire back surface by the above-mentioned structure, the difference in the current density in the semiconductor wafer can be reduced, and the variation in the height of the bump electrode can be remarkably reduced. Is something that can be done.
【００１２】[0012]
【実施例】本発明の一実施例について、図１〜図８を参
照しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.
【００１３】図１〜図５は本発明の一実施例におけるウ
エーハメッキバンプ形成方法の工程順断面図である。1 to 5 are cross-sectional views in order of the steps of a method for forming a wafer-plated bump according to an embodiment of the present invention.
【００１４】図１は、拡散工程完了時の状態を示す。半
導体ウエーハ５上にＰＳＧ等の層間絶縁膜６をスクライ
ブライン５ａ以外の領域及び半導体素子と後に形成する
Ａｌ等の配線金属層７とを接続する領域（図示せず）以
外に気相成長技術、写真蝕刻技術等により形成する。次
にＡｌ等の配線金属層７を所定の領域に形成し、さらに
プラズマナイトライド等の表面保護膜８をスクライブラ
イン５ａと後にバンプ電極を形成するパッド開口部７ａ
以外の領域に形成し拡散工程を完了する。FIG. 1 shows the state at the completion of the diffusion process. A vapor phase growth technique is provided on the semiconductor wafer 5 except for a region other than the scribe line 5a of the interlayer insulating film 6 such as PSG and a region (not shown) for connecting the semiconductor element and a wiring metal layer 7 such as Al formed later. It is formed by photo-etching technology or the like. Next, a wiring metal layer 7 of Al or the like is formed in a predetermined region, and a surface protection film 8 of plasma nitride or the like is further formed on the scribe line 5a and a pad opening 7a for forming a bump electrode later.
The diffusion process is completed by forming in a region other than.
【００１５】上述の構成によれば、拡散工程完了時には
スクライブライン５ａにおいて半導体ウエーハ表面が露
出している構造を成す。According to the above structure, the surface of the semiconductor wafer is exposed at the scribe line 5a when the diffusion process is completed.
【００１６】次に図２に示す様に、半導体ウエーハ５の
表面全面にバンプ形成時の共通電極とするための導体層
となるバリアメタル層９をスパッタ蒸着法、ＥＢ蒸着法
等により形成する。このバリアメタル層９は通常２〜３
種の金属薄膜（例えば、Ｎｉ−Ｃｒ−Ａｕ，Ｔｉ−Ｐｄ
等）を積層して作られ、スクライブライン５ａにおいて
半導体ウエーハ５と接する。また、スクライブライン
は、半導体ウエーハ全面に均一に分布しているからバリ
アメタル層９と、半導体ウエーハ５とは半導体ウエーハ
５の表面全面において均一に接することになる。Next, as shown in FIG. 2, a barrier metal layer 9 serving as a conductor layer for forming a common electrode for bump formation is formed on the entire surface of the semiconductor wafer 5 by a sputter deposition method, an EB deposition method or the like. This barrier metal layer 9 is usually 2-3
Seed metal thin films (eg, Ni-Cr-Au, Ti-Pd)
Etc.) and are in contact with the semiconductor wafer 5 at the scribe line 5a. Since the scribe lines are evenly distributed over the entire surface of the semiconductor wafer, the barrier metal layer 9 and the semiconductor wafer 5 are in uniform contact with each other over the entire surface of the semiconductor wafer 5.
【００１７】そして図３に示すように、写真蝕刻技術に
てバンプ電極を形成する箇所のみに開口部９ａを設けた
フォトレジストパターン１０を形成する。また、バンプ
電極を形成するために、表面加工の終了したウエーハ５
のウエーハメッキ用治具で固定する。半導体ウエーハ５
の裏面と接触する側のウエーハメッキ用治具の支持部１
３の表面は導電性の高い電極層（たとえば白金層）１１
が露出していて、半導体ウエーハ５の裏面全面とウエー
ハメッキ用治具の電極層１１とが密着している。Then, as shown in FIG. 3, a photoresist pattern 10 having an opening 9a is formed only in a portion where a bump electrode is to be formed by a photo-etching technique. Further, in order to form bump electrodes, the wafer 5 whose surface has been finished is processed.
Fix with the wafer plating jig. Semiconductor wafer 5
Support part 1 of the jig for wafer plating on the side that contacts the back surface of the wafer
The surface of 3 has an electrode layer of high conductivity (for example, a platinum layer) 11
Is exposed and the entire back surface of the semiconductor wafer 5 and the electrode layer 11 of the wafer plating jig are in close contact with each other.
【００１８】上記構成により半導体ウエーハ５の裏面に
密着させ電極層１１より半導体ウエーハ５の内部を通
じ、半導体ウエーハ５の表面のバリアメタル層９に均一
に電流を与えることができる。With the above structure, a current can be uniformly applied to the barrier metal layer 9 on the front surface of the semiconductor wafer 5 from the electrode layer 11 through the inside of the semiconductor wafer 5 while being in close contact with the back surface of the semiconductor wafer 5.
【００１９】上記のように治具に固定された半導体ウエ
ーハ５を図８に示す様にメッキ液１６中に浸し、一方を
対向電極１５に、他方を電極層１１に接続した電源１４
より電極層１１に適切な電流密度（例えば０．１〜０．
４Ａ／ｄｍ2）を与える様に印加電流を調整し、適切な
時間、電源１４を稼動させると、１０〜２０μｍ程度の
高さのバンプ電極１２を図４に示すように形成すること
になる。The semiconductor wafer 5 fixed to the jig as described above is dipped in a plating solution 16 as shown in FIG. 8, and one side is connected to the counter electrode 15 and the other side is connected to the electrode layer 11 to form a power supply 14.
More appropriate current density for the electrode layer 11 (for example, 0.1 to 0.
The applied current is adjusted so as to give 4 A / dm 2 ) and the power supply 14 is operated for an appropriate time, so that the bump electrode 12 having a height of about 10 to 20 μm is formed as shown in FIG.
【００２０】さらに、図５に示す様に、バンプ形成時の
共通電極として用いたバリアメタル層９を、バンプ電極
の周辺部以外を写真蝕刻技術により取り除く。Further, as shown in FIG. 5, the barrier metal layer 9 used as the common electrode at the time of forming bumps is removed by a photo-etching technique except for the peripheral portions of the bump electrodes.
【００２１】次に、本発明に用いるウエーハメッキ用治
具について図６，図７を参照にしながら説明する。Next, the wafer plating jig used in the present invention will be described with reference to FIGS. 6 and 7.
【００２２】図に示すようにウエーハメッキ用治具は、
支持部１３と固定部１９と電極層１１から成っている。
支持部１３と固定部１９の表面はテフロン等の絶縁物で
できており、支持部１３のウエーハ５と接触する側の表
面は、電極１４とウエーハ裏面とを接続するための導電
性の高い電極層１１（例えば白金等）が露出している。
この露出した電極層１１とウエーハ５の裏面全面とが完
全に接触する様ウエーハ５のオリエンテーションフラッ
ト部５ｂをウエーハメッキ用治具の固定部１９で固定す
る。ウエーハメッキ用治具は固定する手段として例えば
スプリングを利用したクリップ状の構造をしている。As shown in the figure, the jig for wafer plating is
It is composed of a supporting portion 13, a fixing portion 19 and an electrode layer 11.
The surfaces of the supporting portion 13 and the fixing portion 19 are made of an insulating material such as Teflon, and the surface of the supporting portion 13 on the side in contact with the wafer 5 is an electrode having high conductivity for connecting the electrode 14 and the back surface of the wafer. The layer 11 (eg platinum or the like) is exposed.
The orientation flat portion 5b of the wafer 5 is fixed by the fixing portion 19 of the wafer plating jig so that the exposed electrode layer 11 and the entire back surface of the wafer 5 are completely in contact with each other. The wafer plating jig has a clip-like structure using, for example, a spring as a fixing means.
【００２３】このように本発明の実施例によれば、ウエ
ーハ５の裏面全面に電極層１１を密着させることによ
り、電極層１１とバリアメタル層９との距離が均一にな
り、その結果半導体ウエーハ内の電流密度の差違を小さ
くすることができ、バンプ電極高さのばらつきを著しく
減少することができる。As described above, according to the embodiment of the present invention, the electrode layer 11 is brought into close contact with the entire back surface of the wafer 5, so that the distance between the electrode layer 11 and the barrier metal layer 9 becomes uniform, and as a result, the semiconductor wafer is obtained. It is possible to reduce the difference in the current density in the inside, and to significantly reduce the variation in the bump electrode height.
【００２４】なお上述の実施例では、半導体ウエーハを
メッキ液中に浸し、バンプ形成を行う方法（ディップ方
法）を用いたが、メッキ液をシリコンウエーハ表面に噴
き付け、バンプ形成を行う方法（噴流カップ方法）を用
いても何らさしつかえない。In the above embodiment, the method of dipping the semiconductor wafer in the plating solution to form bumps (dip method) was used. However, the plating solution is sprayed onto the surface of the silicon wafer to form bumps (jet flow). You can use the cup method).
【００２５】[0025]
【発明の効果】以上の実施例から明らかなように本発明
によれば、ウエーハの裏面全面を電極部とし適切な電流
を均一に与えバンプ形成を行うことにより、ウエーハ面
内での電流密度の差違が小さく抑えられ、バンプ電極高
さのウエーハ面内ばらつきが著しく減少するようなメッ
キバンプ形成方法及びそれに用いるウエーハメッキ用治
具を提供できる。As is apparent from the above-described embodiments, according to the present invention, the entire back surface of the wafer is used as an electrode portion and an appropriate current is uniformly applied to form a bump so that the current density in the wafer surface can be reduced. It is possible to provide a plating bump forming method in which the difference is suppressed to a small level and the variation in bump electrode height within the wafer is significantly reduced, and a wafer plating jig used therefor.
【図１】本発明の実施例のメッキバンプ形成方法を示す
工程順断面図1A to 1C are cross-sectional views in order of the steps, showing a plating bump forming method according to an embodiment of the present invention.
【図２】本発明の実施例のメッキバンプ形成方法を示す
工程順断面図2A to 2C are cross-sectional views in order of the steps, showing a plating bump forming method according to an embodiment of the present invention.
【図３】本発明の実施例のメッキバンプ形成方法を示す
工程順断面図3A to 3C are cross-sectional views in order of the steps, showing a plating bump forming method according to an embodiment of the present invention.
【図４】本発明の実施例のメッキバンプ形成方法を示す
工程順断面図4A to 4C are cross-sectional views in order of the processes, showing a plating bump forming method according to an embodiment of the present invention.
【図５】本発明の実施例のメッキバンプ形成方法を示す
工程順断面図5A to 5C are cross-sectional views in order of the steps, showing a method for forming a plating bump according to an embodiment of the present invention.
【図６】本発明の実施例のメッキバンプ形成方法に用い
るウエーハメッキ用治具の概略図FIG. 6 is a schematic view of a wafer plating jig used in the method for forming plating bumps according to the embodiment of the present invention.
【図７】本発明の実施例のメッキバンプ形成方法に用い
るウエーハメッキ用治具の断面図FIG. 7 is a cross-sectional view of a wafer plating jig used in the method for forming plating bumps according to the embodiment of the present invention.
【図８】本発明の実施例のメッキバンプ形成方法を示す
図FIG. 8 is a diagram showing a method for forming plated bumps according to an embodiment of the present invention.
【図９】従来のメッキバンプ形成方法に用いるウエーハ
メッキ用治具の概略図FIG. 9 is a schematic view of a wafer plating jig used in a conventional plating bump forming method.
【図１０】従来のメッキバンプ形成方法に用いるウエー
ハメッキ用治具の断面図FIG. 10 is a sectional view of a wafer plating jig used in a conventional plating bump forming method.
【図１１】従来のメッキバンプ形成方法を示す図FIG. 11 is a diagram showing a conventional plating bump forming method.
１ ウエーハメッキ用治具 ２ 電源 ３ 電極層 ４ 半導体ウエーハ ４ａ オリエンテーションフラット部 ５ 半導体ウエーハ ５ａ スクライブライン ５ｂ オリエンテーションフラット部 ６ 層間絶縁膜 ７ 配線金属層 ７ａ パッド開口部 ８ 表面保護膜 ９ バリアメタル層 ９ａ バンプ電極形成開口部 １０ フォトレジストパターン １１ 電極層 １２ バンプ電極 １３ 治具の支持部 １４ 電源 １５ 対向電極 １６ メッキ液 １７ 対向電極 １８ メッキ液 １９ 治具の固定部 1 wafer plating jig 2 power supply 3 electrode layer 4 semiconductor wafer 4a orientation flat part 5 semiconductor wafer 5a scribe line 5b orientation flat part 6 interlayer insulating film 7 wiring metal layer 7a pad opening 8 surface protective film 9 barrier metal layer 9a bump Electrode formation opening 10 Photoresist pattern 11 Electrode layer 12 Bump electrode 13 Jig support 14 Power supply 15 Counter electrode 16 Plating solution 17 Counter electrode 18 Plating solution 19 Fixing part of jig
Claims (2)
ハ表面の全領域にわたり実質的に均一な分布をもって前
記半導体ウエーハと接する導体層を設け、前記半導体ウ
エーハの裏面全面より前記半導体ウエーハを通じ前記導
体層に電流を与え、前記導体層上の絶縁膜の開口部にバ
ンプ電極を形成するメッキバンプ電極形成方法。1. A semiconductor layer is provided on the front surface of the semiconductor wafer with a conductor layer in contact with the semiconductor wafer with a substantially uniform distribution over the entire area of the surface of the semiconductor wafer, and the conductor layer is formed from the entire back surface of the semiconductor wafer through the semiconductor wafer. A method for forming a plated bump electrode, which comprises applying a current to form a bump electrode in an opening of an insulating film on the conductor layer.
記ウエーハ裏面全面と接続するための電極層をもち、前
記ウエーハ裏面と前記電極層とが完全に接触するように
固定する手段を備えたウエーハメッキ用治具。2. A means having an electrode layer for contacting substantially the entire back surface of the wafer on the side in contact with the back surface of the wafer, and fixing means for fixing the back surface of the wafer and the electrode layer so that they are in complete contact with each other. A jig for wafer plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3331681A JPH05166815A (en) | 1991-12-16 | 1991-12-16 | Plated bump forming method and wafer plating jig used therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3331681A JPH05166815A (en) | 1991-12-16 | 1991-12-16 | Plated bump forming method and wafer plating jig used therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05166815A true JPH05166815A (en) | 1993-07-02 |
Family
ID=18246391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3331681A Pending JPH05166815A (en) | 1991-12-16 | 1991-12-16 | Plated bump forming method and wafer plating jig used therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05166815A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0877419A3 (en) * | 1997-05-09 | 1999-08-18 | Mcnc | Methods of electroplating solder bumps of uniform height on integrated circuit substrates |
| US6692629B1 (en) * | 2000-09-07 | 2004-02-17 | Siliconware Precision Industries Co., Ltd. | Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer |
| US8084349B2 (en) | 2009-11-09 | 2011-12-27 | Samsung Electro-Mechanics Co., Ltd. | Method for forming post bump |
| JP2012508814A (en) * | 2008-11-14 | 2012-04-12 | レプリサウルス グループ エスエーエス | System for plating a conductive substrate and substrate holder for holding a conductive substrate during the plating |
| WO2019130859A1 (en) * | 2017-12-27 | 2019-07-04 | 株式会社カネカ | Method for producing photoelectric conversion element, tool for plating, and plating apparatus |
| JP2022186735A (en) * | 2016-02-25 | 2022-12-15 | ニューサウス イノベーションズ ピーティーワイ リミテッド | Method and Apparatus for Treating the Surface of TCO Materials in Semiconductor Devices |
-
1991
- 1991-12-16 JP JP3331681A patent/JPH05166815A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0877419A3 (en) * | 1997-05-09 | 1999-08-18 | Mcnc | Methods of electroplating solder bumps of uniform height on integrated circuit substrates |
| US6117299A (en) * | 1997-05-09 | 2000-09-12 | Mcnc | Methods of electroplating solder bumps of uniform height on integrated circuit substrates |
| EP1892754A3 (en) * | 1997-05-09 | 2008-03-19 | Unitive International Limited | Method of electroplating solder bumps of uniform height on integrated circuit substrates |
| US6692629B1 (en) * | 2000-09-07 | 2004-02-17 | Siliconware Precision Industries Co., Ltd. | Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer |
| JP2012508814A (en) * | 2008-11-14 | 2012-04-12 | レプリサウルス グループ エスエーエス | System for plating a conductive substrate and substrate holder for holding a conductive substrate during the plating |
| US8084349B2 (en) | 2009-11-09 | 2011-12-27 | Samsung Electro-Mechanics Co., Ltd. | Method for forming post bump |
| JP2022186735A (en) * | 2016-02-25 | 2022-12-15 | ニューサウス イノベーションズ ピーティーワイ リミテッド | Method and Apparatus for Treating the Surface of TCO Materials in Semiconductor Devices |
| WO2019130859A1 (en) * | 2017-12-27 | 2019-07-04 | 株式会社カネカ | Method for producing photoelectric conversion element, tool for plating, and plating apparatus |
| JPWO2019130859A1 (en) * | 2017-12-27 | 2020-12-17 | 株式会社カネカ | Manufacturing method of photoelectric conversion element, plating jig, plating equipment |
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