JPH05157806A - Constant temperature accelerated testing device for semiconductor - Google Patents

Abstract

PURPOSE:To provide a low cost constant temperature accelerated testing device for semiconductors by reducing the number of component elements. CONSTITUTION:A testing device possesses a good semiconductor element 90a, which is a non-defective one out of semiconductor elements to be tested, and a waveform generating unit 6, which feeds input signals having assigned waveforms to the good semiconductor element 90a and the semiconductor element to be tested. The testing device possesses also a waveform detecting unit 7, which compares the output signal waveform of the semiconductor element to be tested and the output signal waveform of the good semiconductor element, being output based on the input signals thereto, and determines whether the semiconductor element to be tested is good or bad, based on the result of the comparison thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor constant temperature accelerating test device for judging whether a semiconductor element is good or bad.

[0002]

2. Description of the Related Art In a semiconductor device manufacturing process, a semiconductor constant temperature acceleration test is carried out in which a burn-in test is carried out for the purpose of finding semiconductor devices having inherent defects or latent defect factors and removing them before shipment as products. Devices have been used for some time. The burn-in test is an acceleration test in which a semiconductor element to be tested is placed under high temperature and a test voltage higher than or equal to the rating is applied, and in the semiconductor constant temperature acceleration test apparatus, a plurality of semiconductor elements to be tested are mounted. The substrate is placed in a constant temperature bath, the constant temperature bath is heated, and a test voltage is simultaneously applied to each semiconductor element on the substrate via a signal line formed on the substrate, so that the semiconductor elements are simultaneously applied to these semiconductor elements. A burn-in test is conducted.

FIG. 1 is a block diagram showing a circuit configuration of a main part of a conventional semiconductor constant temperature acceleration test apparatus. In the figure, 5 is a control unit that performs various controls of the constant temperature acceleration test apparatus. The control unit 5 includes a CPU 50, a program memory 51, an input waveform pattern memory 52, and an expected value pattern memory 53. It is configured.

The program memory 51 stores the internal temperature of the thermostatic chamber, the power supply voltage for operating the semiconductor element, the voltage value of the waveform of the signal input to the semiconductor element (hereinafter referred to as the input waveform), and the output signal from the semiconductor element. The detected waveform judgment value, which is a judgment value for judging whether the detection waveform is good or bad, and a program in which the semiconductor element insertion time into the constant temperature bath is described in correspondence with the semiconductor element under test are stored, and the input waveform is stored. The expected pattern memory 52 stores a program in which the pattern of the input waveform is described, and the expected value pattern memory
Reference numeral 53 stores a program describing the expected value of the pattern of the detected waveform. These program memories 51,
The programs stored in the input waveform pattern memory 52 and the expected value pattern memory 53 are read by the CPU 50 and executed.

The CPU 50 generates an input waveform pattern according to a program stored in the input waveform pattern memory 52 for the waveform generation drivers 61, 61, ... Of the waveform generator 6 for generating an input waveform. , And the waveform generating drivers 61, 61, ... Generate an input waveform based on the control signal. The input waveforms generated by the waveform generating drivers 61, 61, ... Are given to the substrate through a predetermined path and input to each semiconductor element on the substrate through a common input signal line formed on the substrate. It is supposed to be done.

Further, the output signal from the output terminal of each semiconductor element passes through a separate output signal line formed on the substrate and a predetermined path, and then the comparators 71, 7 of the waveform detecting section 7 are provided.
It is designed to be applied to one of the input terminals 1 ,.
The number of output signal lines and the comparators 71, 71,
The number of ... Is provided as many as the number of output terminals × the number of attachable elements. Further, the expected value of the pattern of the detected waveform is given from the expected value pattern memory 53 to the other input terminal of the comparators 71, 71, .... The comparators 71, 71, ... Compare the detected waveform, which is the waveform of the output signal of each semiconductor element, with the expected value of the pattern of the detected waveform stored in the expected value pattern memory 53. The comparison result is given to the CPU 50.

Next, the operation of the semiconductor constant temperature acceleration test apparatus thus configured will be described. First, the CPU 50 supplies power to each semiconductor element for operation, reads a program from the input waveform pattern memory 52, executes the program, and outputs the waveform generation drivers 61, 61, 61, 61 of the waveform generator 6.
Give a control signal to. Waveform generation driver 61,61, ...
Generates an input waveform based on the control signal, and the input waveform is input through a common input line to the semiconductor element mounted on the substrate. The semiconductor element operates on the basis of the input waveform, and its output signal is given to the comparators 71, 71, ... Of the waveform detecting section 7 via the separate output lines.

Further, the expected values of the detected waveform patterns are given to the comparators 71, 71, ..., And the comparators 71, 71 ,. The expected value of the pattern is compared, and if they match, it is determined that the semiconductor element is a good product, and if they do not match, it is determined that the semiconductor element is a defective product. Then, information indicating this determination result (hereinafter referred to as good / bad determination information) is provided to the CPU 50. The CPU 50 performs a predetermined process such as displaying the determination result on a predetermined display unit.

[0009]

In recent years, the number of input / output terminals of a semiconductor element has been increasing. However, when the number of input / output terminals is increased in this way, in the conventional semiconductor constant temperature acceleration test apparatus as described above, , The waveform generating drivers 61, 61, ... Of the waveform generating section 6 can use a common input waveform for each input terminal even if the number of input terminals increases, so it is necessary to increase the number. Although not provided, when the number of output terminals increases, the number of comparators 71, 71, ... Of the waveform detecting section 7 must be increased by the increased amount. In addition, the storage capacity of the expected value pattern memory 53 must be increased accordingly. Therefore, in the conventional semiconductor constant temperature acceleration test apparatus, when the number of input / output terminals of the semiconductor element increases, there is a problem that the apparatus becomes expensive due to the increase in the number of the constituent elements and the capacity of the constituent elements.

The present invention has been made in view of such circumstances, and it is an object of the present invention to provide an inexpensive semiconductor constant temperature acceleration test apparatus by reducing the number of its constituent elements.

[0011]

SUMMARY OF THE INVENTION A semiconductor constant temperature acceleration test apparatus according to the present invention comprises a non-defective semiconductor element which is a non-defective semiconductor element to be tested, a means for applying an input signal of a predetermined waveform to the semiconductor element to be tested, and the input. Means for comparing the output signal waveforms of the semiconductor device under test and the non-defective semiconductor device output based on a signal, and means for determining whether the semiconductor device under test is good or defective based on the comparison result of the means. In the above configuration, the waveform of the output signal of the semiconductor element to be tested is compared with the waveform of the output signal of the non-defective semiconductor element to determine pass / fail of the semiconductor element to be tested.

[0012]

According to the present invention, by comparing the waveform of the output signal of the semiconductor device under test with respect to the same input signal and the waveform of the output signal of the non-defective semiconductor device, the pass / fail of the semiconductor device under test can be determined. Since the determination is made, it is not necessary to provide means for storing the expected value of the waveform of the output signal of the semiconductor device under test as the comparison data, and the number of constituent elements of the device can be reduced as compared with the related art.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 2 is a perspective view showing the appearance of a semiconductor constant temperature acceleration test apparatus according to the present invention.

In the figure, reference numeral 1 is a box-shaped apparatus body. On the right side of the front of the device body 1, from the bottom to the top,
11, a power control unit 12, and a display unit 13 for displaying the power status
And are lined up. Further, on the left side of the front surface of the apparatus main body 1, a constant temperature chamber door for accommodating semiconductor elements is provided above the door.
14 is provided below the main switch 15 of the device.
And a temperature setting volume for setting the temperature of the constant temperature bath
16, a pilot lamp 17 that indicates the operating state of a heater for heating the constant temperature bath, and a recording unit 18 that records the temporal change in the temperature inside the constant temperature bath.

FIG. 3 is a schematic block diagram showing the internal structure of the semiconductor constant temperature acceleration test apparatus. In the figure, 2 is a thermostat, and inside the thermostat 2, a plurality of guide rails 21, 21, ... For loading semiconductor element mounting boards 9 for mounting semiconductor elements 90, 90 ,. Are provided in parallel at predetermined intervals. A heater 3 for heating the constant temperature bath is provided below the constant temperature bath 2. Also, the guide rails 21, 21,
In the vicinity of each of the ..., connectors 81, 81, ... into which parts of the respective semiconductor element mounting boards 9 inserted in the guide rails 21, 21, ... are inserted are provided.

Below the connectors 81, 81, ..., A power supply unit 4 for supplying electric power to each part of the semiconductor constant temperature acceleration test apparatus.
Also provided is a control unit 5 for performing various controls relating to the operation of the semiconductor constant temperature acceleration test apparatus. The controller 5 detects the heater 3, the waveform generator 6 that is the source of the input waveform generated to perform the constant temperature acceleration test, and the waveform of the signal output based on the input waveform to detect the semiconductor to be tested. It is connected to a waveform detection section 7 that determines whether the element is good or bad, and various signals are transmitted to and received from these. In addition, a good semiconductor element 90a serving as a reference for judging whether the semiconductor element is good or bad is arranged above the waveform generator 6 and the waveform detector 7. The non-defective semiconductor element 90a, the waveform generator 6 and the waveform detector 7, and the connectors 81, 81, ... Are connected by a signal cable 82 having a plurality of signal lines.

FIG. 4 is a perspective view showing the structure of the semiconductor element mounting substrate 9 housed in the constant temperature bath 2. The semiconductor element mounting substrate 9 has a rectangular plate shape, and a connector connecting portion 91 to be inserted into the connectors 81, 81, ...
Is provided. On the upper surface of the semiconductor element mounting substrate 9,
A plurality of test element sockets 92, 92 for mounting the semiconductor elements 90, 90 to be tested are provided. In the semiconductor element mounting substrate 9, the test element sockets 92, 92, ...
, And the connector connection portion 91 between the sockets 92, 92, ...
, A common power line 93 and an input signal line 94, and an independent output signal line 95 is printed for each output terminal of each socket 92, 92, ....

Next, the configurations of the controller 5, the waveform generator 6, and the waveform detector 7 will be described. FIG. 5 is a block diagram showing a detailed configuration of the controller 5, the waveform generator 6, and the waveform detector 7 of the semiconductor constant temperature acceleration test apparatus. In the figure, 5 is a control unit for performing various controls of the constant temperature acceleration test apparatus.
Is composed of a CPU 50, a program memory 51, and an input waveform pattern memory 52.

The program memory 51 has an internal temperature of the constant temperature bath 2, a power supply voltage for operating the semiconductor element, and a waveform of a signal input to the semiconductor element (hereinafter referred to as an input waveform).
Voltage value of the semiconductor device 90, 90, ..., The detection waveform judgment value which is a judgment value for judging whether the detection waveform of the output signal from the semiconductor device 90, 90 ,. A program in which the turning-on time is described in correspondence with the semiconductor device to be tested is stored, and the input waveform pattern memory 52 stores the program in which the pattern of the input waveform is described.
The programs stored in the program memory 51 and the input waveform pattern memory 52 are read by the CPU 50 and executed.

The CPU 50 generates an input waveform pattern according to the program stored in the input waveform pattern memory 52 for the waveform generation drivers 61, 61, ... Of the waveform generator 6 for generating the input waveform. , And the waveform generating drivers 61, 61, ... Generate an input waveform based on the control signal. The input waveforms generated by the waveform generating drivers 61, 61, ... Are given to the non-defective semiconductor element 90a via the signal cable 82, and also passed through the signal cable 82, the connector connecting portion 91 and the input signal line 94. 90, ...

The output signals of the semiconductor elements 90, 90, ... Are supplied to one of the input terminals of the comparators 71, 71 ,. It has become. Note that the comparator
The number of 71, 71, ... Is provided by the number of output terminals x number of mountable elements. The output signal of the non-defective semiconductor element 90a is applied to the other input terminal of the comparators 71, 71, ... Via the signal cable 82. comparator
71, 71, ... compares the output signal waveforms of the semiconductor elements 90, 90, ... With the output signal waveforms of the non-defective semiconductor element 90a, and the comparison result is given to the CPU 50. It has become.

Next, the operation of the semiconductor constant temperature acceleration test device thus constructed will be described. First, the CPU 50 supplies electric power for operation to the semiconductor elements 90, 90, ... And the non-defective semiconductor element 90a, reads a program from the input waveform pattern memory 52, executes the program, and executes the program. Control signals are applied to the waveform generation drivers 61, 61, .... The waveform generating drivers 61, 61, ... Generate an input waveform based on the control signal, and the input waveform is input to the semiconductor elements 90, 90 ,. The semiconductor elements 90, 90, ... And the non-defective semiconductor element 90a operate based on the input waveform, and their output signals are given to the comparators 71, 71 ,.

In the comparators 71, 71, ..., The semiconductor element 9
The output signal waveforms of 0, 90, ... are compared with the output signal waveforms of the non-defective semiconductor element 90a. If they match, it is determined that the semiconductor element 90 to be tested is non-defective and they match. If not, it is determined that the semiconductor element 90 is defective. Then, information indicating this determination result (hereinafter referred to as good / bad determination information) is given to the CPU 50,
Performs a predetermined process such as displaying the determination result on a predetermined display unit.

Next, another embodiment of the semiconductor constant temperature acceleration test apparatus according to the present invention will be described. FIG. 6 is a perspective view showing the configuration of a semiconductor element mounting substrate 9 representing another embodiment of the constant temperature acceleration test apparatus according to the present invention. In FIG. 6, the parts corresponding to those in FIG. Is omitted.

On the upper surface of the semiconductor element mounting substrate 9, a plurality of test element sockets 92, 92, ... For mounting the semiconductor elements 90, 90 ,. Non-defective element socket for mounting the semiconductor element 90a
92a is provided. Sockets for these test elements
92, 92, ..., And between the non-defective element socket 92a and the connector connection portion 91, a power supply line 93 and an input signal line 94 common to the sockets 92, 92 ,. Independent output signal line 95 for each 92,92, ..., 92a output terminal
Is printed wiring. By mounting the non-defective semiconductor element 90a on the semiconductor element mounting substrate 9 in this manner, the device body 1
It is not necessary to dispose the non-defective semiconductor element 90a therein.

In the semiconductor constant temperature acceleration test apparatus as described above, the expected value pattern memory provided in the conventional apparatus is unnecessary, so that the number of constituent elements is smaller than that in the conventional apparatus and the cost of the apparatus can be reduced.

Next, an explanation will be given of a semiconductor constant temperature accelerating test device which is capable of reducing the number of constituent elements as compared with the conventional device other than the semiconductor constant temperature accelerating test device as described above. FIG. 7 is a block diagram showing a detailed configuration of the control unit 5, the waveform generation unit 6, and the waveform detection unit 7 of the semiconductor constant temperature acceleration test apparatus capable of reducing the number of constituent elements, which corresponds to FIG. 5 in FIG. The same number is assigned to each and the description thereof is omitted.

The control unit 5 includes a CPU 50 and a program memory.
51, an input waveform pattern memory 52, and an expected value pattern memory 53.

The program memory 51 tests the internal temperature of the constant temperature bath 2, the power supply voltage for operating the semiconductor elements, the voltage value of the input waveform, and the time for loading the semiconductor elements 90, 90, ... Into the constant temperature bath 2. The program described corresponding to the target semiconductor element is stored, and the input waveform pattern memory 52 is
The expected value pattern memory 53, which stores an initial setting pattern of pseudo random number generation in a pseudo random number generation unit 60 described later, is stored.
Stores a program describing an expected value pattern of data compressed by the data compression unit 70 described later. The programs stored in the program memory 51, the input waveform pattern memory 52, and the expected value pattern memory 53 are read by the CPU 50 and executed.

The CPU 50 is a pseudo random number generator of the waveform generator 6.
The initial setting pattern stored in the input waveform pattern memory 52 is given to 60, and the operation is performed to the data compression section 70 of the waveform detection section 7 by the pseudo random number generation section 60.
A control signal for synchronizing with the operation of is given. In the waveform generator 6, the pseudo random number generator 60 is composed of a linear feedback shift register of serial input-parallel output, and the output of each bit of the pseudo random number generator 60 is one of the waveform generating drivers 61, 61 ,. To be given to. The input waveform based on the pseudo-random number generated by the waveform generation driver 61, 61, ...
2, via the connector connecting portion 91 and the input signal line 94, it is applied to the semiconductor elements 90, 90, ....

The output signals of the semiconductor elements 90, 90, ... Are given to the data compression section 70 of the waveform detection section 7 via the output signal line 95, the connector connection section 91 and the signal cable 82. The data compression unit 70 is composed of a parallel input-serial output linear feedback shift register,
The output signals of the semiconductor devices 90, 90, ... Are given to each bit of the data compression unit 70, and the data compression unit 70 compresses the waveform data of these output signals, and this compressed data is stored in one of the comparators 71. It is designed to be applied to the input terminal. Further, the expected value pattern of the compressed data is applied from the expected value pattern memory 53 to the other input terminal of the comparators 71, 71, .... The comparator 71 compares the compressed data of the waveforms of the output signals of the semiconductor devices 90, 90, ... With the expected value pattern, and the comparison result is given to the CPU 50.

Next, the operation of the semiconductor constant temperature acceleration test apparatus thus configured will be described. First, the CPU 50 reads an initial setting pattern for pseudo random number generation from the input waveform pattern memory 52, and supplies this to the pseudo random number generating section 60 of the waveform generating section 6. The pseudo random number generator 60 thereby gives the pseudo random number data to the waveform generating drivers 61, 61, .... The waveform generating drivers 61, 61, ... Generate random input waveforms based on the pseudo random number data, and the input waveforms are input to the semiconductor elements 90, 90 ,. Semiconductor element 90,9
0 operate on the basis of the input waveforms, and output signals of the semiconductor devices 90, 90, ... Based on these input waveforms are given to the data compression unit 70 of the waveform detection unit 7.

The data compression section 70 compresses the waveform data of the output signals of the semiconductor elements 90, 90, ... In synchronization with the pseudo random number generation section 60 based on the control signal given from the CPU 50. The compression of this data is repeatedly performed during a predetermined charging time, and after the charging time ends, the compressed data is given to the comparator 71. The comparator 71 compares the compressed data from the data compression unit 70 with the expected value pattern of the compressed data from the expected value pattern memory 53, and if they match, determines that the semiconductor element 90 is a good product. If they do not match, it is determined that the semiconductor element 90 is defective. Then, information indicating this determination result (hereinafter referred to as good / defective determination information) is given to the CPU 50, and the CPU 50 executes a predetermined semiconductor element identification analysis on the determination result and determines that it is defective. Predetermined processing is performed, such as determining the determined semiconductor element 90 and displaying the result of the determination on a predetermined display unit.

FIG. 8 is a block diagram showing the detailed structure of the control section 5, the waveform generating section 6, and the waveform detecting section 7 of another semiconductor constant temperature acceleration test apparatus capable of reducing the number of constituent elements.
In FIG. 8, the same parts as those in FIG. 7 are designated by the same reference numerals and the description thereof will be omitted.

In the semiconductor constant temperature acceleration test apparatus of FIG.
The input waveform pattern memory 52 in the semiconductor constant temperature acceleration test device is abolished, and the pseudo random number generation unit 60 stores the initial setting pattern of pseudo random number generation. Even with such a configuration, the constant temperature acceleration test of FIG. It is possible to perform the same operation as the device.

In the semiconductor constant temperature acceleration test apparatus of FIGS. 7 and 8 as described above, the number of comparators 71 in the waveform detecting section 7 can be greatly reduced, so that the number of constituent elements is reduced and the apparatus cost is reduced as compared with the conventional case. it can.

[0037]

As described in detail above, according to the present invention,
Since the waveform of the output signal of the semiconductor device under test for the same input signal is compared with the waveform of the output signal of the non-defective semiconductor device, it is determined whether the semiconductor device under test is good or defective. As a result, it is not necessary to provide a means for storing the expected value of the waveform of the output signal of the semiconductor device under test, the number of constituent elements of the device is reduced as compared with the conventional one, and the cost of the device can be reduced. ..

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a main part of a conventional semiconductor constant temperature acceleration test apparatus.

FIG. 2 is a perspective view showing an appearance of a semiconductor constant temperature acceleration test apparatus according to the present invention.

FIG. 3 is a schematic block diagram showing an internal configuration of a semiconductor constant temperature acceleration test apparatus according to the present invention.

FIG. 4 is a perspective view showing a configuration of a semiconductor element mounting substrate.

FIG. 5 is a block diagram showing a detailed configuration of a control unit, a waveform generation unit, and a waveform detection unit of the semiconductor constant temperature acceleration test apparatus of the present invention.

FIG. 6 is a perspective view showing the configuration of a semiconductor element mounting substrate showing another embodiment of the semiconductor constant temperature acceleration test apparatus of the present invention.

FIG. 7 is a block diagram showing a detailed configuration of a control unit, a waveform generation unit, and a waveform detection unit of the semiconductor constant temperature acceleration test apparatus capable of reducing the number of constituent elements.

FIG. 8 is a block diagram showing a detailed configuration of a control unit, a waveform generation unit, and a waveform detection unit of another semiconductor constant temperature acceleration test apparatus capable of reducing the number of constituent elements.

[Explanation of symbols]

 5 Control unit 6 Waveform generation unit 7 Waveform detection unit 50 CPU 61 Waveform generation driver 71 Comparator 90 Semiconductor element 90a Non-defective semiconductor element

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[Procedure amendment]

[Submission date] May 7, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction content]

FIG. 3 is a schematic block diagram showing the internal structure of the semiconductor constant temperature acceleration test apparatus. Figure 2 is a constant temperature bath,該恒the temperature tank 2, the semiconductor elements 90, 90 will be described later, ... semiconductor element mounting substrate 9 a plurality to plurality loading guide rails 21, 21 for mounting, ... Are provided in parallel at predetermined intervals. A heater 3 for heating the constant temperature bath is provided below the constant temperature bath 2. Also, the guide rails 21, 21,
In the vicinity of each of the ..., connectors 81, 81, ... into which parts of the respective semiconductor element mounting boards 9 inserted in the guide rails 21, 21, ... are inserted are provided.

Claims (1)

[Claims] 1. A test target semiconductor element arranged in a thermostatic chamber is provided with an input signal of a predetermined waveform, and the test target is output based on the waveform of the output signal of the test target semiconductor element output based on the input signal. In a semiconductor constant temperature acceleration test apparatus configured to determine whether a semiconductor element is good or bad, a non-defective semiconductor element that is a good product of the test target semiconductor element and a means for applying an input signal of a predetermined waveform to the test target semiconductor element, Means for comparing the waveforms of the output signals of the semiconductor device under test and the non-defective semiconductor device output based on the input signal, and means for judging the pass / fail of the semiconductor device under test based on the comparison result of the means A semiconductor constant temperature acceleration test apparatus comprising: