JPH05102106A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05102106A JPH05102106A JP28188391A JP28188391A JPH05102106A JP H05102106 A JPH05102106 A JP H05102106A JP 28188391 A JP28188391 A JP 28188391A JP 28188391 A JP28188391 A JP 28188391A JP H05102106 A JPH05102106 A JP H05102106A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- insulating film
- hole
- opening
- shape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 26
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000012212 insulator Substances 0.000 abstract 1
- 230000001678 irradiating effect Effects 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 230000035515 penetration Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置の製造方
法、特に絶縁膜にホール（コンタクトホールやスルーホ
ール）を開孔する方法に係り、更には前記ホールをテー
パー形状に形成する方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a hole (contact hole or through hole) in an insulating film, and more particularly to a method for forming the hole in a tapered shape. is there.
【０００２】[0002]
【従来の技術】半導体装置の製造方法において、絶縁膜
にホール（コンタクトホールやスルーホール）を形成し
た際、上層のステップカバレッジを良くするために前記
ホールの上部をテーパー形状に形成する方法としては、
従来、次の２種類の方法があった。2. Description of the Related Art In a method of manufacturing a semiconductor device, when a hole (a contact hole or a through hole) is formed in an insulating film, a method of forming the upper part of the hole in a tapered shape in order to improve step coverage of an upper layer is known. ,
Conventionally, there are the following two methods.
【０００３】第１の方法はウエットエッチングでホール
上部にテーパーを形成する方法であり、この方法は主と
してロジックＬＳＩ製造工程におけるスルーホール形成
工程で実施され、具体的には図３のように行われる。図
３（ａ）において、１はメタル層、２はその上の酸化シ
リコン系層間マスク絶縁膜、３はその上のフォトレジス
トであり、このフォトレジスト３に、形成するスルーホ
ールに対応して開口部４をフォトリソグラフィー工程に
より形成する。次にＨＦ系溶液に浸して図３（ｂ）に示
すように層間絶縁膜２を途中までエッチングし、その際
フォトレジスト３下にアンダーカットを発生させてスル
ーホールの上部テーパー部分を形成する。その後、フォ
トレジスト３をマスクとして層間絶縁膜２をドライエッ
チングでエッチングすることにより図３（ｃ）に示すよ
うにスルーホールの下部垂直部分を形成し、スルーホー
ル５を完成させる。最後にフォトレジスト３を除去す
る。The first method is a method of forming a taper on the upper portion of the hole by wet etching. This method is mainly carried out in the through hole forming step in the logic LSI manufacturing step, and specifically, it is performed as shown in FIG. .. In FIG. 3A, reference numeral 1 is a metal layer, 2 is a silicon oxide-based interlayer mask insulating film on the metal layer, 3 is a photoresist on the metal layer, and the photoresist 3 has openings corresponding to the through holes to be formed. The part 4 is formed by a photolithography process. Next, the interlayer insulating film 2 is partially etched by immersing in an HF-based solution, and at this time, an undercut is generated under the photoresist 3 to form an upper tapered portion of the through hole. After that, the interlayer insulating film 2 is etched by dry etching using the photoresist 3 as a mask to form a lower vertical portion of the through hole as shown in FIG. 3C, and the through hole 5 is completed. Finally, the photoresist 3 is removed.
【０００４】第２の方法は、ホール形成後、酸化シリコ
ン系層間絶縁膜を熱処理し、フローすることによりテー
パーをつける方法で、この方法は主としてコンタクトホ
ールの形成工程で実施され、具体的には図４のように行
われる。図４（ａ）において、１１はシリコン基板、１
２はその上の酸化シリコン系層間絶縁膜であり、この層
間絶縁膜１２に図示しないフォトレジストをマスクとし
てドライエッチングにより垂直にコンタクトホール１３
を形成する。次に、この構造体をＮ2 雰囲気下で、図５
に示すように、まず炉口にて約８００℃で約５分間放置
し、炉に入れた後、徐々に昇温（５．０℃／分）し、約
９００℃になったら、そのままの温度で約１５分間処理
し、そして徐々に降温（２．５℃／分）し、約８００℃
まで下がったら炉から出して炉口に約５分間放置する。
このようにすると、コンタクトホール１３を形成してい
る層間絶縁膜１２が図４（ｂ）に示すようにフローさ
れ、コンタクトホール１３上部になだらかなテーパー形
状が得られる。The second method is a method of forming a hole and then heat-treating the silicon oxide type inter-layer insulating film to make it taper, and this method is mainly carried out in the step of forming a contact hole. This is performed as shown in FIG. In FIG. 4A, 11 is a silicon substrate, 1
Reference numeral 2 denotes a silicon oxide-based interlayer insulating film formed on the interlayer insulating film 12. A contact hole 13 is vertically formed in the interlayer insulating film 12 by dry etching using a photoresist (not shown) as a mask.
To form. Next, this structure is subjected to N 2 atmosphere as shown in FIG.
As shown in Fig. 1, first leave the furnace at about 800 ° C for about 5 minutes, put it in the furnace, then gradually raise the temperature (5.0 ° C / min), and when it reaches about 900 ° C, keep the temperature as it is. For about 15 minutes, then gradually lowering the temperature (2.5 ° C / min) to about 800 ° C.
When it goes down, remove it from the furnace and leave it in the furnace opening for about 5 minutes.
By doing so, the interlayer insulating film 12 forming the contact hole 13 is flowed as shown in FIG. 4B, and a gentle taper shape is obtained above the contact hole 13.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、ウエッ
トエッチングによってテーパーをつける上記第１の方法
では、ＨＦ系溶液のしみ込み量の安定性が悪いためテー
パー部の寸法の制御性が悪く、しみ込み量が大きい場合
にはテーパー部が広がって隣接するホール間がつながっ
てしまったり、フォトレジストが剥離してしまうという
問題も生じる。また、この第１の方法は工程が複雑にな
る。また、フローによりテーパーをつける上記第２の方
法では、図６に示すようにフロー中に、ホール１３を形
成している酸化シリコン系層間絶縁膜１２がホール１３
の内側へオーバーハング状に張り出し（流れ出し）て、
ホール径を狭めたり、ふさいでしまうという問題点があ
った。However, in the first method in which the taper is made by wet etching, the stability of the penetration amount of the HF-based solution is poor, so that the controllability of the dimension of the tapered portion is poor, and the penetration amount is poor. When the value is large, there is a problem that the taper portion spreads and adjacent holes are connected, or the photoresist is peeled off. In addition, this first method complicates the process. Further, in the second method of tapering by the flow, as shown in FIG. 6, during the flow, the silicon oxide-based interlayer insulating film 12 forming the hole 13 has the hole 13
Overhangs (flows) to the inside of
There was a problem that the hole diameter was narrowed or blocked.
【０００６】この発明は上記の点に鑑みなされたもの
で、従来の方法が寸法および形状の制御性に悪く、一部
は工程も複雑であるという問題点を除去し、工程簡単に
して、かつ制御性良くテーパー形状にホールを形成でき
る半導体装置の製造方法を提供することを目的とする。The present invention has been made in view of the above points, and eliminates the problems that the conventional method is poor in the controllability of the size and shape and the process is complicated in some cases, and simplifies the process, and It is an object of the present invention to provide a method for manufacturing a semiconductor device that can form holes in a tapered shape with good controllability.
【０００７】[0007]
【課題を解決するための手段】この発明では、絶縁膜上
にフォトレジストを形成し、このフォトレジストにホー
ルエッチング用の開口部を形成した後、フォトレジスト
に対する紫外光の照射と加熱処理を行うことにより、前
記開口部部分の段差部がなだらかな形状となるようにフ
ォトレジストを変形させ、その後ドライエッチングによ
り、前記開口部部分でフォトレジストを後退させながら
フォトレジストをマスクとして前記絶縁膜をエッチング
し、テーパー状のホールを絶縁膜に形成する。According to the present invention, a photoresist is formed on an insulating film, an opening for hole etching is formed in the photoresist, and then the photoresist is irradiated with ultraviolet light and heat-treated. As a result, the photoresist is deformed so that the stepped portion in the opening has a gentle shape, and then the insulating film is etched by using the photoresist as a mask while retreating the photoresist in the opening by dry etching. Then, a tapered hole is formed in the insulating film.
【０００８】[0008]
【作用】ホールエッチング用開口部を形成したフォトレ
ジストに紫外光を照射すると、フォトレジストの硬化が
起ると同時に変形が起る。さらに紫外光照射と同時にフ
ォトレジストを加熱すると、熱だれによりフォトレジス
トが変形する。これら２つの処理の相乗効果により、開
口部部分の段差部がなだらかな形状のフォトレジストを
得ることができる。そして、このようなフォトレジスト
をマスクにドライエッチングを行うと、開口部部分でフ
ォトレジストが後退しながらエッチングが進行するた
め、絶縁膜にテーパー状にホールが形成される。When the photoresist on which the hole etching opening is formed is irradiated with ultraviolet light, the photoresist is hardened and deformed at the same time. Further, if the photoresist is heated at the same time as the ultraviolet light irradiation, the photoresist is deformed due to the heat drop. Due to the synergistic effect of these two processes, it is possible to obtain a photoresist in which the step portion of the opening portion has a gentle shape. When dry etching is performed using such a photoresist as a mask, the photoresist advances in the opening while the etching proceeds, so that a tapered hole is formed in the insulating film.
【０００９】[0009]
【実施例】以下この発明の一実施例を図１および図２を
参照して説明する。図１（ａ）において、２１はメタル
層、２２はその上の１．５〜２μｍ厚の酸化シリコン系
層間絶縁膜であり、まずこの層間絶縁膜２２上にフォト
レジスト２３（例えば東京応化社製ＴＳＭＲ８９００）
を例えば１．４μｍ厚に形成する。次に通常のフォトリ
ソグラフィー工程によってフォトレジスト２３に図１
（ｂ）に示すようにホールエッチング用の開口部２４を
形成する。その後、上記構造体を図示しないステージ上
に乗せて、ステージ温度（換言すれば上記構造体の温度
であり、フォトレジスト２３の温度である）を毎秒１℃
強で約２分間、約１５０°前後になるまで上昇させ続
け、同時にその間の、図１（ｃ）に示すようにフォトレ
ジスト２３に紫外光ランプ（６００mW／cm2)で紫外光を
照射し続ける。すると、フォトレジスト２３は変形し、
開口部２４部分の段差部は図２（ａ）に示すようになだ
らかな形状となる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1A, 21 is a metal layer, 22 is a silicon oxide type interlayer insulating film having a thickness of 1.5 to 2 μm, and a photoresist 23 (for example, manufactured by Tokyo Ohka Co., Ltd.) is first formed on the interlayer insulating film 22. (TSMR8900)
Is formed to have a thickness of 1.4 μm, for example. Next, as shown in FIG.
As shown in (b), an opening 24 for hole etching is formed. Then, the structure is placed on a stage (not shown), and the stage temperature (in other words, the temperature of the structure and the temperature of the photoresist 23) is 1 ° C. per second.
For about 2 minutes, keep increasing the temperature until it reaches about 150 °, and at the same time, continue to irradiate the photoresist 23 with ultraviolet light with an ultraviolet lamp (600 mW / cm 2 ) as shown in FIG. 1 (c). .. Then, the photoresist 23 is deformed,
The stepped portion at the opening 24 has a gentle shape as shown in FIG.
【００１０】しかる後は、フォトレジスト２３をマスク
として、例えぱ平行平板型の放電方式のプラズマ処理装
置を用いて、圧力＝1.７Torr，ガスＡｒ／ＣＨＦ3 ／Ｃ
Ｆ4 ＝８００／６０／６０（ＳＣＣＭ），高周波電力＝
７５０Ｗのプラズマ生成条件下で層間絶縁膜２２のドラ
イエッチングを図２（ｂ）に示すように行う。すると、
この時、開口部部分の段差部がなだらかな形状である上
記フォトレジスト２３によれば、開口部部分のフォトレ
ジストが後退しながら、該フォトレジストをマスクとし
て層間絶縁膜２２のエッチングが行われるようになり、
その結果図２（ｂ）に示すように層間絶縁膜２２にはテ
ーパー状にホール２５が開孔されることになる。しか
も、以上の方法によれば寸法および形状の制御性よくテ
ーパー状にホール２５が開孔されることになる。その
後、図２（ｃ）に示すようにフォトレジスト２３を除去
し、ホール開孔工程を終了する。Thereafter, using the photoresist 23 as a mask, a parallel plate type discharge type plasma processing apparatus is used, for example, pressure = 1.7 Torr, gas Ar / CHF 3 / C.
F 4 = 800/60/60 (SCCM), high frequency power =
Dry etching of the interlayer insulating film 22 is performed as shown in FIG. 2B under the plasma generation condition of 750 W. Then,
At this time, according to the photoresist 23 in which the stepped portion in the opening portion has a gentle shape, the interlayer insulating film 22 is etched using the photoresist as a mask while the photoresist in the opening portion recedes. become,
As a result, as shown in FIG. 2B, the holes 25 are formed in the interlayer insulating film 22 in a tapered shape. Moreover, according to the above method, the hole 25 is opened in a tapered shape with good controllability of the size and shape. Then, as shown in FIG. 2C, the photoresist 23 is removed, and the hole opening step is completed.
【００１１】[0011]
【発明の効果】以上詳細に説明したように、この発明に
よれば、フォトレジストの開孔部部分の段差部を紫外光
照射と加熱処理でなだらかな形状に変形させ、その部分
の後退を利用してドライエッチングで絶縁膜にテーパー
状にホールを開孔するようにしたので、形状および寸法
の制御性よくテーパー状にホールを開孔することがで
き、かつウエットエッチング法に比較して製造工程を簡
略化できる。したがって、半導体集積回路装置の製造歩
留り，信頼性，スループットなどの向上が期待できる。As described in detail above, according to the present invention, the stepped portion of the opening portion of the photoresist is deformed into a gentle shape by the ultraviolet light irradiation and the heat treatment, and the retreat of the portion is used. Since the holes are taper-shaped in the insulating film by dry etching, the holes can be taper-shaped with good control of the shape and dimensions. Can be simplified. Therefore, improvement in manufacturing yield, reliability, throughput, etc. of the semiconductor integrated circuit device can be expected.
【図１】この発明の一実施例の一部を示す工程断面図で
ある。FIG. 1 is a process sectional view showing a part of an embodiment of the present invention.
【図２】この発明の一実施例の一部を示す工程断面図で
ある。FIG. 2 is a process sectional view showing a part of an embodiment of the present invention.
【図３】従来の第１の方法を示す工程断面図である。FIG. 3 is a process cross-sectional view showing a first conventional method.
【図４】従来の第２の方法を示す工程断面図である。FIG. 4 is a process sectional view showing a second conventional method.
【図５】従来の第２の方法におけるフロー温度特性図で
ある。FIG. 5 is a flow temperature characteristic diagram in the second conventional method.
【図６】従来の第２の方法における問題点を示す断面図
である。FIG. 6 is a cross-sectional view showing a problem in the second conventional method.
２２ 層間絶縁膜 ２３ フォトレジスト ２４ 開口部 ２５ ホール 22 Interlayer Insulating Film 23 Photoresist 24 Opening 25 Hole
Claims (1)
のフォトレジストにホールエッチング用の開口部を形成
した後、フォトレジストに対する紫外光の照射と加熱処
理を行うことにより、前記開口部部分の段差部がなだら
かな形状となるようにフォトレジストを変形させ、その
後ドライエッチングにより、前記開口部部分でフォトレ
ジストを後退させながらフォトレジストをマスクとして
前記絶縁膜をエッチングし、テーパー状のホールを絶縁
膜に形成するようにした半導体装置の製造方法。1. A photoresist is formed on an insulating film, an opening for hole etching is formed in the photoresist, and then ultraviolet light is irradiated to the photoresist and a heat treatment is performed to expose the opening. The photoresist is deformed so that the step becomes a gentle shape, and then the insulating film is etched by using the photoresist as a mask while retreating the photoresist at the opening by dry etching to insulate the tapered hole. A method for manufacturing a semiconductor device, which is formed on a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28188391A JPH05102106A (en) | 1991-10-03 | 1991-10-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28188391A JPH05102106A (en) | 1991-10-03 | 1991-10-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05102106A true JPH05102106A (en) | 1993-04-23 |
Family
ID=17645300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28188391A Pending JPH05102106A (en) | 1991-10-03 | 1991-10-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05102106A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005036244A1 (en) * | 2003-10-09 | 2005-04-21 | Fujitsu Limited | Module for reflection liquid crystal display and its manufacturing method, and reflection liquid crystal display |
| WO2008066059A1 (en) * | 2006-11-30 | 2008-06-05 | Kabushiki Kaisha Toshiba | Semiconductor device and semiconductor device manufacturing method |
-
1991
- 1991-10-03 JP JP28188391A patent/JPH05102106A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005036244A1 (en) * | 2003-10-09 | 2005-04-21 | Fujitsu Limited | Module for reflection liquid crystal display and its manufacturing method, and reflection liquid crystal display |
| WO2008066059A1 (en) * | 2006-11-30 | 2008-06-05 | Kabushiki Kaisha Toshiba | Semiconductor device and semiconductor device manufacturing method |
| US7749901B2 (en) | 2006-11-30 | 2010-07-06 | Kabushiki Kaisha Toshiba | Method for forming a tapered via of a semiconductor device |
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