JPH04288818A - Semiconductor manufacturing apparatus and manufacture of semiconductor device - Google Patents
Semiconductor manufacturing apparatus and manufacture of semiconductor deviceInfo
- Publication number
- JPH04288818A JPH04288818A JP3052781A JP5278191A JPH04288818A JP H04288818 A JPH04288818 A JP H04288818A JP 3052781 A JP3052781 A JP 3052781A JP 5278191 A JP5278191 A JP 5278191A JP H04288818 A JPH04288818 A JP H04288818A
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- JP
- Japan
- Prior art keywords
- film
- voltages
- phase
- chamber
- phase difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H10W72/01515—
-
- H10W72/075—
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- H10W72/5363—
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- H10W90/754—
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- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
【0001】(目次) ・産業上の利用分野 ・従来の技術(図7) ・発明が解決しようとする課題 ・課題を解決するための手段 ・作用 ・実施例 (1)第1の実施例(図1,図5) (2)第2の実施例(図2〜図4,図6)・発明の効果[0001] (Table of Contents) ・Industrial application field ・Conventional technology (Figure 7) ・Problem that the invention aims to solve ・Means to solve problems ・Effect ·Example (1) First embodiment (Fig. 1, Fig. 5) (2) Second embodiment (Figures 2 to 4, and 6) - Effects of the invention
【0002】0002
【産業上の利用分野】本発明は、半導体製造装置及び半
導体装置の製造方法に関し、更に詳しく言えば、対向電
極の間の被成膜体に膜形成する半導体製造装置及び半導
体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing apparatus and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor manufacturing apparatus and a method of manufacturing a semiconductor device in which a film is formed on a film-forming object between opposing electrodes. .
【0003】近年、電子デバイス及び新素材を用いた新
素子の開発等において、無機材料からなる保護膜,アモ
ルファス膜,又は磁性体膜を三次元的に形成する膜形成
装置が開発され、製造に用いられるようになっている。
この膜形成装置により形成された膜はステップカバレー
ジに優れ、また被成膜体に与えるダメージも小さい。In recent years, in the development of electronic devices and new elements using new materials, film forming apparatuses for three-dimensionally forming protective films, amorphous films, or magnetic films made of inorganic materials have been developed, and manufacturing has improved. It is now being used. The film formed by this film forming apparatus has excellent step coverage and causes little damage to the object on which the film is formed.
【0004】このような膜形成装置として対向電極型の
プラズマCVD装置やスパッタ装置がある。[0004] As such a film forming apparatus, there are a facing electrode type plasma CVD apparatus and a sputtering apparatus.
【0005】[0005]
【従来の技術】図7(a)は、従来例の対向電極型プラ
ズマCVD装置の構成図である。2. Description of the Related Art FIG. 7(a) is a block diagram of a conventional opposed electrode type plasma CVD apparatus.
【0006】図7(a)において、1は膜形成するため
に内部が減圧されるチャンバ、2a,2bはチャンバ内
に設置された、反応ガスをプラズマ化するため交流電圧
/電流の印加される対向電極、3は被成膜体を載置する
導電性の保持具で、対向電極2a,2bからの交流電圧
/電流が保持具3によりその広がりが妨げられないよう
に対向電極2a,2bの板面に対して各載置面が垂直に
並べられている。4a,4bはそれぞれ対向電極2a,
2bと接続され、交流電圧/電流を供給する交流電源、
5は対向電極2a,2bに印加される交流電圧/電流の
互いの位相関係を制御するフェーズシフタで、図7(b
)に示すように、対向電極2a,2b間の全体にプラズ
マが広がるような位相関係が実験的に調査され、互いの
位相シフトが約75度になるように設定されている。In FIG. 7(a), 1 is a chamber whose interior is depressurized for film formation, and 2a and 2b are installed in the chamber to which alternating current voltage/current is applied to convert the reaction gas into plasma. The counter electrode 3 is a conductive holder on which the object to be film-formed is placed, and the counter electrodes 2a, 2b are arranged so that the AC voltage/current from the counter electrodes 2a, 2b is not prevented from spreading by the holder 3. Each mounting surface is arranged perpendicularly to the plate surface. 4a and 4b are the counter electrodes 2a and 4b, respectively.
an AC power supply connected to 2b and supplying an AC voltage/current;
5 is a phase shifter that controls the mutual phase relationship of AC voltage/current applied to the opposing electrodes 2a and 2b, as shown in FIG. 7(b).
), a phase relationship in which plasma spreads throughout the opposing electrodes 2a and 2b has been experimentally investigated, and the mutual phase shift is set to approximately 75 degrees.
【0007】次に、このような対向電極型プラズマCV
D装置を用いて、組立て完了後、裸のチップや内部リー
ドの表面に絶縁性の保護膜を形成する方法について図3
(a),(b)を参照しながら説明する。Next, such a counter electrode type plasma CV
Figure 3 shows how to use D equipment to form an insulating protective film on the surface of bare chips and internal leads after assembly is complete.
This will be explained with reference to (a) and (b).
【0008】図3(a)は、組立て完了後、保護膜の形
成前の状態を示す、被成膜体10としての半導体装置の
断面図で、組立て基台6上にSi基板7が固着され、か
つこのSi基板7と外部リードの内部ポスト8a,8b
とを接続して内部リード9a,9bが形成されている。FIG. 3(a) is a cross-sectional view of a semiconductor device as a film-forming object 10, showing a state after assembly is completed and before the formation of a protective film, in which a Si substrate 7 is fixed on an assembly base 6. , and this Si substrate 7 and the internal posts 8a and 8b of the external leads.
Internal leads 9a and 9b are formed by connecting these.
【0009】このような状態で、まず、図7に示す、対
向電極型プラズマCVD装置の保持具3の載置面に被成
膜体10を載置した後、チャンバ1内部を減圧する。In this state, first, the object 10 to be film-formed is placed on the mounting surface of the holder 3 of the opposed electrode type plasma CVD apparatus shown in FIG. 7, and then the pressure inside the chamber 1 is reduced.
【0010】次に、交流電圧/電流を対向電極2a,2
bに印加して所定時間保持すると、図3(b)に示すよ
うに、裸のSi基板7や内部リード9a,9bの表面に
絶縁性の保護膜11が形成される。Next, the AC voltage/current is applied to the opposing electrodes 2a, 2.
b is applied and maintained for a predetermined time, an insulating protective film 11 is formed on the surface of the bare Si substrate 7 and the internal leads 9a, 9b, as shown in FIG. 3(b).
【0011】[0011]
【発明が解決しようとする課題】ところで、上記のよう
なプラズマCVD装置であっても、同時に成膜する被成
膜体10が多い場合、膜厚分布のバラツキが大きくなり
、また再現性にも乏しくなってきた。なお、表1及び図
6にそれぞれ膜厚分布のバラツキ及び再現性についての
調査結果を示す。[Problems to be Solved by the Invention] However, even with the plasma CVD apparatus described above, when there are many objects 10 to be film-formed at the same time, the variation in film thickness distribution becomes large, and the reproducibility also deteriorates. It's getting scarce. Note that Table 1 and FIG. 6 show the investigation results regarding the variation in film thickness distribution and reproducibility, respectively.
【0012】このため、更に膜厚を薄く、かつ精度良く
形成する場合等に問題となる。[0012] This poses a problem when forming the film even thinner and with higher precision.
【0013】本発明は、かかる従来の問題点に鑑みてな
されたもので、形成膜の膜厚分布の均一性及び再現性を
向上することができる半導体製造装置及び半導体装置の
製造方法を提供することを目的とするものである。The present invention has been made in view of such conventional problems, and provides a semiconductor manufacturing apparatus and a semiconductor device manufacturing method that can improve the uniformity and reproducibility of the film thickness distribution of a formed film. The purpose is to
【0014】[0014]
【課題を解決するための手段】上記課題は、第1に、減
圧可能なチャンバと、該チャンバへの反応ガスの導入口
と、前記チャンバ内の排気口と、前記チャンバ内の対向
電極と、該対向電極間に設けられた、被成膜体を載置す
る保持具と、前記対向電極にそれぞれ接続された交流電
源と、該交流電源により供給され、前記対向電極に印加
される交流電圧の互いの位相関係を調整する位相制御手
段とを有する半導体製造装置において、前記各対向電極
の直流電圧を検出・比較し、この結果に基づいて前記位
相制御手段に位相制御信号を出力する直流検出/制御信
号出力手段を有することを特徴とする半導体製造装置に
よって達成され、第2に、対向電極の間に被成膜体を置
いた後、前記各対向電極に印加される交流電圧の位相差
を小さい方から大きい方へ、又は大きい方から小さい方
へ調整していき、各対向電極の直流電圧がほぼ等しくな
ったところで、被成膜体上に第1の膜形成を行う工程と
、前記位相差を更に大きい方に又は小さい方に調整して
、各対向電極の直流電圧が再びほぼ等しくなったところ
で、前記第1の膜形成により形成された膜の上に第2の
膜形成を行う工程とを有する半導体装置の製造方法によ
って達成される。[Means for Solving the Problems] The above-mentioned problems firstly include a chamber capable of reducing pressure, an inlet for introducing a reaction gas into the chamber, an exhaust port in the chamber, a counter electrode in the chamber, A holder provided between the opposing electrodes for placing the object to be film-formed, an AC power source connected to each of the opposing electrodes, and an AC voltage supplied by the AC power source and applied to the opposing electrode. In a semiconductor manufacturing apparatus having a phase control means for adjusting mutual phase relationship, a DC detection device detects and compares DC voltages of the respective opposing electrodes, and outputs a phase control signal to the phase control means based on the result. This is achieved by a semiconductor manufacturing apparatus characterized by having a control signal output means, and secondly, after placing a film-forming object between opposing electrodes, the phase difference between the alternating current voltages applied to each of the opposing electrodes is determined. The step of forming a first film on the object to be film-formed when the DC voltages of the opposing electrodes are approximately equal by adjusting from the smaller to the larger or from the larger to the smaller; A step of forming a second film on the film formed by the first film formation when the DC voltages of the opposing electrodes are approximately equal again by adjusting the phase difference to be larger or smaller. This is achieved by a method of manufacturing a semiconductor device having the following.
【0015】[0015]
【作用】本願発明者は、プラズマCVD装置において、
形成される膜厚の分布の均一性と各対向電極の直流電圧
との間に下記のような関係があることを実験により見い
だした。[Operation] In the plasma CVD apparatus, the inventor of the present application has
It has been experimentally found that the following relationship exists between the uniformity of the thickness distribution of the formed film and the DC voltage of each opposing electrode.
【0016】即ち、通常、交流電圧の印加されている対
向電極にはプラズマ中のイオンや電子の分布により異な
る負の値を有する直流電圧が生じる。しかも、この直流
電圧値は交流電圧の位相差により変動する。That is, normally, a DC voltage having a different negative value is generated at the opposite electrode to which an AC voltage is applied depending on the distribution of ions and electrons in the plasma. Moreover, this DC voltage value varies depending on the phase difference of the AC voltage.
【0017】いま、イオンや電子の分布状態が膜厚の分
布を左右していると推定されるので、直流電圧と膜厚の
分布との相関について調査した。表1は、実験の条件に
ついて表したものである。[0017] Since it is presumed that the distribution of ions and electrons influences the distribution of film thickness, the correlation between DC voltage and the distribution of film thickness was investigated. Table 1 shows the experimental conditions.
【0018】[0018]
【表1】[Table 1]
【0019】この条件により、実験を行い、図4(a)
〜(c)に示すような結果が得られた。被成膜体として
ウエハ20a〜20cを用い、このウエハ上に目標とす
る膜厚5000ÅのSi3N4 膜21a〜21cを形
成した。[0019] Under these conditions, an experiment was conducted, and the result was shown in Fig. 4(a).
The results shown in ~(c) were obtained. Wafers 20a to 20c were used as objects to be film-formed, and Si3N4 films 21a to 21c having a target thickness of 5000 Å were formed on these wafers.
【0020】その結果、次のようなことが判明した。As a result, the following was found.
【0021】(1)直流電圧が等しい場合、膜厚の分布
は均一にはならないが、対向電極の間の中央部に対して
対称になる。(1) When the DC voltages are equal, the film thickness distribution will not be uniform, but will be symmetrical with respect to the center between the opposing electrodes.
【0022】(2)また、直流電圧が等しくなるような
位相差は2点(実験の場合、約75度と約255 度)
あり、図4(a),(b)に示すように、それぞれ相補
うような膜厚分布になる。即ち、位相差が小さい方では
中央部が薄くなり、周辺部で厚くなる。一方、位相差が
大きい方では中央部が厚くなり、周辺部で薄くなる。(2) Furthermore, there are two phase differences that make the DC voltages equal (in the case of experiments, about 75 degrees and about 255 degrees).
As shown in FIGS. 4(a) and 4(b), the film thickness distributions are complementary to each other. That is, in the case where the phase difference is smaller, the center part becomes thinner and the peripheral part becomes thicker. On the other hand, in the case where the phase difference is large, the center part becomes thicker and the peripheral part becomes thinner.
【0023】上記の調査結果に基づいて、位相差約75
度で10分/位相差約255 度で10分連続して膜形
成した(図4(c))。その結果、表1に示すように、
膜厚分布のバラツキは目標膜厚5000Åに対して−1
1〜+8%と、従来の場合−28〜+39%と比較して
大幅に改善された。また、図6は、表1の条件と同じ条
件で再現性の調査を行った結果を示しており、図6によ
れば、従来の場合と比較して再現性も改善された。Based on the above research results, the phase difference is approximately 75
The film was formed continuously for 10 minutes at a temperature of 255 degrees/10 minutes at a phase difference of about 255 degrees (FIG. 4(c)). As a result, as shown in Table 1,
The variation in film thickness distribution is -1 for the target film thickness of 5000 Å.
1 to +8%, which is a significant improvement compared to -28 to +39% in the conventional case. Moreover, FIG. 6 shows the results of a reproducibility investigation conducted under the same conditions as those in Table 1, and according to FIG. 6, the reproducibility was also improved compared to the conventional case.
【0024】ところで、本発明の半導体製造装置によれ
ば、各対向電極に印加される交流電圧の直流成分を検出
・比較し、この結果に基づいて位相制御手段に位相制御
信号を出力する直流検出/制御信号出力手段を有してい
るので、上記のように直流電圧がほぼ等しくなるように
位相差を調整できる。これにより、直流電圧が等しくな
るような各位相差でそれぞれ第1及び第2の膜を連続し
て形成することができるので、各位相差での膜厚のバラ
ツキを相補うようにして膜形成でき、最終的に膜厚分布
の均一性の良い膜を再現性良く得ることができる。By the way, according to the semiconductor manufacturing apparatus of the present invention, the DC detection detects and compares the DC component of the AC voltage applied to each counter electrode, and outputs a phase control signal to the phase control means based on the result. / Since the control signal output means is provided, the phase difference can be adjusted so that the DC voltages are approximately equal as described above. As a result, the first and second films can be formed continuously at each phase difference such that the DC voltage is equal, so that the film can be formed so as to compensate for variations in film thickness at each phase difference. Finally, a film with good uniformity of film thickness distribution can be obtained with good reproducibility.
【0025】また、本発明の半導体装置の製造方法によ
れば、直流電圧が等しくなるような各位相差でそれぞれ
第1及び第2の膜を連続して形成しているので、それぞ
れの位相差での膜厚のバラツキを相補うようにして膜形
成できる。これにより、最終的に膜厚分布の均一性の良
い膜を再現性良く得ることができる。Further, according to the method of manufacturing a semiconductor device of the present invention, since the first and second films are successively formed with respective phase differences such that the DC voltages are equal, The film can be formed so as to compensate for the variation in film thickness. As a result, it is possible to finally obtain a film with good uniformity of film thickness distribution with good reproducibility.
【0026】[0026]
【実施例】(1)第1の実施例
図1は、本発明の第1の実施例の対向電極型プラズマC
VD装置について説明する構成図である。[Example] (1) First Example FIG. 1 shows a counter-electrode type plasma C of the first example of the present invention.
FIG. 2 is a configuration diagram illustrating a VD device.
【0027】図1において、12は膜形成するために内
部が減圧されるチャンバ、13a,13bはチャンバ1
2内に設置された、反応ガスをプラズマ化するため交流
電圧/電流の印加される対向電極、14は被成膜体を載
置する導電性の保持具で、対向電極13a,13bから
の交流電圧/電流が保持具14の被成膜体の載置面によ
りその広がりが妨げられないように対向電極13a,1
3bの板面に対して垂直に並べられている。15a,1
5bはそれぞれ対向電極13a,13bと接続され、交
流電圧/電流を供給する交流電源、16は各対向電極1
3a,13bが有する直流電圧を検出し、この直流電圧
を比較して制御信号を出力する直流検出/制御信号出力
手段で、通常、印加される交流電圧/電流により対向電
極13a,13b間に発生するプラズマの分布により各
対向電極13a,13bで異なる値を持つ。また、17
は直流検出/制御信号出力手段16からの直流電圧に基
づいて互いの位相関係を制御するフェーズシフタ(位相
制御手段)で、各対向電極13a,13bに印加される
交流電圧の位相差を例えば小さい方から大きい方へ調整
していき、各対向電極13a,13bの直流電圧がほぼ
等しくなったところで、各交流電圧の位相を固定して所
定時間保持する。実験によれば、各交流電圧の位相差が
約75度、及び約225度のときに各対向電極13a,
13bの直流電圧がほぼ等しくなる。In FIG. 1, 12 is a chamber whose interior is depressurized for film formation, and 13a and 13b are chambers 1
A counter electrode 2 is installed in which AC voltage/current is applied to convert the reaction gas into plasma, and 14 is a conductive holder on which the object to be filmed is placed. The opposing electrodes 13a and 1 are arranged so that the voltage/current is not prevented from spreading by the mounting surface of the film-forming object of the holder 14.
They are arranged perpendicularly to the plate surface of 3b. 15a,1
5b is connected to the counter electrodes 13a and 13b, respectively, and is an AC power source that supplies an AC voltage/current; 16 is each counter electrode 1;
A DC detection/control signal output means that detects the DC voltage possessed by the DC voltages 3a and 13b, compares the DC voltages, and outputs a control signal.Usually, the voltage generated between the opposing electrodes 13a and 13b due to the applied AC voltage/current is Each counter electrode 13a, 13b has a different value depending on the plasma distribution. Also, 17
is a phase shifter (phase control means) that controls the mutual phase relationship based on the DC voltage from the DC detection/control signal output means 16, and reduces the phase difference between the AC voltages applied to each opposing electrode 13a and 13b, for example. When the DC voltages of the opposing electrodes 13a and 13b become approximately equal, the phase of each AC voltage is fixed and held for a predetermined time. According to experiments, when the phase difference between the AC voltages is about 75 degrees and about 225 degrees, the opposing electrodes 13a,
The DC voltages of 13b become approximately equal.
【0028】18は反応ガスの導入口、19は反応に用
いたガスを排出する排気口である。Reference numeral 18 represents an inlet for the reaction gas, and 19 represents an exhaust port for discharging the gas used in the reaction.
【0029】以上のように、本発明の第1の実施例の対
向電極型のプラズマCVD装置によれば、各対向電極1
3a,13bの直流電圧を検出・比較し、この結果に基
づいてフェーズシフタ17に位相制御信号を出力する直
流検出/制御信号出力手段16を有しているので、上記
のように直流電圧がほぼ等しくなるように位相差を調整
できる。これにより、直流電圧が等しくなるような各位
相差でそれぞれ連続して膜形成することができるので、
各位相差での膜厚のバラツキを相補うようにして膜形成
でき、最終的に膜厚分布の均一性の良い膜を再現性良く
得ることができる。As described above, according to the opposed electrode type plasma CVD apparatus of the first embodiment of the present invention, each of the opposed electrodes 1
3a and 13b, and outputs a phase control signal to the phase shifter 17 based on this result. The phase difference can be adjusted so that they are equal. This allows continuous film formation at each phase difference such that the DC voltage is equal.
A film can be formed so as to compensate for variations in film thickness due to each phase difference, and finally a film with good uniformity of film thickness distribution can be obtained with good reproducibility.
【0030】(2)第2の実施例
次に、このような対向電極型プラズマCVD装置を用い
て、組立て完了後、裸のチップや内部リードの表面にS
i3N4 膜からなる保護膜を形成する方法について図
1,図2(a),(b),図3(a),(b)を参照し
ながら説明する。(2) Second Embodiment Next, using such a facing electrode type plasma CVD apparatus, after the assembly is completed, S is applied to the surface of the bare chip and internal leads.
A method for forming a protective film made of an i3N4 film will be described with reference to FIGS. 1, 2(a) and 2(b), and 3(a) and 3(b).
【0031】図3(a)は、組立て完了後、Si3N4
膜の形成前の状態を示す、被成膜体26としての半導
体装置の断面図で、組立て基台22上にSi基板23が
固着され、かつこのSi基板23と外部リードの内部ポ
スト24a,24bとを接続して内部リード25a,2
5bが形成されている。FIG. 3(a) shows the Si3N4
This is a cross-sectional view of a semiconductor device as a film-forming object 26, showing a state before film formation, in which a Si substrate 23 is fixed on an assembly base 22, and the Si substrate 23 and internal posts 24a, 24b of external leads are connected to each other. and internal leads 25a, 2.
5b is formed.
【0032】このような状態で、まず、図1に示す対向
電極型プラズマCVD装置の保持具14に被成膜体26
を載置した後、チャンバ12内部を減圧する。In this state, first, the object 26 to be film-formed is placed on the holder 14 of the opposed electrode type plasma CVD apparatus shown in FIG.
After placing the chamber 12, the pressure inside the chamber 12 is reduced.
【0033】次に、図2(a)に制御系の概略を示すよ
うに、フェーズシフタ17の制御信号により各対向電極
13a,13bに印加される交流電圧の位相差を小さい
方から大きい方へ調整していく。直流検出/制御信号出
力手段16で各対向電極13a,13bの直流電圧を監
視し、各対向電極13a,13bの直流電圧がほぼ等し
くなったところで、この状態を約10分間保持し、目標
とする膜厚の約半分の膜厚のSi3N4 膜の膜形成を
行う。このとき、位相差はほぼ75度になっており、形
成された膜の膜厚分布は中央部が周辺部よりも薄くなっ
ている(図4(a))。Next, as shown in the outline of the control system in FIG. 2(a), the phase difference between the AC voltages applied to each of the opposing electrodes 13a and 13b is changed from the smaller to the larger by the control signal of the phase shifter 17. We will make adjustments. The DC voltage of each opposing electrode 13a, 13b is monitored by the DC detection/control signal output means 16, and when the DC voltage of each opposing electrode 13a, 13b becomes almost equal, this state is maintained for about 10 minutes and the target is set. A Si3N4 film having a thickness of about half of the film thickness is formed. At this time, the phase difference is approximately 75 degrees, and the film thickness distribution of the formed film is thinner at the center than at the periphery (FIG. 4(a)).
【0034】次に、位相差を更に大きい方に調整して、
各対向電極の直流電圧が再びほぼ等しくなったところで
、この状態を約10分間保持し、残りの膜厚のSi3N
4 膜の膜形成を行う。このとき、位相差はほぼ225
度になっており、実験により確認されているように中央
部が周辺部よりも厚く形成される(図4(b))。これ
により、個々の位相差で形成されるSi3N4 膜の膜
厚は不均一であるが、最終的には丁度相補いあって均一
な膜厚のSi3N4 膜27が形成される(図4(c)
)。Next, the phase difference is adjusted to a larger value,
When the DC voltages of each counter electrode became almost equal again, this state was maintained for about 10 minutes, and the remaining film thickness was
4 Perform film formation of the film. At this time, the phase difference is approximately 225
As confirmed by experiments, the central part is thicker than the peripheral part (FIG. 4(b)). As a result, although the thickness of the Si3N4 film formed by each individual phase difference is non-uniform, in the end they complement each other exactly and the Si3N4 film 27 with a uniform thickness is formed (Fig. 4(c)).
).
【0035】上記の調査結果によれば、表1に示すよう
に、膜厚分布のバラツキは目標膜厚5000Åに対して
−11〜+8%と、従来の場合−28〜+39%と比較
して大幅に改善された。また、図6は、表1の条件と同
じ条件で再現性の調査を行った結果を示しており、図6
によれば、従来の場合と比較して再現性も改善された。According to the above investigation results, as shown in Table 1, the variation in film thickness distribution is -11 to +8% for a target film thickness of 5000 Å, compared to -28 to +39% in the conventional case. Significantly improved. In addition, Figure 6 shows the results of a reproducibility study conducted under the same conditions as those in Table 1.
According to the authors, reproducibility was also improved compared to the conventional case.
【0036】以上のように、本発明の第2の実施例の半
導体装置の製造方法によれば、直流電圧が等しくなるよ
うな各位相差でそれぞれ連続して膜形成しているので、
それぞれの位相差での膜厚のバラツキを相補うようにし
て膜形成できる。これにより、最終的に膜厚分布の均一
性の良い膜を再現性良く得ることができる。As described above, according to the method for manufacturing a semiconductor device according to the second embodiment of the present invention, films are formed successively at each phase difference such that the DC voltages are equal.
The film can be formed so as to compensate for variations in film thickness due to each phase difference. As a result, it is possible to finally obtain a film with good uniformity of film thickness distribution with good reproducibility.
【0037】なお、上記第2の実施例では、交流電圧の
位相差を小さい方から大きい方へ調整しているが、逆に
大きい方から小さい方へ調整することもできる。In the second embodiment, the phase difference of the AC voltage is adjusted from the smaller to the larger, but it can also be adjusted from the larger to the smaller.
【0038】[0038]
【発明の効果】以上のように、本発明の半導体製造装置
によれば、各対向電極の直流電圧を検出・比較し、この
結果に基づいて位相制御手段に位相制御信号を出力する
直流検出/制御信号出力手段を有しているので、上記の
ように直流電圧がほぼ等しくなるように位相差を調整で
きる。これにより、直流電圧が等しくなるような各位相
差でそれぞれ第1及び第2の膜を連続して形成すること
ができるので、各位相差での膜厚分布のバラツキを相補
うようにして膜形成でき、最終的に膜厚分布の均一性の
良い膜を再現性良く得ることができる。As described above, the semiconductor manufacturing apparatus of the present invention detects and compares the DC voltage of each opposing electrode, and outputs a phase control signal to the phase control means based on the result. Since the control signal output means is provided, the phase difference can be adjusted so that the DC voltages are approximately equal as described above. This allows the first and second films to be formed successively at each phase difference such that the DC voltage is equal, so that the film can be formed in such a way as to compensate for variations in film thickness distribution at each phase difference. Finally, a film with good uniformity of film thickness distribution can be obtained with good reproducibility.
【0039】また、本発明の半導体装置の製造方法によ
れば、直流電圧が等しくなるような各位相差でそれぞれ
連続して膜形成しているので、それぞれの位相差での膜
厚のバラツキを相補うようにして膜形成できる。これに
より、最終的に膜厚分布の均一性の良い膜を再現性良く
得ることができる。Furthermore, according to the method of manufacturing a semiconductor device of the present invention, since films are formed successively at each phase difference such that the DC voltage is equal, variations in film thickness at each phase difference are compensated for. A film can be formed in a complementary manner. As a result, it is possible to finally obtain a film with good uniformity of film thickness distribution with good reproducibility.
【図1】本発明の第1の実施例の対向電極型のプラズマ
CVD装置について説明する構成図である。FIG. 1 is a configuration diagram illustrating a counter electrode type plasma CVD apparatus according to a first embodiment of the present invention.
【図2】本発明の第2の実施例の半導体装置の製造方法
に適用する対向電極型のプラズマCVD装置への交流電
圧印加方法について説明する図である。FIG. 2 is a diagram illustrating a method of applying an alternating current voltage to a facing electrode type plasma CVD apparatus applied to a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
【図3】本発明の第2の実施例の半導体装置の製造方法
について説明する断面図である。FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
【図4】本発明の半導体製造装置及び半導体装置の製造
方法の作用について説明する断面図である。FIG. 4 is a cross-sectional view illustrating the operation of the semiconductor manufacturing apparatus and the semiconductor device manufacturing method of the present invention.
【図5】本発明の第1の実施例のプラズマCVD装置の
対向電極に印加される交流電圧と、各対向電極の直流電
圧について説明する図である。FIG. 5 is a diagram illustrating an AC voltage applied to a counter electrode of the plasma CVD apparatus according to the first embodiment of the present invention and a DC voltage of each counter electrode.
【図6】本発明の実施例の半導体装置の製造方法による
膜形成の再現性について比較説明する図である。FIG. 6 is a diagram for comparing and explaining the reproducibility of film formation by the method of manufacturing a semiconductor device according to an embodiment of the present invention.
【図7】従来例の対向電極型のプラズマCVD装置につ
いて説明する図である。FIG. 7 is a diagram illustrating a conventional opposed electrode type plasma CVD apparatus.
1,12 チャンバ、
2a,2b,13a,13b 対向電極、3,14
保持具、
4a,4b,15a,15b 交流電源、5 フェ
ーズシフタ、
6,22 組立て基台、
7,23 チップ、
8a,8b,24a,24b 内部ポスト、9a,9
b,25a,25b 内部リード、10,26 被
成膜体、
11,27 保護膜、
16 直流検出/制御信号出力手段、17 フェー
ズシフタ(位相制御手段)、18 ガス導入口、
19 排気口、
20a〜20c ウエハ、
21a〜21c Si3N4 膜。1, 12 chamber, 2a, 2b, 13a, 13b counter electrode, 3, 14
Holder, 4a, 4b, 15a, 15b AC power supply, 5 Phase shifter, 6, 22 Assembly base, 7, 23 Chip, 8a, 8b, 24a, 24b Internal post, 9a, 9
b, 25a, 25b internal lead, 10, 26 film-forming object, 11, 27 protective film, 16 DC detection/control signal output means, 17 phase shifter (phase control means), 18 gas inlet, 19 exhaust port, 20a ~20c wafer, 21a~21c Si3N4 film.
Claims (2)
の反応ガスの導入口と、前記チャンバ内の排気口と、前
記チャンバ内の対向電極と、該対向電極間に置かれた、
被成膜体を載置する保持具と、前記対向電極にそれぞれ
接続された交流電源と、該交流電源により供給され、前
記対向電極に印加される交流電圧の互いの位相関係を調
整する位相制御手段とを有する半導体製造装置において
、前記各対向電極の直流電圧を検出・比較し、この結果
に基づいて前記位相制御手段に位相制御信号を出力する
直流検出/制御信号出力手段を有することを特徴とする
半導体製造装置。1. A chamber capable of reducing pressure, an inlet for introducing a reaction gas into the chamber, an exhaust port in the chamber, a counter electrode in the chamber, and a chamber disposed between the counter electrodes.
A holder for placing the object to be film-formed, an AC power supply connected to the counter electrode, and a phase control for adjusting the mutual phase relationship of the AC voltage supplied by the AC power supply and applied to the counter electrode. The semiconductor manufacturing apparatus has a DC detection/control signal output means for detecting and comparing DC voltages of each of the opposing electrodes and outputting a phase control signal to the phase control means based on the results. Semiconductor manufacturing equipment.
前記各対向電極に印加される交流電圧の位相差を小さい
方から大きい方へ、又は大きい方から小さい方へ調整し
ていき、各対向電極の直流電圧がほぼ等しくなったとこ
ろで、被成膜体上に第1の膜形成を行う工程と、前記位
相差を更に大きい方に又は小さい方に調整して、各対向
電極の直流電圧が再びほぼ等しくなったところで、前記
第1の膜形成により形成された膜の上に第2の膜形成を
行う工程とを有する半導体装置の製造方法。Claim 2: After placing a film-forming object between opposing electrodes,
The phase difference of the AC voltages applied to each of the opposing electrodes is adjusted from the smaller to the larger, or from the larger to the smaller, and when the DC voltages of the opposing electrodes become approximately equal, the film-forming object is a step of forming a first film on the top; and adjusting the phase difference to be larger or smaller, and when the DC voltages of the opposing electrodes become approximately equal again, forming the first film. a step of forming a second film on the formed film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3052781A JPH04288818A (en) | 1991-03-18 | 1991-03-18 | Semiconductor manufacturing apparatus and manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3052781A JPH04288818A (en) | 1991-03-18 | 1991-03-18 | Semiconductor manufacturing apparatus and manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04288818A true JPH04288818A (en) | 1992-10-13 |
Family
ID=12924391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3052781A Withdrawn JPH04288818A (en) | 1991-03-18 | 1991-03-18 | Semiconductor manufacturing apparatus and manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04288818A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0780731A2 (en) | 1995-12-22 | 1997-06-25 | Mitsubishi Chemical Corporation | Photopolymerizable composition for a color filter, color filter and liquid crystal display device |
| JP2002261031A (en) * | 2001-03-06 | 2002-09-13 | Kanegafuchi Chem Ind Co Ltd | Method for forming semiconductor layer and method for manufacturing photoelectric conversion device |
| JP2005329353A (en) * | 2004-05-21 | 2005-12-02 | Fuiisa Kk | Plasma processing method and apparatus |
| WO2007123183A1 (en) | 2006-04-19 | 2007-11-01 | Mitsubishi Chemical Corporation | Color image display device |
| EP2078978A2 (en) | 2004-04-26 | 2009-07-15 | Mitsubishi Chemical Corporation | LCD backlight containing a LED with adapted light emission and suitable colour filters |
| WO2009099211A1 (en) | 2008-02-07 | 2009-08-13 | Mitsubishi Chemical Corporation | Semiconductor light emitting device, backlighting device, color image display device and phosphor used for those devices |
| WO2019096891A1 (en) | 2017-11-15 | 2019-05-23 | Byk-Chemie Gmbh | Block co-polymer |
| WO2019096893A1 (en) | 2017-11-15 | 2019-05-23 | Byk-Chemie Gmbh | Block co-polymer |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0780731A2 (en) | 1995-12-22 | 1997-06-25 | Mitsubishi Chemical Corporation | Photopolymerizable composition for a color filter, color filter and liquid crystal display device |
| JP2002261031A (en) * | 2001-03-06 | 2002-09-13 | Kanegafuchi Chem Ind Co Ltd | Method for forming semiconductor layer and method for manufacturing photoelectric conversion device |
| EP2078978A2 (en) | 2004-04-26 | 2009-07-15 | Mitsubishi Chemical Corporation | LCD backlight containing a LED with adapted light emission and suitable colour filters |
| JP2005329353A (en) * | 2004-05-21 | 2005-12-02 | Fuiisa Kk | Plasma processing method and apparatus |
| WO2007123183A1 (en) | 2006-04-19 | 2007-11-01 | Mitsubishi Chemical Corporation | Color image display device |
| WO2009099211A1 (en) | 2008-02-07 | 2009-08-13 | Mitsubishi Chemical Corporation | Semiconductor light emitting device, backlighting device, color image display device and phosphor used for those devices |
| EP3045965A1 (en) | 2008-02-07 | 2016-07-20 | Mitsubishi Chemical Corporation | Red emitting fluoride phosphor activated by mn4+ |
| WO2019096891A1 (en) | 2017-11-15 | 2019-05-23 | Byk-Chemie Gmbh | Block co-polymer |
| WO2019096893A1 (en) | 2017-11-15 | 2019-05-23 | Byk-Chemie Gmbh | Block co-polymer |
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