JPH042114A - Lithography process verification methods - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for verifying a lithography process. More particularly, the present invention relates to a novel method for validating lithography processes in determining manufacturing processes for semiconductor devices and the like.

BACKGROUND OF THE INVENTION In integrated circuit manufacturing technology using lithography technology, more precise control of the wafer process is required as devices become more multifunctional and highly integrated.

When optimizing a wafer process, software considerations are used, such as simulating the wafer process on a computer; ＼-Dware considerations still have important significance.

Conventional methods for verifying lithography processes using test patterns include using an optical microscope;
It can be roughly divided into methods using an electron microscope. FIGS. 5(a) and 5(a) are diagrams showing typical test pattern shapes conventionally used for such verifications as well as various verification methods.

That is, when verifying the resolution of the lithography process using an optical microscope, as shown in FIG. 5(a),
After a test pattern consisting of lines 20a and spaces 20b is actually formed on the wafer 10 using the resist layer 20, the pattern is observed using an optical microscope from above the wafer 10.

In addition, in the method using an electron microscope, the wafer 1
After actually forming a test pattern consisting of lines 20a and spaces 20b on the resist layer 20,
As shown in FIG. 5(b), this is a method in which the wafer 10 is fractured at right angles to the line pattern 20a in the region where the pattern is formed, and the vicinity of the formed fracture surface is observed using an electron microscope. .

By these methods, it is possible to verify the fine shape of the resist pattern actually formed on the wafer 10 by a specific lithography process.

Problems to be Solved by the Invention However, when patterns are miniaturized to 1 μm or less as in recent years, sufficient resolution cannot be obtained using an optical microscope.

On the other hand, when using an electron microscope, sufficient verification is possible in terms of resolution, but the wafer must be broken each time verification is performed. Therefore, not only the number of work steps for verification increases, but also the consumption of wafers increases.

In addition, in a test pattern consisting of parallel grooves and a space formed between them, interference occurs between adjacent line patterns, making it difficult to individually evaluate the effect of each pattern in the lithography process. There is.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for evaluating a lithography process using a novel test pattern, which solves the above-mentioned problems of the prior art and allows verification of minute shapes of resist patterns without destroying the wafer. The purpose is

According to the present invention, a resist layer coated on a semiconductor wafer is patterned into a predetermined test pattern by lithography, and then the resist pattern is formed by observing the formed resist pattern with a microscope. In the method of verifying the lithography process when
A resist pattern consisting of lines or spaces formed on the wafer includes a test pattern forming an end face perpendicular to the longitudinal direction of the pattern, and the end face is observed without destroying the wafer. Accordingly, a method for verifying a lithography process is provided, which is characterized by evaluating a lithography process when forming the resist pattern.

The main feature of the lithography process verification method according to the present invention is that by employing a unique test pattern, it is possible to evaluate the minute shape of a resist pattern using an electron microscope without destroying the wafer. be.

In other words, in the conventional method, the lithography process was verified using a test pattern consisting of continuous lines or spaces, so in order to observe the formed resist pattern with an electron microscope, it was necessary to break the wafer. I needed to. Furthermore, in conventional test patterns, lines and spaces are arranged close to each other, so it is not possible to avoid mutual interference effects between lines or spaces.

On the other hand, the test pattern used in the method according to the present invention has a shape in which a resist pattern consisting of lines or spaces forms an end face perpendicular to the longitudinal direction of the pattern. Therefore, a pseudo cross section has already been formed when the resist pattern is formed, and this pseudo cross section and its vicinity can be observed using an electron microscope from diagonally above (at an elevation angle of about 60° from the wafer surface) without destroying the wafer. be able to.

Further, according to a preferred embodiment of the present invention, the resist pattern forming the pseudo cross section is formed apart from other patterns, so that the influence of mutual interference with other patterns can be eliminated.

Hereinafter, the present invention will be described in more detail with reference to the drawings, but the following disclosure is only one embodiment of the present invention, and the following disclosure does not limit the technical scope of the present invention in any way.

Example 1 FIGS. 1(a) and 1(a) are diagrams showing a test pattern used when implementing the method according to the present invention and the shape of a resist pattern formed by this test pattern.

That is, FIG. 1(a) shows the test pattern used in this example as a mask pattern for positive resist. It is composed of a line pattern 2 that terminates in the center of a rectangular space area 1.

Using such a test pattern, Figure 1(b)
As shown in FIG. 2, a short line pattern 2 is formed that protrudes into a space 1 with no other patterns around it and has a pseudo cross section 2a approximately in the center of the space 1. Therefore, this pseudo cross section 2a can be observed obliquely from above using an electron microscope.

Similar to the test pattern shown in FIG. 1(a), FIGS. 2(a) and 2(a) show other examples of test patterns that can be advantageously used when verifying line-shaped resist patterns. FIG. 4 is a diagram showing the same using a mask pattern for a positive resist.

The test pattern shown in FIG. 2(a) is provided with a pair of independent line patterns 2 from a pair of sides facing each other in a rectangular space area 1 with no other adjacent patterns. .

The test pattern shown in FIG. 2(b) also includes four independent line patterns 2 from each side toward the center in a rectangular space area 1 with no other adjacent patterns. ing.

By using a test pattern having such a shape, pseudo end faces in mutually different directions are formed in the resist pattern to be verified, which facilitates electron microscope observation after forming the resist pattern.

Example 2 FIGS. 3(a) and 3(a) are diagrams showing other test patterns that can be used in the method of the present invention and the shapes of resist patterns formed by the test patterns.

That is, FIG. 1(a) shows the test pattern used in this example as a mask pattern for negative resist, and as shown in the same figure, this test pattern is used as a mask pattern for other adjacent spaces. It is constituted by a space pattern 4 that terminates in the center of a rectangular space area 3.

When such a test pattern is used, a space pattern 4 having a pseudo cross section 4a is formed inside a space 3 with no other lines around it, as shown in FIG. 3b). Therefore, this pseudo cross section 4a can be observed obliquely from above using an electron microscope.

Similar to the test pattern shown in FIG. 3(a), FIGS. 4(a) and 4(a) are other examples of test patterns that can be advantageously used when verifying space-like resist patterns. FIG.

The test pattern shown in FIG. 4(a) is provided with a pair of space patterns 4 each having an end on a pair of sides facing each other in a rectangular space area 3 with no other adjacent spaces. There is.

In addition, the test pattern shown in FIG. 4(b) is a rectangular space area 3 with no other spaces in the vicinity, and four space patterns 4 each having an end on each side.
It is equipped with

By using a test pattern having such a shape, pseudo end faces in mutually different directions are formed in the resist pattern to be verified, which facilitates electron microscope observation after forming the resist pattern.

As described in detail, according to the lithography process verification method according to the present invention, it is possible to observe a resist pattern using an electron microscope without breaking the wafer on which the test pattern is formed.

Therefore, it is possible to shorten the time required for verification work, and since verification can be performed without destroying the wafer, consumption of wafers is reduced, which ultimately reduces the manufacturing cost of devices that involve lithography processes. I can do it.

[Brief explanation of drawings]

FIGS. 1(a) and 1(a) are diagrams showing a test pattern that can be used when implementing the method according to the present invention and the shape of a resist pattern formed using the test pattern. Figures 2(a) and 2) are diagrams showing examples of other test patterns that can perform the same verification as the test pattern shown in Figure 1(a), and Figures 3(a) and 3) are FIG. 4(a) and FIG. 4(Q)) are diagrams showing other test patterns that can be used when carrying out the method according to the present invention and the shapes of resist patterns formed using the test patterns; teeth,
5A and 5B are diagrams showing examples of other test patterns that can perform the same verification as the test pattern shown in FIG. 3A; FIGS. This is a diagram for [Main reference numbers] 1... Space region, 2... Line pattern, 3... Space region, 4... Space pattern, 2a, 4a... Pseudo end face 10... Wafer 20a...・Line, 20b... Space Figure 1 Figure 3 Figure 2 (a) (b) a Figure 4 (a) (b) 1,..., Space 2,... Line

Claims (1)

[Claims] A method in which a resist layer coated on a semiconductor wafer is patterned into a predetermined test pattern by lithography, and then the lithography process used to form the pattern is verified by observing the formed resist pattern under a microscope. A resist pattern formed of lines or spaces includes a test pattern forming an end face perpendicular to the longitudinal direction of the pattern, and the end face of the resist pattern is observed without destroying the wafer. A method for verifying a lithography process, the method comprising: evaluating a lithography process when forming the resist pattern.