JPH04207226A - Input/output circuit - Google Patents

Abstract

PURPOSE:To perform the quick operation even in a CMOS input/output circuit by constituting a circuit which prescribes the logical level of a transmission signal by the current mode and attains impedance matching to the transmission line. CONSTITUTION:The output circuit of a first IC constitute a current push/pull circuit and switches output current pulling-in and pulling-out functions in accordance with the logical value of the logical signal of a logic circuit 11. The signal transmitted through a transmission line 7 is transmitted to the input circuit of a second IC. In the input circuit of the second IC, the common source electrode of an N-channel transistor TR 8 and a P-channel TR 9 receives the signal from the transmission line 7 as the input terminal of the second IC. Gate potentials are given to gate electrodes of TRs 8 and 9 from voltage sources 6b and 6c respectively, and drain electrodes 5 and 4 transmits the logical signal to the second IC as output terminals of the input circuit of the second IC.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to an input/output circuit that transmits signals between ICs via a transmission path.

(Prior Art) In recent years, as systems have become larger and faster, demands on LSIs that make up these systems have become increasingly strict. Specifically, these include high-speed operation, low power consumption, and high-density integration. At present, no process has been found that satisfies all of these requirements.
SI is desired.

If we consider the CMOS process here, it fully satisfies the two requirements of low power consumption and high density integration, and with the current miniaturization of CMOS, the operating speed inside the IC is also increasing. . However, when constructing a large-scale system, the operating speed of the entire system is limited by the signal transmission speed between ICs.

For signal transmission between ICs, the ECL circuit is superior to the CMO3 output circuit in terms of high-speed signal transmission. Therefore, when high speed is required, EC is usually used.
Configure the system by performing input/output according to L logic.

In particular, using the B1CMOS process that forms five CMO elements and a bipolar element on the same chip, the logic section is made into CMO.
According to the method of configuring the system with S transistors and the input/output section with bipolar transistors, the logic section can be configured with CMOS and the input/output circuit with ECL, making it possible to configure a system that operates at high speed. becomes.

However, when compared in the development phase, the B1 CMOS process has problems such as a manufacturing process that is more complex than an individual CMOS process, resulting in poor yields and an inability to obtain a high degree of integration of the manufactured devices.

(Problem to be solved by the invention) In the conventional CMO5IC, when applied to a large-scale, high-speed system, high speed inside the circuit was achieved to some extent, but due to the operating speed of the CMO 3 output circuit, the overall system The operating speed was limited.

An object of the present invention is to provide an input/output circuit that performs high-speed signal transmission using a CMOS process.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, in an input/output circuit in which an output circuit of a first IC is connected to an input circuit of a second IC via a transmission path. , a first Ic output circuit that outputs a logic signal with a logic value as a current change, a P channel transistor and an N channel transistor are connected in series, and the source electrodes of the P channel transistor and the N channel transistor are commonly connected. each drain electrode is connected to a first reference potential and a second reference potential, and each gate electrode is connected to an input circuit connected to a first voltage source or a second voltage source, and the P-channel transistor. A transmission line connected between a common source terminal with an N-channel transistor and an output circuit of the first IC is provided. (Function) The output circuit of the first IC includes a circuit that outputs a logic signal of a logic circuit as a current change.

This produces a current mode logic signal. The current output from this output circuit is transmitted to the input circuit of the second IC via the transmission path. The input circuit of the second IC has, as an input terminal, a drain electrode of a P-channel transistor and an N-channel transistor connected in common, and transmits a signal current due to a difference in the logical value of the transmission signal to the second IC.

According to the present invention, it is possible to define the logic level of a transmission signal using the current mode, and at the same time configure a circuit that can achieve impedance matching with the transmission line, so that high-speed operation can be performed even in a CMO5 input/output circuit. Furthermore, it is resistant to variations in characteristics of constituent elements depending on the manufacturing process, and lower power consumption can be achieved compared to ECL input/output circuits. Furthermore, since it is easy to perform matching termination with low impedance for a wide range of input currents, the configuration allows easy matching with the transmission line regardless of the level of the input signal. This allows CMO to perform high-speed signal transmission between ICs via the transmission line.
Realizes an S input/output circuit.

(Example) The following is a configuration diagram illustrating an example of the present invention using a configuration diagram. The output circuit of the first IC constitutes a current push-pull circuit, and the function of drawing in and drawing out the output current is switched according to the logical value of the logic signal of the logic circuit 11. The signal transmitted via the transmission line 7 is transmitted to the input circuit of the second IC. In the input circuit of the second IC, the common source electrodes of the N-channel transistor 8 and the P-channel transistor 9 are connected to the transmission line 7 as an input terminal of the input circuit of the second IC, and each gate electrode has a gate potential. It is connected to the voltage source 6b or 6C. The drain electrode 5 of the N-channel transistor 8 and the drain electrode 4 of the P-channel transistor 9 transmit a logic signal to the second IC as output terminals of the input circuit of the second IC.

Next, the operation of the circuit shown in FIG. 1a will be explained. The current and current sources 1 and 2 are the logic value rHJ of the logic signal of the logic circuit 15.
rLJ is selected corresponding to the output terminal lO of the first IC.
It is assumed that a current corresponding to the logic signal is outputted to the transmission line 7 from. This current is transmitted to the input terminal of the second IC via the transmission path 7, and is transmitted to the common source electrode of the N-channel transistor 8 and the P-channel transistor 9 in response to the logic signal. As a result, a current corresponding to one of the logic signals is sent to the input terminal of the input circuit of the second IC via the transmission line 7 and flows to the output terminal 4 via the transistor 9. A current corresponding to the other logic signal (also drawn through the transmission line 7 and flowing from the output terminal 5 of the second IC to the transistor 8 is received).

With such a configuration, the CMOS input/output circuit performs current mode signal transmission and at the same time impedance matching with the transmission path is performed, so that high-speed signal input/output can be achieved. Further, the input impedance seen from the common source electrode in the second IC circuit is a parallel resistance of the impedance seen from the north electrodes of transistors 8 and 9, and the structure is such that impedance matching with the transmission line is achieved. As a result, the output impedance is approximately constant over a wide range of input current values, so that changes in the input impedance of the circuit with respect to the input current can be reduced, and good matching of the characteristic impedance with the transmission line can be achieved. This situation is shown in FIG. -Also the transmission line and the input signal of the second IC.

- Even in the case where the impedance is not matched with the impedance, the reduction in operating speed due to capacitive load can be suppressed.

Even if the input current from current source 1 or 2 changes greatly, the common source electrode potential of transistor 8.9 hardly changes. The DC potential of the output terminal of the first IC] 0 becomes the common source potential of the transistors 8.9 of the input circuit of the second IC.

FIG. 2 shows a configuration diagram of another embodiment of the present invention.

(ゝ The main parts of the configuration are similar to the circuit shown in FIG. 1a. .

However, a matching resistor 12 is connected to the output terminal 10 for impedance matching between the transmission line and the first output circuit.

In this circuit configuration, the high output impedance of current sources 1 and 2 is improved, and the reflection of the transmission signal in the first output circuit is reduced by setting the matching resistor 12 to a value that matches the transmission line. This enables faster signal transmission.

FIG. 3 shows a specific example of the configuration of the matching resistor 12. It consists of a series circuit of a resistor R and a capacitor C, and satisfies the following relationship.

CR> 1/2 yr f c where fc is the frequency of the signal to be transmitted.

Next, an example of a circuit for realizing the present invention will be shown.

52J-- FIG. 4 is a circuit diagram showing a configuration example corresponding to the output circuit of the first IC shown in FIG. 1a.

The connection relationship of each element is as follows. Input terminals 18 and 19 receive differential signals from the logic circuit.

The input terminals 18 and 19 are connected to the gate terminals of transistors 14 and 15, respectively, and the source electrodes of these transistors 14 and 15 are connected to the drain electrode of transistor 13. Transistor 13 provides current, and transistors 14 and 15 constitute a so-called differential pair transistor. The drain electrode of the transistor 14 is commonly connected to the drain and gate electrodes of the transistor 23, and the source electrode of the transistor 23 is connected to the reference potential 100. The drain electrode of the transistor 15 is commonly connected to the drain and gate electrodes of the transistor 24, and the source electrode of the transistor 24 is connected to the reference potential 10.
Connected to 0.

Transistor 23, transistor 6, transistor 11
and transistor 12, transistor 24, and transistor 32 respectively constitute a so-called current mirror circuit,
The respective drain electrodes of the transistor 12 and the transistor 32 are commonly connected to form an output terminal 17.

Similarly, the transistors 24 and 20, the transistors 21 and 22, and the transistors 23 and 31 each form a current mirror circuit, and the drain electrodes of the transistors 22 and 31 are commonly connected to form the output terminal 16.

Next, the operation of this circuit will be explained. Consider a case where the logic signal of the logic circuit is "L" at the input terminal 18 and the input terminal 19rHJ is input. At this time, no current flows through the transistor 15, and only the current supplied from the transistor 13 flows through the transistor 14. This current or transistor #3,3
1 becomes the drain current of the transistor 31 through a current mirror circuit composed of 1. Since no current is flowing through the transistor 22, the output terminal 16 operates in the direction of drawing current from the transmission path. Conversely, it operates in the direction of pushing out the current by one degree from the output terminal 17 via the transiller circuit. When the logic signal of the logic circuit is "H" to the input terminal 18 and input terminal 19rLJ is input, current is pushed from the output terminal 16 to the transmission path by the operation principle opposite to the above, and from the output terminal 17 is pushed to the transmission path. It operates in the direction of drawing current from the transmission path.

FIG. 5 is a circuit diagram realizing the input circuit of the second IC shown in the eleventh layer. Transistor 51 and transistor 5
2. Transistor 53 and transistor 54 constitute a current mirror circuit, and the drain electrode of transistor 54 is connected to the drain electrode of transistor 58. The gate electrode of transistor 5B is commonly connected to the drain electrode, and is also connected to the gate electrode of transistor 59. The source electrode of transistor 58 is connected to transistor 56
The drain electrode of transistor 56 is connected to reference potential 110. The gate electrode of transistor 56 is connected in common to the gate electrode of transistor 57, and is connected to voltage source 130. The drain electrode of transistor 57 is connected to reference potential 110, and the source electrode is connected to the source electrode of transistor 59. The source common connection electrodes of transistors 57 and 59 are connected to an input terminal 70 of the circuit. transistor 5
The drain terminal of transistor 9 is connected to the drain terminal of transistor 60 and also to the gate terminal of transistor 60, and the source electrode of transistor 60 is connected to reference potential 1.
20. Transistor 51 and transistor 5
5. The transistor 60 and the transistor 61 each constitute a current mirror circuit, and the drain terminals of the transistor 55 and the transistor 61 are commonly connected and connected to the output terminal 71 of the circuit.

The operation of this circuit will be explained. When there is no input to the input terminal 70, equal currents flow due to the potential applied to the common gate electrode 130 of the transistors 56 and 57, and these currents act in the direction of flowing to the transistors 58 and 59, respectively, so that the circuit maintains balance.

As a result, ideally, currents of equal value would flow through the drain electrode of the transistor 55 and the drain electrode of the transistor 61 constituting the output terminal 71 of the circuit, so that the output terminal 71 becomes undefined. However, when a current is drawn from the input terminal 70, the balance between the transistors 57 and 59 is lost, and the drain current of the transistor 57 increases and the drain current of the transistor 59 decreases. As a result, the drain current of the transistor 61 also decreases, so the output potential rHJ at the output terminal 71
becomes. Conversely, when current is passed through the input terminal 70,
The operation is opposite to the above explanation, and the drain current of the transistor 6e increases, so the output potential rL of the output terminal 71
It becomes J.

In particular, when transmitting signals at high speed with this circuit, the channel lengths of the transistors 56, 57, 58, and 59,
The current value of the current source 80 may be set according to the width ratio so that matching with the transmission path can be achieved.

FIG. 6 is an embodiment of a circuit diagram for realizing an input circuit of a second IC different from that shown in FIG. 5, and is a circuit in which the input stage of the circuit shown in FIG. 5 is performed by differential input. be.

According to this circuit, the input circuit of the second IC can be configured even when the input signal is a logic signal or a differential signal from the transmission line. The operating principle is similar to the circuit shown in FIG. 5. For example, when a current is drawn from the input terminal 170 and a signal is input to the input terminal 171 in the direction in which the current is drawn, the drain current of the transistor 96 decreases. , conversely, the drain current of transistor 91 increases. At this time, the drain current of transistor 98 decreases, and
The drain current of transistor 95 will increase through the current mirror circuit formed by transistors 2,93 or 94,95. As a result, the output terminal 172 becomes the output potential rHJ. Especially in this case,
Transistor 90 and transistor 91, transistor 9
2 and the transistor 93, and the transistor 94 and the transistor 95 respectively constitute a current mirror circuit,
The current gain doubles.

FIG. 7 is a circuit diagram constructed by adding an additional circuit to the circuit shown in FIG. 5. The operating principle is similar to the circuit shown in FIG. 5, and provides a potential at the output terminal in response to changes in the current input from the transmission line. This configuration doubles the current gain compared to the circuit shown in FIG.

FIG. 8 is a circuit diagram constructed by adding an additional circuit to the circuit of FIG. 6. This also allows an input circuit to be configured, and the current gain is doubled compared to the circuit shown in FIG.

In the embodiments described above, CMO is used in the circuit configuration.
3, but the circuit can also be configured using bipolar elements.

In addition, the input/output circuit using CMO5 explained this time is ECL
EC, which is currently widely used in high-speed systems, can be applied as a circuit that transmits logic.
It is also possible to maintain compatibility with the L circuit.

[Effects of the Invention] As described above, according to the present invention, the logic value is defined by the current using the output circuit equipped with the circuit that provides the logic value of the logic signal as an output current change, so that the CMOS
Signal transmission can also be performed at high speed in the output circuit. In addition, the input circuit allows you to configure an input circuit with impedance matching for a wide range of transmission currents.
It is easy to match with the transmission line, and the circuit can operate at high speed. This makes it possible to implement a CMOS input/output circuit even in systems that require high speed.

[Brief explanation of the drawing]

FIG. 1 I is a diagram for proving one embodiment of the input/output circuit of the present invention, FIG. 2 is a diagram showing another embodiment of the input/output circuit of the present invention, and FIG. 3 is a diagram shown in FIG. 4 is a diagram showing an embodiment of the output circuit of the present invention, FIG. 5 is a diagram showing an embodiment of the single-phase input circuit of the present invention, and FIG. 6 is a diagram showing the differences in the present invention. FIG. 7 is a diagram showing another embodiment of the single-phase input circuit of the present invention, and FIG. 8 is a diagram showing another embodiment of the differential input circuit used in the present invention. It is a diagram. 1.2.80...Current source, 1B, 19,70,170
, 171...input terminal, 4.5, 10.16.17.
71.172...Output terminal, 8.9, 13, 14, 1
5.20.21, 22, 23, 24, 31, 32.51
~61.90~98...MOS transistor, 7...
Transmission line, 6b, 6c, 3B, 100, 110°120
．． 130...voltage source, 11. F...Logic circuit, 12
...matching resistance.

Claims (3)

[Claims] (1) In an input/output circuit in which the output circuit of the first IC is connected to the input circuit of the second IC via a transmission line, the output of the first IC outputs a logic signal of a logic value as a current change. a circuit, a P-channel transistor and an N-channel transistor are connected in series, respective source electrodes of the P-channel transistor and the N-channel transistor are commonly connected, and each drain electrode is connected to a first reference potential and a second reference potential; an input circuit connected to a first voltage source or a second voltage source, a common source terminal of the P-channel transistor and the N-channel transistor, and an output circuit of the first IC. An input/output circuit comprising a transmission path connected between the input and output circuits. (2) An input/output circuit matching the output terminal of the output circuit of the first IC. (3) The input circuit of the second IC connects the drain electrodes of the P-channel transistor and the N-channel transistor to the current-voltage conversion circuit between the first reference potential and the second reference potential. 2. The input/output circuit according to claim 1, wherein the input/output circuit is an input circuit characterized in that: