JP7761295B1 - Capacitive sensor array chip and sampling device with programmable pixel resolution adjustment, and control system therefor - Google Patents

Abstract

The present invention provides a capacitance sensor array chip and sampling device that programmably adjust pixel resolution, and a control system thereof.
[Solution] The device comprises a programmable module for generating a selection signal based on a first clock signal, a delay pulse module for generating a third clock signal based on a second clock signal and a sensing pulse signal, a charging unit for generating a charging signal based on the sensing pulse signal, and a plurality of electrode array modules including M x N electrode pixel units forming an array and a sampling unit, wherein the electrode array module is used to sequentially select the electrode pixel units of a specific pattern based on the selection signal, and the electrode pixel units of the specific pattern in the electrode array module are used to generate a sampling signal based on the charging signal, and the sampling unit is used to generate a sensing output signal based on the sampling signal and the third clock signal.
[Selected Figure] Figure 1

Description

Article 30, Paragraph 2 of the Patent Act applies. <Disclosure Fact 1> (1) Publication date: May 22, 2023 (2) Publication: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, VOL. 70, NO. 5, pp. 1734-1738, MAY 2023 (3) Discloser: National Yangming Jiao Tong University (4) Disclosure: Lai Linhong, Lin Wenyu, Lu Yi, Liu Hengyu, Yoshida Shinsuke, Qiu Shihua, and Li Zhenyi have disclosed in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, VOL. 70, NO. 5, MAY 2023, "Capacitive Sensor Array Chip and Sampling Device with Programmable Pixel Resolution Adjustment, and Control System Thereof," invented by Lai Linhong, Lin Wenyu, and Li Zhenyi.

The present invention relates to a capacitive sensor array chip, and more particularly to a capacitive sensor array chip that allows programmable pixel resolution adjustment.

CMOS laboratory chips offer unprecedented applications in life sciences, such as rapid medical testing using digital microfluidics, cell sorting using traveling wave dielectrophoresis, and polymerase chain reaction using heated microelectrode arrays (H-MEA), achieving lower costs, faster operation, smaller reagent volumes, and higher throughput than traditional methods. Capacitive sensor arrays (CSAs) play a crucial role in collecting the electrical and physical responses of biological targets and providing the correct operational strategies.

However, due to the size mismatch between a single electrode and a single cell, it is difficult to detect the behavior of a single cell. Monitoring cell proliferation in real time by converting capacitance into frequency using a ring oscillator (RO) is sufficient for identifying the adhesion of cell clusters, but the spatial resolution for observing the behavior of a single cell still has room for improvement.

Therefore, there is an urgent need for a sensing method that can balance spatial resolution and sensitivity by dynamically using corresponding electrode sizes depending on the sample size.

The object of the present invention is to provide a capacitive sensor array chip, sampling device, and control system that programmably adjusts pixel resolution to solve the various problems of the prior art described above.

To achieve the above object, a first aspect of the present invention provides a capacitive sensor array chip that includes a programmable module, a delay pulse module, and multiple electrode array modules, and that programmably adjusts pixel resolution.

The programmable module is used to generate a selection signal based on a first clock signal. The delay pulse module is used to generate a third clock signal based on a second clock signal and a sensing pulse signal. The plurality of electrode array modules include a charging unit for generating a charging signal based on the sensing pulse signal, M x N electrode pixel units (M is a positive integer greater than or equal to 1, and N is a positive integer greater than or equal to 1) forming an array, and a sampling unit for generating a sensing output signal based on the sampling signal and the third clock signal. The electrode array module is used to sequentially select the electrode pixel units of a specific pattern based on the selection signal, and the electrode pixel units of the specific pattern in the electrode array module are used to generate a sampling signal based on the charging signal.

In one embodiment of the present invention, the electrode pixel unit includes an electrode, a first transistor having a drain connected to the electrode, and a switching logic gate having an input terminal that receives the selection signal and an output terminal that is connected to the gate of the first transistor.

In one embodiment of the present invention, the selection signal includes an M-bit row signal and an N-bit column signal.

In one embodiment of the present invention, the charging unit includes a first voltage source, at least one first PMOS connected to the first voltage source, and a first CMOS inverter connected to the at least one first PMOS. The input terminal of the first CMOS inverter receives the sensing pulse signal, and the output terminal of the first CMOS inverter outputs the charging signal.

In one embodiment of the present invention, the charging unit includes a second voltage source, a second CMOS inverter connected to the second voltage source, at least one second PMOS connected to the second CMOS inverter, and a third multiplexer connected to the at least one second PMOS. The first input terminal of the third multiplexer is connected to a control voltage, and when the third multiplexer selects the first input terminal, it controls the output current of the at least one second PMOS via the control voltage. The input terminal of the second CMOS inverter receives the sensing pulse signal, and the output terminal of the second CMOS inverter outputs the charging signal.

In one embodiment of the present invention, the delay pulse module includes a first DFF, a delay time generator (DPDG) connected to the output terminal of the first DFF, and a first multiplexer. The clock input terminal of the first DFF receives the sensing pulse signal, the first input terminal of the first multiplexer is connected to the output terminal of the delay time generator, the second input terminal of the first multiplexer receives a second clock signal, and the output terminal of the first multiplexer outputs the third clock signal.

In one embodiment of the present invention, the sampling unit comprises a first INV, a second multiplexer, and a second DFF. The input terminal of the first INV receives the sampling signal, and the first input terminal of the second multiplexer is connected to the output terminal of the first INV. The clock input terminal of the second DFF receives the third clock signal, and the input terminal of the second DFF is connected to the output terminal of the second multiplexer. The output terminal of the second DFF outputs the sensing output signal and is connected to the second input terminal of the second multiplexer of the sampling unit of the next electrode array module to form a serial output.

In one embodiment of the present invention, the first INV is a Hi-Skew inverter.

In one embodiment of the present invention, the electrodes of the electrode pixel units are arranged in a square, staggered, or aligned pattern, and the electrode pixel units may or may not include a guard ring.

In one embodiment of the present invention, the electrode pixel unit is made of the metal material of the top layer or the metal material of the next layer.

A second aspect of the present invention provides a sampling device, the sampling device comprising:
The present invention comprises a capacitive sensor array chip for programmably adjusting pixel resolution according to the first aspect of the present invention, a protective layer covering the capacitive sensor array chip for programmably adjusting pixel resolution, a container for accommodating the capacitive sensor array chip for programmably adjusting pixel resolution, and an insulator arranged to surround the capacitive sensor array chip for programmably adjusting pixel resolution and for firmly connecting the container and the capacitive sensor array chip for programmably adjusting pixel resolution.

A third aspect of the present invention provides a control system for controlling a capacitance sensor array chip with programmable pixel resolution adjustment to sense a sample. The control system includes the capacitance sensor array chip with programmable pixel resolution adjustment described in the first aspect of the present invention, and a control unit for determining resistance and capacitance values during sampling and controlling the electrode pixel units.

In one embodiment of the present invention, the control unit includes a shift register for determining resistance and capacitance values at the time of sampling to establish equivalent electrode sizes.

In one embodiment of the present invention, the shift register is an (M+N)-bit shift register.

In one embodiment of the present invention, the control system further includes a programmable board connected to the capacitive sensor array chip that programmably adjusts pixel resolution and the control unit, for arranging signals from the control unit and transmitting information generated by the capacitive sensor array chip that programmably adjusts pixel resolution to an external processor.

In one embodiment of the present invention, the control system further comprises an optical imaging device for recording the sample to generate the optical pattern.

In one embodiment of the present invention, the optical pattern is used to verify the correlation of the capacitance pattern obtained after the control system collects the sample.

In one embodiment of the present invention, the control system is used to capture a first noise, which is a fixed pattern noise on the capacitive sensor array chip, to programmably adjust the pixel resolution.

In one embodiment of the present invention, the control system is used to continuously collect the samples to obtain multiple frames.

In one embodiment of the present invention, the programmable board is used to average the multiple frames to remove second noise and obtain the appearance characteristics of the sample, where the second noise is random noise.

In one embodiment of the present invention, the programmable board further removes the first noise in the sample's appearance characteristics to obtain a pure sample value of the sample.

The capacitance sensor array chip, sampling device, and control system with programmable pixel resolution provided by the present invention combine an interface, readout circuit, and sampling circuit within the pixel, allowing the electrode size to be dynamically adjusted according to the characteristics of the biological sample being tested, not only improving sensing performance but also optimizing sampling sensitivity through predetermined fusion pixel modes.

1 is a functional block diagram of a capacitive sensor array chip with programmable pixel resolution adjustment according to a first embodiment of the present invention; FIG. FIG. 10 is a schematic circuit diagram of an electrode array module according to a second embodiment of the present invention. FIG. 10 is a schematic circuit diagram of a delay pulse module according to a third embodiment of the present invention. 10 is a timing chart according to a fourth embodiment of the present invention. FIG. 10 is a schematic circuit diagram of a charging unit according to a fifth embodiment of the present invention. 10A and 10B are a schematic view and a schematic cross-sectional view of a sampling device according to a sixth embodiment of the present invention. 10A and 10B are a schematic view and a schematic cross-sectional view of a sampling device according to a sixth embodiment of the present invention. FIG. 10 is a schematic diagram of a control system according to a seventh embodiment of the present invention. 13A-13C show capacitance values measured by taking different samples in different fused pixel modes using a control system according to an eighth embodiment of the present invention; FIG. 13 is a diagram showing the results of real-time monitoring of a sample using a control system according to a ninth embodiment of the present invention.

The following describes the implementation of the present invention through specific embodiments. Those skilled in the art will readily understand other advantages and effects of the present invention from the contents disclosed herein. The present invention may also be implemented or applied through other different specific embodiments, and various details of the present specification may be variously refined and modified based on different perspectives and applications without departing from the spirit of the present invention.

[First embodiment]
1, which is a functional block diagram of a capacitive sensor array chip with programmable pixel resolution adjustment according to a first embodiment of the present invention. As shown in the figure, the capacitive sensor array chip with programmable pixel resolution adjustment according to the present invention includes a programmable module 10, a delay pulse module 11, and electrode array modules 12a and 12b. In the embodiment of FIG. 1, two electrode array modules 12a and 12b are used as an example, but this is not limiting, and more electrode array modules may be used in other embodiments.

The programmable module 10 is used to generate a selection signal based on a first clock signal. The delay pulse module 11 is used to generate a third clock signal based on the second clock signal and the sensing pulse signal. The electrode array module 12a includes a charging unit 120a, a plurality of electrode pixel units 121a, and a sampling unit 122a. The electrode array module 12b similarly includes a charging unit 120b, a plurality of electrode pixel units 121b, and a sampling unit 122b.

The charging units 120a and 120b are used to generate charging signals based on the sensing pulse signals. For example, when an object contacts the electrode pixel unit 121a, the capacitance value of the electrode pixel unit 121a changes, and the charging unit 120a is further used to convert the change in capacitance value into a difference in charging time.

A plurality of electrode pixel units 121a form an MxN array, where M is a positive integer greater than or equal to 1 and N is a positive integer greater than or equal to 1. A plurality of electrode pixel units 121b similarly form an MxN array. The electrode array module 12a is used to sequentially select electrode pixel units 121a of a specific pattern based on the selection signal, and the electrode pixel units 121a of the specific pattern in the electrode array module 12a generate a sampling signal based on the charging signal. The sampling unit 122a is used to generate the sampling signal and the third clock signal to generate a sensing output signal. The operation method of the electrode array module 12b is the same as that of the electrode array module 12a. More specifically, the delay pulse module 11 generates the third clock signal and is used to determine whether to generate a sensing output signal by the sampling unit 122a of the electrode array module 12a or the sampling unit 122b of the electrode array module 12b based on the third clock signal.

The programmable module 10 is used to generate the selection signal, and the electrode array module 12a is used to sequentially select electrode pixel units 121a of a specific pattern based on the selection signal. For example, the specific pattern may be, but is not limited to, 1x1, 1x2, 2x2, 2x4, or 4x4. The appropriate specific pattern is selected depending on the size of the test sample.

Sampling circuits, such as ADCs, in prior art capacitive sensor arrays generally require large areas and complex systems to achieve high accuracy. Therefore, prior art sampling circuits are difficult to embed in the pixels of the sensor array, limiting the sensing output. Compared to prior art, the capacitive sensor array chip with programmable pixel resolution of the present invention integrates a charging unit 120a, multiple electrode pixel units 121a, and a sampling unit 122a into an electrode array module 12a, and realizes a time-sharing time-to-digital converter (ts-TDC) through control of the programmable module 10 and delay pulse module 11. This method allows the capacitive sensor array chip to operate in global shutter mode, freeing up more area under the electrodes and providing potential for future multi-module integration. The programmable electrode geometry of this design improves sensing performance by capturing multiple frames of the same or different patterns for improved digital image processing.

Second Embodiment
2, which is a schematic circuit diagram of an electrode array module according to a second embodiment of the present invention. In one embodiment, the electrode array module 20 includes a charging unit 200, electrode pixel units 201a, 201b, 201c, and 201d, and a sampling unit 202. The electrode pixel unit 201a includes an electrode 2010a, a first transistor 2011a having a drain connected to the electrode 2010a, and a switching logic gate 2012a. The input terminal of the switching logic gate 2012a receives a charging signal, and the output terminal of the switching logic gate 2012a is connected to the gate of the first transistor 2011a. Similarly, the electrode pixel units 201b, 201c, and 201d respectively include electrodes 2010b, 2010c, and 2010d, first transistors 2011b, 2011c, and 2011d, and switching logic gates 2012b, 2012c, and 2012d.

In one embodiment, the first transistors 2012a, 2012b, 2012c, and 2012d may be, but are not limited to, NMOS or PMOS transistors. The switching logic gates 2011a, 2011b, 2011c, and 2011d may be implemented with, but are not limited to, logic gates such as NOR or NAND, or a single NMOS.

In the embodiment of Figure 2, 2x2 electrode pixel units 201a, 201b, 201c, and 201d are given as an example, but the present invention is not limited to this.

In one embodiment, the selection signal includes M-bit row signals R[0] to R[M-1] and N-bit column signals C[0] to C[N-1].

In one embodiment, the charging unit 200 includes a first voltage source 2000, first PMOS transistors 2001a, 2001b, and 2001c connected to the first voltage source 2000, and a first CMOS inverter 2002 connected to the first PMOS transistor 2001c. The input terminal of the first CMOS inverter 2002 receives the sensing pulse signal SP, and the output terminal of the first CMOS inverter 2002 outputs a charging signal. In the embodiment of FIG. 2, three first PMOS transistors 2001a, 2001b, and 2001c are used as an example, but are not limited to this. In other embodiments, more or fewer first PMOS transistors can be used to adjust the current.

In one embodiment, the sampling unit 202 includes a first INV 2020, a second multiplexer 2021, and a second DFF 2022. The input terminal of the first INV 2020 receives the sampling signal, and the first input terminal of the second multiplexer 2021 is connected to the output terminal of the first INV 2020. The clock input terminal of the second DFF 2022 receives the third clock signal DFF_CLK, and the input terminal of the second DFF 2022 is connected to the output terminal of the second multiplexer 2021. The output terminal of the second DFF 2022 outputs the sensing output signal, which is connected to the second input terminal of the second multiplexer of the sampling unit of the next electrode array module to form a serial output. In other words, signal Qn is sent to the next electrode array module, and signal Qn-1 is from the previous electrode array module.

In one embodiment, the first INV2020 is a Hi-Skew inverter to improve sensing efficiency.

[Third embodiment]
3, which is a schematic circuit diagram of a delay pulse module according to a third embodiment of the present invention. In one embodiment, the delay pulse module 30 includes a first DFF 300, a delay time generator 301 connected to the output of the first DFF 300, and a first multiplexer 302. A clock input of the first DFF 300 receives the sensing pulse signal SP, a first input of the first multiplexer 302 is connected to the output of the delay time generator 301, a second input of the first multiplexer 302 receives the second clock signal scan_out_clk, and an output of the first multiplexer 302 outputs the third clock signal DFF_CLK.

[Fourth embodiment]
Referring to FIG. 4, FIG. 4 is a timing chart of a fourth embodiment of the present invention. As shown, the circuit includes a sensing pulse signal SP and a voltage signal Electrode(N0) of the electrode pixel unit. Din(N1) is the input signal of the second DFF. The third clock signal DFF_CLK is the signal at the clock input terminal of the second DFF. The sensing output signal DFF_Qn is the signal at the output terminal of the second DFF. First, a charging unit is used to convert capacitance to time. When the sensing pulse signal SP is at a low potential, the first voltage source begins to charge the electrode pixel unit M. The output of the first INV is turned off until the voltage signal Electrode(N0) of the electrode pixel unit reaches 0.8 VDD. Then, the second DFF performs sampling N with a delay code. FIG. 4 shows the cases of no sample (Cpar) and sample presence (Csample), where both signals Qpar and Qsample are logic 1. This process is repeated multiple times, with a slight delay in the sampling time of the second DFF. For signal Qpar after t1, since it has reached 0.8 VDD earlier, signal Qpar becomes logic 0, while signal Qsample remains logic 1. For signal Qsample after t2, it finally drops to logic 0. Finally, all Q values are added together to obtain the exact time difference between the two cases. The corresponding capacitance result can be estimated. The design scheme of the present invention allows the sampling circuit to be embedded in the pixel, and the purpose can be achieved using only a simple delay time generator.

Fifth Embodiment
5, which is a schematic circuit diagram of a charging unit according to a fifth embodiment of the present invention. In one embodiment, the charging unit 500 includes a second voltage source 5000, a second CMOS inverter 5001 connected to the second voltage source 5000, second PMOS transistors 5002a, 5002b, and 5002c connected to the second CMOS inverter 5001, and a third multiplexer 5003 connected to the second PMOS transistor 5002b. The first input terminal of the third multiplexer 5003 is connected to a control voltage Vctrl. When the third multiplexer 5003 selects the first input terminal, the control voltage Vctrl can be changed to control the magnitude of the output current of the second PMOS transistors 5002a, 5002b, and 5002c, thereby adjusting the sensing amplification factor (sensitivity). The input terminal of the second CMOS inverter 5001 receives a sensing pulse signal SP, and the output terminal of the second CMOS inverter 5001 outputs a charging signal. 5, three second PMOSs 5002a, 5002b, and 5002c are used as an example, but are not limited to this, in other embodiments, more or fewer second PMOSs can be used to regulate the current.

In one embodiment of the present invention, the electrodes of the electrode pixel units are arranged in a square, staggered, or aligned pattern, and the electrode pixel units may or may not include a guard ring.

In one embodiment, the electrode pixel unit is made of the metal material of the top layer or the next layer.

Sixth Embodiment
6(a) and 6(b) are a schematic diagram and a schematic cross-sectional view of a sampling device according to a sixth embodiment of the present invention. In one embodiment, the sampling device of the present invention includes the capacitive sensor array chip 60 having a programmable pixel resolution according to the first aspect of the present invention, a protective layer 61 covering the capacitive sensor array chip 60 having a programmable pixel resolution, a container 62 for accommodating the capacitive sensor array chip 60 having a programmable pixel resolution, and an insulator 63 provided to surround the capacitive sensor array chip 60 having a programmable pixel resolution and for firmly connecting the container 62 and the capacitive sensor array chip 60 having a programmable pixel resolution.

In one embodiment, the capacitive sensor array chip 60 with programmable pixel resolution can be secured to a printed circuit board 64 with an insulator 63, such as, but not limited to, a high-resistivity, non-conductive medical-grade epoxy resin, to effectively shield the chip's metal lines.

In one embodiment, the capacitance sensor array chip 60 with programmable pixel resolution adjustment has a sensing area 601, and preferably, the upper part of the sensing area 601 can be brought into contact with the biological sample to be tested.

In one embodiment, the capacitive sensor array chip 60 with programmable pixel resolution adjustment includes bonding wires 602 that can be secured and protected with another insulating material to prevent interaction with liquids or solutions. In one embodiment, the capacitive sensor array chip 60 with programmable pixel resolution adjustment is bonded to only one side to ensure sufficient space is available for other operations.

In accordance with the present invention, a layer of medical-grade epoxy 63 can be applied and cured around the periphery of the programmably pixel-resolution-adjustable capacitance sensor array chip 60. A laser-cut container, such as a Petri dish 62, is then attached to a printed circuit board 64, and the medical epoxy is re-cured. This Petri dish can then contain culture media and cells and be used for cell growth and interaction.

Seventh Embodiment
7 is a schematic diagram of a control system according to a seventh embodiment of the present invention. Referring to both FIGS. 1 and 7, the control system of the present invention is used to control the capacitance sensor array chip 70 for programmably adjusting pixel resolution to sense a sample, and includes a capacitance sensor array chip 70 for programmably adjusting pixel resolution, and a control unit 71 for determining resistance and capacitance values during sampling and controlling the electrode pixel units 121 a.

In one embodiment, the control unit 71 includes a shift register 711 for determining the resistance and capacitance values at the time of sampling to establish equivalent electrode sizes.

In one embodiment, the shift register 711 may be an (M+N)-bit shift register.

Referring again to FIG. 3, in one embodiment, the control unit 71 may be used to sense the pulse signal SP and then generate and transmit a pulse to the delay time generator 301.

In one embodiment, the control system further includes a programmable board 72 connected to the capacitive sensor array chip 70 for programmably adjusting the pixel resolution and the control unit 71 for arranging signals from the control unit 71 and transmitting information generated by the capacitive sensor array chip 70 for programmably adjusting the pixel resolution to an external processor 74.

In one embodiment, the programmable board 72 may be, for example, but is not limited to, a Field Programmable Gate Array (FPGA) board.

In one embodiment, the control system further comprises an optical imaging device 73 for recording the sample and generating an optical pattern. According to the present invention, the optical imaging device 73 may be, for example, but not limited to, a microscope. In one embodiment, the optical pattern can be used to verify the correlation of a capacitance pattern obtained after the control system collects the sample.

Specifically, the control system provided by the present invention can be used to capture first noise, which is fixed pattern noise on a capacitive sensor array chip, to programmably adjust the pixel resolution.

In one embodiment, the control system can be used to continuously acquire the sample to obtain multiple frames. In a preferred embodiment, the programmable board is used to average the multiple frames to remove second noise and obtain the appearance characteristics of the sample, where the second noise is random noise.

In a preferred embodiment, the programmable board can further remove the first noise in the sample's appearance characteristics to obtain a pure sample value of the sample.

Eighth Embodiment
Referring to FIG. 8, FIG. 8 is a diagram showing capacitance values measured by taking different samples in different fused pixel modes using a control system according to an eighth embodiment of the present invention.

8 shows the control system provided by the present invention sampling each electrode unit with dynamically adjusted pixel patterns of 1x1, 1x2, 2x2, 2x4, and 4x4, respectively, including four samples: silicone oil (OIL), StemFlex ^™ stem cell medium (CM), saturated saline (SALT), and deionized water (DIW). The resulting capacitance reflects the magnitude of the relative dielectric constant. The values are SALT, CM, DIW, and OIL, from largest to smallest, which is consistent with the results of the prior art.

Ninth Embodiment
Referring to FIG. 9, this figure shows the results of real-time sample monitoring using a control system according to a ninth embodiment of the present invention. The real-time monitoring times were t = 5, 15, 25, 27, 29, and 110 minutes. Saturated saline was used as the target sample. At room temperature, 10 μL of saturated saline was dropped onto the surface of a capacitance sensor array chip with programmable pixel resolution provided by the present invention, and the liquid and solid detection results were observed. In this embodiment, 4×4 pixel fusion was enabled. As can be seen from FIG. 9, the droplet gradually became smaller before t = 27 minutes. After that, some flake-like salt crystals appeared, but since they were not in direct contact with the chip surface, they only reflected their shape. This indicates that the longer the distance between the sample and the chip, the smaller the change in capacitance due to the electrodes.

The capacitive sensor array chip, sampling device, and control system with programmable pixel resolution provided by the present invention can effectively adjust the electrode size to adapt to the size of the biological sample, thereby achieving better sensing results and simultaneously balancing spatial resolution and sensitivity. The present invention uses a time-to-digital conversion circuit method and a noise reduction method to achieve a higher pixel count in global shutter mode, and the sampling results are consistent with the configuration of the optical imaging device. The present invention integrates multiple functions and contributes to the development of a large number of biological applications and personalized medicine.

10 Programmable module, 11 Delay pulse module, 12a, 12b Electrode array module, 120a, 120b Charging unit, 121a, 121b Electrode pixel unit, 122a, 122b Sampling unit, 20 Electrode array module, 200 Charging unit, 201a, 201b, 201c, 201d Electrode pixel unit, 202 Sampling unit, 2010a, 2010b, 2010c, 2010d Electrode, 2011a, 2011b, 2011c, 2011d First transistor, 2012a, 2012b, 2012c, 2012d Switching logic gate, 2000 First voltage source, 2001a, 2001b, 2001c First PMOS, 2002 First CMOS inverter, 2020 First INV 2020, 2021 Second multiplexer, 2022 Second DFF, 30 Delay pulse module, 300 First DFF, 301 Delay time generator, 302 First multiplexer, 500 Charging unit, 5000 Second voltage source, 5001 Second CMOS inverter 5001, 5002a, 5002b, 5002c Second PMOS, 5002a, 5002b, 5002c, 5003 Third multiplexer, 60 Capacitive sensor array chip for programmably adjusting pixel resolution, 61 Protective layer, 62 Container, 63 Insulator, 64 Printed circuit board, 601 Sensing area, 602 Bonding wire, 70 Capacitive sensor array chip for programmably adjusting pixel resolution, 71 Control unit, 711 Shift register, 72 Programmable substrate, 73 Optical imaging device, 74 External processor.

Claims (19)

a programmable module for generating a selection signal based on a first clock signal;
a delay pulse module for generating a third clock signal based on the second clock signal and the sensing pulse signal;
a plurality of electrode array modules;
Equipped with
The electrode array module includes:
a charging unit for generating a charging signal based on the sensing pulse signal;
M×N electrode pixel units (M is a positive integer of 1 or more, and N is a positive integer of 1 or more) forming an array;
a sampling unit for generating a sensing output signal according to a sampling signal and the third clock signal ;
A capacitive sensor array chip with programmable pixel resolution, which is used to sequentially select the electrode pixel units of a specific pattern based on the selection signal, and the electrode pixel units of the specific pattern are used to generate the sampling signal based on the charging signal. The electrode pixel unit comprises:
An electrode;
a first transistor having a drain connected to the electrode;
2. The capacitive sensor array chip for programmably adjusting pixel resolution according to claim 1, further comprising: an input terminal for receiving the selection signal; and an output terminal comprising a switching logic gate connected to the gate of the first transistor. A capacitive sensor array chip with programmable pixel resolution adjustment as described in claim 1, wherein the selection signal includes an M-bit row signal and an N-bit column signal. The charging unit is
a first voltage source;
At least one first PMOS connected to the first voltage source;
a first CMOS inverter connected to the at least one first PMOS;
2. The capacitive sensor array chip as claimed in claim 1, wherein an input terminal of the first CMOS inverter receives the sensing pulse signal, and an output terminal of the first CMOS inverter outputs the charging signal. The charging unit is
a second voltage source;
a second CMOS inverter connected to the second voltage source;
at least one second PMOS connected to the second CMOS inverter;
a third multiplexer connected to the at least one second PMOS, the third multiplexer having a first input terminal connected to a control voltage, and controlling an output current of the at least one second PMOS through the control voltage when the third multiplexer selects the first input terminal;
2. The capacitive sensor array chip as claimed in claim 1, wherein an input terminal of the second CMOS inverter receives the sensing pulse signal, and an output terminal of the second CMOS inverter outputs the charging signal. The delay pulse module includes:
a first DFF having a clock input terminal for receiving the sensing pulse signal;
a delay time generator (DPDG) connected to the output terminal of the first DFF;
a first multiplexer;
2. The capacitive sensor array chip with programmable pixel resolution adjustment as claimed in claim 1, wherein a first input terminal of the first multiplexer is connected to an output terminal of the delay time generator, a second input terminal of the first multiplexer receives a second clock signal, and an output terminal of the first multiplexer outputs the third clock signal. The sampling unit comprises:
a first INV having an input terminal for receiving the sampling signal;
a second multiplexer having a first input connected to the output of the first INV;
a second DFF;
2. The capacitive sensor array chip with programmable pixel resolution adjustment as claimed in claim 1, wherein a clock input terminal of the second DFF receives the third clock signal, an input terminal of the second DFF is connected to an output terminal of the second multiplexer, and an output terminal of the second DFF outputs the sensing output signal and is connected to a second input terminal of the second multiplexer of a sampling unit of a next electrode array module to form a serial output. The capacitive sensor array chip for programmably adjusting pixel resolution described in claim 7, wherein the first INV is a Hi-Skew inverter. A capacitive sensor array chip with programmable pixel resolution adjustment as described in claim 2, wherein the electrodes of the electrode pixel units are arranged in a square, staggered, or aligned pattern, and the electrode pixel units may or may not include a guard ring. A capacitive sensor array chip with programmable pixel resolution adjustment as described in claim 9, wherein the electrode pixel unit is made of a metal material in the top layer or a metal material in the next layer. A capacitive sensor array chip with programmable pixel resolution adjustment according to any one of claims 1 to 9;
a protective layer covering the capacitive sensor array chip for programmably adjusting pixel resolution;
a container for containing the capacitive sensor array chip for programmably adjusting pixel resolution;
A sampling device comprising an insulator arranged to surround the capacitance sensor array chip for programmably adjusting the pixel resolution, and for firmly connecting the container and the capacitance sensor array chip for programmably adjusting the pixel resolution. a capacitance sensor array chip that programmably adjusts pixel resolution and is used to sense the sample;
A capacitive sensor array chip with programmable pixel resolution adjustment according to any one of claims 1 to 10;
a control unit for determining resistance and capacitance values at sampling time to control the electrode pixel unit. The control system of claim 12 further comprising a programmable board connected to the capacitance sensor array chip that programmably adjusts pixel resolution and the control unit, for arranging signals from the control unit and transmitting information generated by the capacitance sensor array chip that programmably adjusts pixel resolution to an external processor. The control system of claim 12, further comprising an optical imaging device for recording the sample to generate an optical pattern. 15. The control system of claim 14 , wherein the optical pattern is used to verify the correlation of a capacitance pattern obtained after the control system has taken the sample. 14. The control system of claim 13 , adapted to capture a first noise that is a fixed pattern noise on a capacitive sensor array chip that programmably adjusts the pixel resolution. 17. The control system of claim 16 , adapted to take the samples sequentially to obtain multiple frames. 18. The control system of claim 17 , wherein the programmable board is used to average the plurality of frames to remove second noise and obtain the appearance characteristics of the specimen, the second noise being random noise. 20. The control system of claim 17 , wherein the programmable board further removes the first noise in the appearance characteristics of the specimen to obtain a pure specimen value of the specimen.