JP6590331B2 - Control circuit - Google Patents

Description

The present invention relates to control of an EA-LD in which a DC-driven semiconductor LD (Laser Diode) and an EA (Electro Absorption) modulator that modulates laser light emitted from the semiconductor LD are integrated.

Patent Document 1 discloses a technique related to an optical communication device provided with a semiconductor laser module. The input signal generation unit inputs an input signal corresponding to the transmission signal to the base of the transistor. A limiter circuit is connected between the emitter of the transistor and the ground, and a semiconductor laser is connected in parallel with the limiter circuit. A limiter circuit is provided in parallel with the LD so that a voltage higher than that set by the limiter circuit is not applied to the LD.

Patent Document 2 discloses a technique related to a semiconductor laser driving device. When the differential voltage value obtained by subtracting the input voltage value from the reference voltage value is a positive value, the semiconductor laser driving device increases the driving current of the semiconductor laser, and the differential voltage value is a negative value. In this case, the drive current of the semiconductor laser is decreased. This semiconductor laser driving device includes a driving current control unit, a resistor that converts a supplied current into a voltage, a current source that supplies the converted voltage as an input voltage to the driving current control unit, and one of the lights from the semiconductor laser. And a current path for supplying a predetermined amount of current to the resistor when the semiconductor laser is turned off. And an instantaneous light emission avoiding circuit that cuts off the current path when the light output interruption is released.

Patent Document 3 discloses a technique related to a control circuit of a semiconductor light emitting element. A switch is arranged in parallel with the semiconductor laser, and the current flowing through the parallel circuit of the semiconductor laser and the switch is controlled by the current control unit so as to be a constant value. When the switch is turned off, the semiconductor laser emits light, and when it is turned on, the light emission stops.

JP 2003-198048 A JP 2009-194138 A JP 2011-2109 A

An EA-LD in which a DC-driven semiconductor LD and an EA modulator that modulates laser light emitted from the semiconductor LD are integrated (generally, a distributed feedback LD (DFB-LD) is used as the LD). In many cases, this is called EA-DFB) and is mounted on an optical module, and is generally driven with a constant current by, for example, a constant current circuit as shown in FIG. All the configurations shown in FIG. 5 are included in the configuration shown in FIG. 1 and will be described in detail later. In FIG. 5, the same reference numerals as those in FIGS. 1 to 4 are given to the same configurations as those shown in FIGS.

Referring to FIG. 5, in the EA-LD, the cathode of the LD 3a and the cathode of the EA modulator 3b are connected to each other. The output of the differential amplifier 4a is connected to the base of an npn type transistor 4b (Tr) as a current buffer. The current detection resistor 4d is connected to the emitter of Tr4b, and the cathode of the LD 3a is connected to the collector. The power supply VD of the optical module is supplied to drive the LD 3a. The power supply VD applies a bias to the LD 3a. The problem of the driving circuit of the EA-LD3 is that a power supply circuit 4c (CPU, D / A-) that generates a reference potential to be applied to each circuit element, particularly the differential amplifier 4a, Tr4b, or the non-inverting input of the differential amplifier 4a. C and the like) are not guaranteed to have transient characteristics.

For example, the differential amplifier 4a is supplied with the power supply VCC of the optical module as a positive power supply and GND (ground) as a negative power supply, but after the power supply VCC is cut off (off), finally, 0 [ V], the output behavior (potential) of the differential amplifier 4a is not guaranteed. If the output potential of the differential amplifier 4a monotonously converges to 0 [V] as it approaches 0 [V] after the power supply VCC is turned off, there is no problem, but the output potential of the differential amplifier 4a is the power supply. It is also assumed that the potential once increases from the off-state potential of VCC and then converges to 0 [V]. In addition, with respect to Tr4b, there is a case where the base potential rises once and Tr4b becomes conductive while the collector potential remains as a significant value by the bypass capacitor 5. In this case, an excessively large current flows through the LD 3a.

As for the EA modulator 3b, when the reverse bias by the signal source 11 that supplies the modulation signal to the EA modulator 3b becomes deeper, the light absorption increases and the laser light from the LD 3a is not output. However, when the reverse bias to the EA modulator 3b decreases transiently in a state where a current flows through the LD 3a (a state where the LD 3a emits light) due to the transient characteristics of the differential amplifiers 4a and Tr4b as described above, It is also assumed that light absorption by the modulator 3b disappears and the light emitted from the LD 3a is output from the EA modulator 3b as it is.

Accordingly, an object of the present invention has been made in view of the above matters, and prevents the output of laser light from an LD mounted on an optical module in a transient state that occurs when the power is turned on or off. To provide a circuit.

A control circuit according to an aspect of the present invention is an over-emission control circuit of an LD mounted on an optical module, and includes a transistor (TR) connected in parallel to the LD, an inverting gate circuit that drives the TR, The power supply of the inverting gate circuit is supplied from the power supply of the optical module via a power supply maintaining circuit composed of a diode and a capacitor, and the input of the inverting gate circuit is connected to the power supply of the optical module, The inverting gate circuit detects disconnection of the power supply, sets the output of the inverting gate circuit to H level, and makes the TR conductive.

According to the above, it is possible to provide a circuit that prevents the output of laser light from the LD mounted on the optical module in a transient state that occurs when the power is turned on or off.

FIG. 1 is a diagram illustrating a configuration of a control circuit according to the embodiment. FIG. 2 is a diagram illustrating a configuration of a modified example of the control circuit according to the embodiment. FIG. 3 is a diagram illustrating a configuration of a modified example of the control circuit according to the embodiment. FIG. 4 is a diagram illustrating a configuration of a modified example of the control circuit according to the embodiment. FIG. 5 is a diagram showing a conventional control circuit.

[Description of Embodiment of the Present Invention]
First, embodiments of the present invention will be listed and described. A control circuit according to an aspect of the present invention is an over-emission control circuit for an LD mounted on an optical module, and includes a TR connected in parallel to the LD and an inverting gate circuit for driving the TR. The power supply of the inverting gate circuit is supplied from the power supply of the optical module via a power supply maintaining circuit composed of a diode and a capacitor, and the input of the inverting gate circuit is connected to the power supply of the optical module, Detects the disconnection of the power supply, sets the output of the inverting gate circuit to H level (High level), and makes the TR conductive. In this way, the inverting gate circuit conducts TR when detecting the disconnection of the power supply of the optical module, so that the current flowing through the LD flows to the TR connected in parallel with the LD, and the LD power The light emission can be stopped immediately. Therefore, it is possible to immediately prevent over-light emission of the LD in response to the disconnection of the power supply of the optical module regardless of the transient characteristics of each circuit element of the optical module.

The control circuit according to one embodiment of the present invention maintains the output of the inverting gate circuit at the H level for a predetermined period after the power supply of the optical module is turned off. Since the conduction of the TR is maintained for a predetermined period after the power is turned off and the light emission of the LD is suppressed, for example, until the transient state that occurs after the power is turned off and the operation of the optical module is sufficiently stopped , LD can be prevented from emitting light.

A control circuit according to one embodiment of the present invention includes a plurality of power supplies that output different voltages from each other, and the inverting gate circuit is connected to each of the plurality of power supplies. One disconnection is detected, the H level is maintained within a predetermined period after the disconnection, and the TR is turned on. As described above, even when the optical module includes a plurality of power supplies, the LD can be prevented from emitting light if any one of the plurality of power supplies is disconnected.

In the control circuit according to one aspect of the present invention, the LD is connected between the constant current circuit and the power supply of the optical module, and one current terminal of the TR is connected to the power supply of the optical module, The other current terminal of TR is grounded. When the LD is connected between the power supply of the optical module and the constant current circuit in this way, since the TR is connected to the power supply, the charge remaining in the power supply when the power supply is cut off does not pass through the LD. It can be discharged immediately via TR. Therefore, it is possible to prevent the LD from emitting light immediately in response to power-off of the optical module.

In the control circuit according to one embodiment of the present invention, the LD is connected between the output of the constant current circuit and the ground, and one current terminal of the TR is between the output of the constant current circuit and the LD. And the other current terminal of the TR is grounded. When the LD is connected between the constant current circuit and the ground in this way, since the TR is connected between the output of the current circuit and the LD, the power supply and current are supplied in response to the power supply of the optical module being cut off. The electric charge remaining in the circuit can be immediately discharged through TR without going through LD. Therefore, it is possible to prevent the LD from emitting light immediately in response to power-off of the optical module.

In the control circuit according to one embodiment of the present invention, the LD can be an LD portion of an EA-LD element (EA-LD: Electro Absorption Laser Diode). As described above, the control circuit according to one embodiment of the present invention can be applied to the LD of the EA-LD element.

[Details of the embodiment of the present invention]
Specific examples of the control circuit according to the embodiment of the present invention will be described below with reference to the drawings. In addition, this invention is not limited to these illustrations, is shown by the claim, and intends that all the changes within the meaning and range equivalent to a claim are included.

FIG. 1 shows a circuit diagram of a control circuit 2 according to the embodiment. The control circuit 2 is mounted on the optical module 1 including the EA-LD 3 and is a control circuit that suppresses transient over-emission of the LD 3a (semiconductor laser). The control circuit 2 includes a constant current circuit 4, a bypass capacitor 5, TR 6 (switching transistor), an inverting gate circuit 7, and a power supply maintenance circuit 8. The control circuit 2 receives power supply from a plurality of power supplies, that is, the power supply VDD and the power supply VCC. Hereinafter, the power supply VDD and the power supply VCC may be collectively referred to as the power supply of the optical module 1.

The EA-LD 3 includes an LD 3a and an EA modulator 3b, and outputs modulated signal light. The LD 3a is an LD unit of the EA-LD 3, and the EA modulator 3b is a modulation unit of the EA-LD 3. The LD 3a is connected between the constant current circuit 4 and the power source VD. The cathode of the LD 3a is connected to the cathode of the EA modulator 3b and the collector of Tr4b, and the anode is connected to the power source VD. The anode is further connected to one electrode of the bypass capacitor 5, and the other electrode of the bypass capacitor 5 is grounded. The anode of the EA modulator 3b is connected to the signal source 11, and a modulation signal is provided from the signal source 11.

The LD 3a and the EA modulator 3b are generally integrated on a common semiconductor substrate (many n-type semiconductors). The semiconductor substrate serves as a common cathode for the LD 3a and the EA modulator 3b. Each anode is electrically isolated from each other. A direct current is supplied from the anode of the LD 3a toward the semiconductor substrate. The LD 3a generates laser light by this direct current, and this laser light enters the EA modulator 3b. The EA modulator 3b modulates the incident laser light in accordance with a modulation signal supplied to the anode. The EA modulator 3b outputs the modulated light. The EA modulator 3b utilizes an electro-optical effect (Franz-Keldish effect) of a semiconductor material.

The constant current circuit 4 includes differential amplifiers 4a and Tr4b, a power supply circuit 4c, and a resistor 4d, and constitutes a constant current circuit for the LD 3a. The non-inverting input of the differential amplifier 4a is connected to the power supply circuit 4c and receives a reference potential from the power supply circuit 4c. The inverting input of the differential amplifier 4a is connected to the emitter of Tr4b, and is further grounded through a resistor 4d. The output of the differential amplifier 4a is connected to the base of Tr4b. The differential amplifier 4a adjusts the output potential so that the potential applied to the non-inverting input is equal to the potential of the inverting input. That is, the output potential is adjusted so that a current that equalizes the potential drop generated in the resistor 4d and the potential of the non-inverting input flows through the LD 3a.

The bypass capacitor 5 is a circuit for removing high-frequency noise in order to stabilize the LD 3a and the power supply VD. In order to increase the noise removal rate, the capacitance value must be set to a relatively large value. Accordingly, immediately after the power source VD is turned off, electric charge remains in the bypass capacitor 5, and this electric charge is discharged through the LD 3a or TR6.

TR6 according to the present embodiment is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). TR6 is connected in parallel to the LD 3a with respect to the power source VD and the bypass capacitor 5. The drain of TR6 is connected to power supply VD and bypass capacitor 5, and the anode of LD 3a. The source of TR6 is grounded, and the gate is connected to the output of the inverting gate circuit 7.

The inverting gate circuit 7 includes an OR gate 7a and inverters 7b1 and 7b2, and drives TR6. The input of inverting gate circuit 7 receives power supply VCC and power supply VDD. The input of the OR gate 7a is connected to the power supply VCC via the inverter 7b1, and is connected to another power supply VDD via the inverter 7b2. The output of the inverting gate circuit 7 is connected to the gate of TR6. The power supply for the inverting gate circuit 7 is supplied from the power supply VCC / VDD via the power supply maintaining circuit 8. The inverting gate circuit 7 detects that at least one of the power supply VCC and the power supply VDD is cut off, and after this cut-off, maintains the output of the inverting gate circuit 7 at the H level (high level) for a predetermined time. Make TR6 conductive.

The power supply maintenance circuit 8 is a circuit for maintaining the power supply of the inverting gate circuit 7. The power supply maintenance circuit 8 includes a diode 8a and a bypass capacitor 8b. One terminal of the cathode of the diode 8a and the bypass capacitor 8b is connected to the respective power supply terminals of the OR gate 7a and the inverters 7b1 and 7b2, and the other terminal is grounded. ing. The anode of the diode 8a is biased by any power supply VCC / VDD. OR gate 7a and inverters 7b1 and 7b2 receive power supply VDD / VCC smoothed by diode 8a and bypass capacitor 8b.

The inverting gate circuit 7 will be described in detail. When the power supply VCC and the power supply VDD are normal, that is, when all the power supplies of the optical module 1 are turned on and within the normal voltage range and the optical module 1 is in a steady operation state, the values are 5.0 as an example. It is often set to the order of [V], 3.3 [V]. The power supply VCC is led to one input of the OR gate 7a via the inverter 7b1, and the power supply VDD is led to the other input of the OR gate 7a via the inverter 7b2. In a normal case, that is, when the two power supplies VCC and VDD are in the normal voltage range, the two inputs of the OR gate 7a are all at the L level (Low level), and therefore the output of the OR gate 7a is at the L level. It is maintained and TR6 is maintained in the off state (state that is not conducting). In this case, the driving of the LD 3a is not affected at all. When one of the power supplies is turned off and its value decreases toward 0 [V], one input of the OR gate 7a becomes H level and its output also becomes H level. In this case, since the gate of TR6 is set to the H level, TR6 becomes conductive and the charge stored in the bypass capacitor 5 is rapidly discharged via TR6. That is, the residual charge of the bypass capacitor 5 is prevented from flowing into the LD 3a, and as a result, the transient light emission of the LD 3a is also suppressed. The output of the OR gate 7a is output within a predetermined period after any of the power supplies VCC and VDD connected to the power supply maintenance circuit 8 is turned off, for example, until the residual charge of the bypass capacitor 5 is discharged via TR6. During this period, the H level is maintained.

Here, the operation of the OR gate 7a will be described. The power source of the OR gate 7a is supplied from one of the power sources VCC and VDD via the diode 8a, and is bypassed by a relatively large capacity bypass capacitor 8b. There are two discharge paths for the bypass capacitor 8b: a path through the inverting gate circuit 7 and a path toward the power supply VDD / VCC that gradually decreases to 0 [V] through the diode 8a. Generally, other circuits such as a constant current circuit 4 are connected to the power supply VCC / VDD. A current larger than the bias current for the inverting gate circuit 7 is supplied to these circuits, and the current rapidly decreases toward 0 [V] during a transient when the power is turned off. Therefore, the anode potential of the diode 8a becomes lower than the cathode potential, and a situation occurs in which the diode 8a is reverse-biased. The bias of the bypass capacitor 8b eventually reaches 0 [V] due to the discharge through the inverting gate circuit 7, but the time constant τ1 of the decrease is the resistance value R11 when the diode 8a is reverse biased and the inverting gate circuit. (R11 // Z7) × C1 determined by the parallel value of the impedance Z7 estimated from the diode 8a and the capacitance C1 of the bypass capacitor 8b. The power supply voltage of the circuit 7 has a sufficiently significant value for a long time, and remains as a value sufficient for normal operation of the OR gate 7a and the two inverters 7b1 and 7b2. That is, the logic operation of the inverting gate circuit 7 is maintained even when the power supply VCC / VDD is gradually decreasing toward 0 [V]. As described above, since the power supply of the inverting gate circuit 7 is supplied from the power supply VCC / VDD via the power supply maintaining circuit 8, the power supply of the optical module 1 is turned off and the power supply is turned on during the transition toward 0 [V]. If the sustain circuit 8 is not used, the logical operation of the OR gate 7a cannot be guaranteed. However, by interposing the power supply sustain circuit 8, the logical operation of the inverting gate circuit 7 is guaranteed even during this transition. The

The inverting gate circuit 7 needs a threshold value for inverting the outputs of the inverters 7b1 and 7b2 from the L level to the H level in accordance with the decrease of the power supply VCC / VDD. That is, the inverting gate circuit 7 is in a state where the optical module 1 is not sufficiently stopped after the optical module 1 is turned off and other circuit functions in the optical module 1 are still operating. It is necessary to quickly invert the output of the OR gate 7a from the L level to the H level and to make the TR6 conductive. This is achieved by adjusting the inversion thresholds of the inverters 7b1 and 7b2. By setting this threshold value of the inverting gate circuit 7 to a value slightly reduced from the specification voltage of the power supply VCC and the power supply VDD (for example, a value reduced by 10% from the lowest value within the specification range of the power supply VCC and the power supply VDD). The electric charge stored in the bypass capacitor 5 can be discharged quickly.

According to the configuration described above, the TR 6 is connected to the power source VD for supplying power to the LD 3a and the bypass capacitor 5, and the control circuit 2 uses the inverting gate circuit 7 to turn off the power source of the optical module 1 to 0 [V]. Since the TR6 is immediately turned on in a transient state that decreases toward the power source, the electric charge remaining in the power supply VD and the bypass capacitor 5 is rapidly discharged through the TR6, and the power supply VD and the bypass capacitor 5 are supplied to other power supply VCC, power supply VDD, etc. First, it decreases to 0 [V]. As described above, when the inverting gate circuit 7 detects that the optical module 1 is turned off, the inverting gate circuit 7 conducts TR6, so that the current flowing through the LD 3a flows into TR6 connected in parallel to the LD 3a, and thus the optical module 1 power supply. In response to the interruption, the light emission of the LD 3a can be stopped immediately. Accordingly, it is possible to prevent laser light from being transiently output from the EA modulator 3b regardless of the transient characteristics of each circuit element of the optical module 1. Furthermore, the optical module 1 has a plurality of power sources (in the embodiment shown in FIG. 1, the power source VDD and the power source VCC). If any one of the plurality of power sources is turned off, the LD 3a can be prevented from emitting light.

(Modification 1)
As the inverting gate circuit, a simpler configuration that does not use the OR gate 7a can be used. The control circuit 2a according to the first modification implements the same function as the control circuit 2 by using the two transistors Tr71a and 71b without using the OR gate 7a.

As shown in FIG. 2, the difference between the control circuit 2 and the control circuit 2 a is that the inverting gate circuit 7 is replaced with an inverting gate circuit 71. Except for this difference, the configuration of the control circuit 2 a is the same as the configuration of the control circuit 2. In particular, in the control circuit 2a, the configuration connected to the drain of TR6 is the same as that of the control circuit 2, and is not shown. The inverting gate circuit 71 corresponds to a NAND gate composed of discrete semiconductor elements, and its logical operation is exactly the same as that of the inverting gate circuit 7.

As shown in FIG. 2, the inverting gate circuit 71 is a circuit in which Trs 71a and 71b are vertically stacked. The inverting gate circuit 71 includes Trs 71a and 71b and resistors 71c to 71g. The collector of Tr71a is connected to the gate of TR6, and is further connected to the power supply maintaining circuit 8 via a resistor 71g. The emitter is connected to the collector of Tr 71b. The emitter of Tr 71b is grounded. The base of the Tr 71a is connected to the power supply VCC via a resistor 71c and grounded via a resistor 71d. The base of the Tr 71b is connected to the power supply VDD via a resistor 71e and grounded via a resistor 71f. That is, Tr 71a receives a potential obtained by dividing the power supply VCC by two resistors 71c and 71d, and Tr 71b receives a potential obtained by dividing the power supply VDD by two resistors 71e and 71f.

When one of Tr 71a and 71b is turned off and becomes non-conductive, the discharge path of bypass capacitor 8b of power maintenance circuit 8 is substantially lost (bypassing other than reverse-biased diode 8a and turned off Tr 71b). There is no substantial discharge path of the capacitor 8b), and the inverting gate circuit 71 is in an operating state (inverted gate circuit) for a relatively long time even after the power supply VCC or the power supply VDD is cut to decrease to 0 [V]. The output of 71 is in the H level).

The threshold value for inverting the output of the inverting gate circuit 71 from the L level to the H level adjusts the dividing ratio of the resistance dividing circuit with respect to the power supply VCC and the power supply VDD supplied to the base of the Tr 71a and the base of the Tr 71b, respectively. Can be obtained. This resistance divider circuit is composed of resistors 71c, 71d, 71e, 71f, and the division ratio of the resistor divider circuit is the ratio of the resistance values of the resistor 71c and the resistor 71d with respect to the power supply VCC, and with respect to the power supply VDD. It is a ratio of resistance values of the resistor 71e and the resistor 71f. The power supply VCC / VDD smoothed by the diode 8a and the bypass capacitor 8b of the power supply maintenance circuit 8 is supplied to two Trs 71a and 71b that are vertically stacked via a resistor 71g.

The resistor 71g determines the power consumption of the inverting gate circuit 71 when both the power supply VCC and the power supply VDD are on. When the resistor 71g does not exist, only the diode 8a is substantially connected between the power supply VCC / VDD and the ground at the time of steady operation when the two Trs 71a and 71b are both conductive. Current flows. When the resistor 71g is connected in series with the diode 8a, a potential drop occurs in the resistor 71g, and an appropriate current flows out from the power supply VCC / VDD.

(Modification 2)
In the case of the configuration of the control circuit 2 or the control circuit 2a, there is a possibility that TR6 becomes conductive until the power supply of the optical module 1 is turned on and then the power supply VDD and the power supply VCC reach the normal voltage range. In this case, a large rush current (current absorbed by GND via TR6) may flow through the power supply VD. The power supply VCC and the power supply VDD have risen to some extent (even if the power supply VCC and the power supply VDD do not reach the normal voltage range, the power supply of the inverting gate circuits 7 and 71 supplied via the diode 8a is the inverting gate. Such a situation may occur in a state where the circuits 7 and 71 are established to the extent that they function normally.

The control circuit 2b according to the modification 2 has a configuration that ensures a suitable operation even in a transient state that occurs when the power of the optical module 1 is turned on. Similar to the control circuit 2, the control circuit 2b is a control circuit that suppresses over-emission of the LD 3a of the EA-LD 3, and has at least the same effects as the control circuit 2.

As shown in FIG. 3, the difference between the control circuit 2 and the control circuit 2a and the control circuit 2b is that, in the control circuit 2b, the power maintenance circuit 8 is replaced with a power maintenance circuit 81, and the gate of TR6 is It is grounded through a resistor 9. Except for the above differences, the configuration of the control circuit 2b is the same as the configuration of the control circuit 2 or the control circuit 2a. In particular, in the control circuit 2b, the configuration connected to the drain of TR6 is the same as that of the control circuit 2 and the control circuit 2a, and is not shown.

The power maintenance circuit 81 includes a diode 8a, a bypass capacitor 8b, and a resistor 8c. In the control circuit 2b, (1) the output (input of the gate of TR6) of the inverting gate circuit 7 (or the inverting gate circuit 71) is grounded by the resistor 9 (pull-down resistor), and (2) the inverting gate circuit 7 (or The power of the inverting gate circuit 71) is supplied via a series circuit of a diode 8a and a resistor 8c.

The pull-down resistor 9 does not turn on TR6 by setting the gate of TR6 to L level when the output of the inverting gate circuit 7 (or inverting gate circuit 71) is not fixed. Further, supplying the power supply VCC / VDD to the inverting gate circuits 7 and 71 via the series circuit of the diode 8a and the resistor 8c means that the resistance value of the diode 8a during forward bias is R and the capacitance of the bypass capacitor 8b. Is equivalent to setting C1 and the resistance value of the resistor 9 to R2, and setting the rise time constant τ2 of the power source of the inverting gate circuits 7 and 71 to (R12 + R2) × C1. Although the diode 8a has a relatively large operating resistance value at zero bias, once the current starts to flow, the operating resistance value rapidly decreases and decreases to several Ω to several tens of Ω under normal operating conditions. The rise time constant τ2 is increased by setting the resistance value of the resistor 8c to about several hundreds [Ω], and the inverting gate circuits 7 and 71 are raised with a delay from the rise of the power supply VCC and the power supply VDD. During this time, since the gate of TR6 is pulled down, it is possible to prevent the conduction of TR6 during the transition from when the power source of the optical module 1 is turned on until it reaches a steady value. When the resistance value R12 is about several hundreds [Ω], the resistor 8c does not hinder the steady operation of the inverting gate circuits 7 and 71. Further, the inverting gate circuits 7 and 71 may perform a logic operation in a transient state that occurs when the power of the optical module 1 is turned off. In this case, the power necessary for the operation of the inverting gate circuits 7 and 71 is as follows: This can be covered by a bypass capacitor 8b connected in parallel to the power supply VCC / VDD. Even if such a relatively large resistance value is adopted as the series resistor 8c, the transient response of the inverting gate circuits 7 and 71 is not affected by the resistor 8c.

(Modification 3)
The control circuit 2c according to the modified example 3 has a configuration that enables a suitable operation even in a transient state that occurs when the optical module 1 is powered on, as in the modified example 2. Similar to the control circuit 2, the control circuit 2c is a control circuit that suppresses over-emission of the LD 3a of the EA-LD 3, and at least has the same effect as the control circuit 2.

As shown in FIG. 4, the differences between the control circuits 2 and 2a and the control circuit 2c are as follows. (1) In the control circuit 2c, the constant current circuit 4 is replaced with a constant current circuit 41. 41 is provided between the power supply VD and the bypass capacitor 5 and the anode of LD3a, (2) the cathode of LD3a is directly grounded, (3) the drain of TR6 is connected to the anode of LD3a, It is connected to the bypass capacitor 5 via the constant current circuit 41. Except for the above differences, the configuration of the control circuit 2c is the same as the configuration of the control circuit 2 or the control circuit 2a.

The constant current circuit 41 includes a differential amplifier 4a, a power supply circuit 4c, resistors 4d, and Tr4e, and configures a constant current source for the LD 3a in the same manner as the constant current circuit 4. Tr4e is a pnp type Tr. The base of Tr4e is connected to the output of the differential amplifier 4a, and the emitter is connected to the power supply VD and the bypass capacitor 5 via a resistor 4d. The collector of Tr4e is connected to the anode of LD3a and the drain of TR6. The LD 3a is connected between the output of the constant current circuit 41 (Tr4e collector) and GND. The power source VD is supplied from the bypass capacitor 5 to the anode of the LD 3a via the resistors 4d and Tr4e of the constant current circuit 41. The power supply circuit 4c is provided between the non-inverting input of the differential amplifier 4a and the power supply VD. The inverting input of the differential amplifier 4a is connected to the emitter of Tr4e. The drain of TR6 is connected between the output of the constant current circuit 41 and the LD 3a. The value of the constant current supplied to the LD 3a is determined by the potential difference between the input potential supplied from the power supply circuit 4c to the non-inverting input of the differential amplifier 4a and the power supply VD. When the potential of the power supply circuit 4c is increased, the value of the constant current is decreased, and when the potential is decreased, the current value is increased.

According to the control circuit 2c, the LD 3a is connected between the output of the bypass capacitor 5 and the GND, and the TR 6 is connected between the output of the constant current circuit 4 and the LD 3a. Accordingly, the charge remaining in the power supply VD (further, the bypass capacitor 5) and the constant current circuit 41 can be immediately discharged through TR6 without passing through the LD 3a.

Also in the control circuit 2c, TR6 is connected in parallel with the LD 3a. However, unlike the control circuits 2, 2a, and 2b, in the case of the control circuit 2c, the TR 6 does not bypass the resistor 4d. In the case of the control circuits 2 and 2a, the rush current (current flowing directly into GND via TR6) caused by the TR6 bypassing the resistor 4d has been a problem. However, in the control circuit 2c, TR6 is turned on and becomes conductive. Even if a current flows through TR6, the current flows through the resistor 4d, so that the rush current is effectively limited by the resistor 4d.

While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

In the present embodiment, as an example, the power source of the optical module 1 has been described as being composed of a plurality of power sources (power source VDD, power source VCC, etc.). It may be the case. In the case of the control circuit having such a configuration, the OR gate 7a of the inverting gate circuit 7 is unnecessary, and the TR 6 is driven by the output of the inverter of the inverting gate circuit 7 connected to the power source (one of the inverters 7b1 and 7b2). The power of the inverter is supplied through the power maintenance circuit 8.

Further, the inverting gate circuit 7 in which the OR gate 7a and the inverters 7b1 and 7b2 are combined can be used in place of the NAND gate. The NAND gate is supplied with power via the power supply maintaining circuit 8 in the same manner as the inverting gate circuit 7. The function similar to that of the inverting gate circuit 7 is exhibited.

DESCRIPTION OF SYMBOLS 1 ... Optical module, 11 ... Signal source, 2, 2a, 2b, 2c ... Control circuit, 3 ... EA-LD, 3a ... LD, 3b ... EA modulator, 4, 41 ... Constant current circuit, 4a ... Differential amplifier 4b, 4e, 71a, 71b ... Tr, 4c ... power supply circuit, 4d, 71c, 71d, 71e, 71f, 71g, 8c, 9 ... resistor, 8, 81 ... power supply maintenance circuit, 5, 8b ... bypass capacitor, 6 ... TR, 7, 71 ... Inverting gate circuit, 7a ... OR gate, 7b1, 7b2 ... Inverter, 8a ... Diode.

Claims (5)

A control circuit for a semiconductor laser mounted on an optical module,
A switching transistor connected in parallel to the semiconductor laser;
An inverting gate circuit for driving the switching transistor ;
A constant current circuit connected to the semiconductor laser;
Including
The power of the constant current circuit is supplied from the power of the optical module,
The power supply of the inverting gate circuit is supplied from the power supply of the optical module through a power supply maintenance circuit composed of a diode and a capacitor.
The input of the inverting gate circuit is connected to the power supply of the optical module,
The inverting gate circuit detects the disconnection of the power of the optical module connected to the input, to set the output of the inverting gate circuit to a high level to turn on the switching transistor, the current flowing through the semiconductor laser A control circuit that suppresses excessive light emission of the semiconductor laser by flowing it through a switching transistor . The control circuit according to claim 1, wherein the output of the inverting gate circuit is maintained at the high level for a predetermined period after the optical module is powered off. The power supply of the optical module comprises a plurality of power supplies that output different voltages from each other,
The inverting gate circuit is connected to each of the plurality of power supplies, detects the disconnection of any one of the plurality of power supplies, maintains the high level for a predetermined period after the disconnection, and The control circuit according to claim 1, wherein the control circuit is made conductive. The semiconductor laser is connected between a power supply and a bypass capacitor of the constant current circuit and the optical module,
The control circuit according to claim 1, wherein one current terminal of the switching transistor is connected to a power source of the optical module, and the other current terminal of the switching transistor is grounded. The semiconductor laser is connected between ground and the output of the constant current circuit,
The constant current circuit is connected between the semiconductor laser and the power supply and bypass capacitor of the optical module;
The current terminal of the switching transistor is connected between the output of the constant current circuit and the semiconductor laser, and the other current terminal of the switching transistor is grounded. Control circuit according to.

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