JP5970071B2 - Device structure manufacturing method and structure - Google Patents

Description

  The present invention relates to three-dimensional (3D) packaging, and more particularly to through-silicon vias (TSV).

  3D packaging has emerged as a solution for microelectronics development towards system on chip (SOC) and system in package (SIP). In particular, a 3D flip chip structure with TSV may be widely applied. A TSV 3D package generally includes two or more chips stacked vertically and has vias that penetrate the silicon substrate instead of edge wiring that forms electrical connections between circuits on each chip. .

  During the TSV process, the device wafer is processed to be thin, typically 50 μm to 100 μm thick. In order to handle such a thin wafer safely, some kind of support system is required to hold the wafer flat and protect the thin and fragile wafer from mechanical damage such as chipping, cracking and the like.

  Current TSV processes typically involve removing a thinly processed device wafer from a support wafer at the end of the process flow sequence after attaching the device wafer to a temporary support wafer using a temporary adhesive. Including. Several implementations may be used to remove the thinly processed device wafer from the support wafer.

  In the first implementation, removal by heat is used. In this mounting form, a thermoplastic resin adhesive is used to temporarily bond the device wafer to the temporary support wafer. After the TSV process is complete, heat is used to soften the adhesive and mechanically remove the thinly processed device wafer from the temporary support wafer.

  In the second implementation, removal by ultraviolet light (UV) is used. In this implementation, a device wafer is temporarily attached to a glass transport wafer using a UV curable temporary adhesive with a light-to-heat conversion (LTHC) release coating. After the TSV process is complete, laser irradiation is applied to the LTHC layer that has penetrated the glass transport wafer to weaken the LTHC layer. Then, the glass transport wafer is lifted off from the thinly processed device wafer, and the UV curing adhesive is peeled off from the thinly processed device wafer.

  In the third implementation, solvent removal is used. In this mounting form, a device wafer is attached to a temporary transport wafer having holes using a temporary adhesive. After the TSV process is completed, a solvent is applied through the holes of the temporary transfer wafer to dissolve and remove the temporary adhesive.

  In each of the three implementations described above, the temporary adhesive is mechanically soft and provides minimal protection against mechanical damage to the fragile device wafer during TSV processing.

It is the vertical sectional view which showed the device wafer of the reversed state before bonding with respect to the support substrate which concerns on embodiment of this invention.

It is the vertical sectional view which showed the inverted device wafer in the state joined with respect to the support substrate which concerns on embodiment of this invention.

It is the vertical sectional view which showed the via final process of the inverted device wafer in the state joined to the support substrate concerning the embodiment of the present invention.

It is the vertical sectional view which showed the processed device wafer after removing the support substrate which concerns on embodiment of this invention.

It is a side view of 3D package which mounts TSV concerning the embodiment of the present invention.

It is the figure which showed the system which concerns on embodiment of this invention.

  In various embodiments, structures and methods for handling device wafers during TSV processing will be described with reference to the drawings. However, some embodiments may be practiced without one or more of these details, and may be implemented using other well-known methods and combinations of materials. In the following detailed description, numerous details are set forth, such as specific materials and processes, in order to provide a thorough understanding of the present invention. In addition, to avoid unnecessarily obscuring the present invention, well-known packaging processes and manufacturing techniques are used throughout this specification which are not described in detail. The phrase “an embodiment” means that a particular feature, structure, material, or characteristic associated with the embodiment is included in at least one of the embodiments of the invention. Thus, the phrases “one embodiment” or “an embodiment” used in various places in the specification do not necessarily indicate the same embodiment of the invention. Also, in one or more embodiments of the present invention, certain features, structures, materials or characteristics may be suitably combined.

  The terms “over”, “to”, “between”, “on” are relative to one layer relative to another. May refer to a location. The term one layer is “over” or “joined” to another layer means that one layer is in direct contact with another layer. And including one or more intervening layers. The term “one layer” “between” a plurality of layers includes the case where one layer is in direct contact with the plurality of layers and the case of having one or more intervening layers. On the other hand, the phrase “the first layer is on the second layer” means that the first layer contacts the second layer.

  Embodiments of the present invention provide permanent adhesion, such as cured thermoset materials, that can provide mechanical rigidity and robustness to mechanically maintain substrate support and TSV processing of device wafers. Structures and processes for temporarily supporting device wear using agents are described. Such a process involves attaching the device wafer to the temporary support substrate using a permanent adhesive material and removing the temporary support substrate after the TSV process is complete. The “via end” TSV process (via is formed after the metal interconnect structure) is illustrated and described in detail below, but embodiments of the present invention are not limited thereto, and embodiments of the present invention are “ Via first “TSV process (via is formed before microelectronic device is formed)” and “via intermediate” TSV process (via microelectronic device formation and metal wiring structure formation, vias are formed. Can be used in the same way. Furthermore, although the embodiments are described with reference to TSV processing, the embodiments are also applicable to substrates of wafers other than silicon, such as compound III-V wafers or II-VI wafers.

In one embodiment, a structure is described that includes a semiconductor substrate having a front surface, a back surface, a microelectronic device, and vias (eg, TSVs) extending through the semiconductor substrate between the back surface and the entire surface. One or more bumps from the solder reflow are formed on the front surface, and a cured thermosetting material is formed on the front surface and around the one or more reflowed solder bumps. The cured thermoset material and the one or more reflowed solder bumps together form a flat front interface. The flat front joint surface may be exposed. The flat front side joining surface may not have a polished surface. In an embodiment, the semiconductor substrate may be a TSV processing device wafer having a plurality of structures as described above. Alternatively, the TSV processing device wafer may be divided individually to form a plurality of semiconductor substrates, and the plurality of semiconductor substrates are not subjected to further processing to form a plurality of chips. It may also be incorporated into a 3D package structure. Thus, in one embodiment, the structure is a chip.

  In one embodiment, the 3D package structure is described as comprising a substrate and a chip having the above structure with a flat front bonding surface attached to the substrate. In such an embodiment, one or more chips may be stacked on each other.

In one embodiment, a method is described that includes bonding a device wafer to a support substrate under heat and pressure. The device wafer may have a front surface and one or more solder bumps formed on the front surface. The support substrate may have a flat wetting surface. A layer of thermosetting material may be formed on the flat wetting surface. During bonding under heat and pressure, the solder bumps penetrate the layer of thermosetting material and spread over or wet the flat wetting surface during reflow to at least cause the thermosetting material to Partially cure. The step of wetting the flat wetting surface with the solder bump and the step of at least partially curing the thermosetting material may be performed simultaneously. The support substrate may have a flat wetting surface over the entire surface. Then, the support substrate is removed to expose a flat front joint surface having reflowed solder bumps and at least partially cured thermosetting material. In the via final process flow, one or more vias may be formed to extend between the front and back surfaces of the device wafer after bonding and prior to removal of the support substrate. Prior to forming the vias, a grinding or chemical mechanical polishing (CMP) process may be performed on the backside of the device wafer to reduce the thickness of the device wafer. In a via first or intermediate via process flow, one or more vias may be formed to extend between the front and back surfaces of the device wafer prior to bonding.

  The manufacturing method will be described with reference to FIGS. FIG. 1 shows the device wafer 100 in an inverted state on the support substrate 200. The device wafer 100 may have a front surface 102 and a back surface 104. The device wafer 100 may have various forms. For example, the device wafer may be a bulk semiconductor, may have an epitaxial layer formed on the bulk semiconductor, may have a semiconductor-on-insulator (SOI) structure, or other structure. May be used. In the particular embodiment illustrated, the device wafer 100 may have an (SOI) structure that includes a semiconductor layer 116 and a bulk substrate 118 stacked on an insulating layer 114. The device wafer 100 further includes metal-insulator-semiconductor field effect transistors (MOSFETs), capacitors, inductors, resistors, diodes, micro-electro-mechanical systems (MEMS), other active or passive elements, and combinations thereof. It may have doped regions or other doped structures to form a variety of microelectronic devices.

  A metal wiring structure 112 may be formed on the front surface 102 of the substrate 100. As shown in the figure, the metal wiring structure 112 includes a plurality of wiring layers formed of a conductive metal such as copper or aluminum, and an interlayer insulating material such as silicon oxide, carbon-doped oxide, or silicon nitride. A passivation layer 113 may be formed over the metal wiring structure 112 to provide physical and chemical protection. One or more conductive pads 108 (for example, copper, aluminum, etc.) may be provided on the opening formed in the passivation layer 113, and one or more solder bumps 106 may be formed on the conductive pad 108. Good.

  The support substrate 200 may have a flat wetting surface 202 formed from a material that has an acceptable adhesion to the solder bump 106 material during reflow, and the solder bump 106 is flat during reflow. Spread over the wet surface 202 and wet the wet surface. In some embodiments, the solder bumps 106 may be formed from a tin-based material, a lead-tin based material, an indium-based material, or a lead-based material. In such embodiments, the flat wetting surface 202 may be formed from a metal having solder wettability such as nickel, gold, platinum, palladium, cobalt, copper, iron and steel. Further, the flat wet surface 202 can be used as having sufficient adhesion to the solder bump 106 during reflow.

  The flat wetting surface 202 may be formed integrally with the support substrate 200. For example, the support substrate 200 may be formed of a bulk metal, such as copper, having a smooth, flat wetting surface 202, for example. The flat wetting surface 202 may also be formed as a separate layer 204 on the bulk substrate 206. Layer 204 may have desirable properties suitable for wettability or polishing. The material for forming the bulk substrate 206 and layer 204 may be selected based on cost, etching characteristics, ease of removal after the device wafer is bonded to the support substrate, and the like.

  Referring again to FIG. 1, a layer of thermosetting material 208 is formed on the flat wetting surface 202. The layer of thermosetting material 208 may be formed of a suitable underfill type or buffer coating type material such as, but not limited to, epoxy resin, phenolic resin, polyimide and polybenzoxazole (PBO). . The layer of thermosetting material 208 may be applied in various ways such as spin coating and sheet lamination. Also, the layer of thermosetting material 208 may be B-stage cured before or after being applied to the flat wetting surface 202.

  FIG. 2 shows how the device wafer 100 is bonded to the support substrate 200 under heat and pressure. As shown, a plurality of solder bumps 106 extends through or wets the flat wetting surface 202 through the layer of thermosetting material 208 during reflow. At the same time, the layer of thermosetting material 208 is at least partially cured.

  According to an embodiment of the present invention, bonding is performed on a wafer scale, the bond head lifts the back surface 104 of the device wafer 100, places the device wafer 100 on the support substrate 200, and the support substrate 200 is a pedestal. Supported by. The specific thermal bonding profile will depend on the type of solder bump 106 and thermosetting material 208. In an example of the thermocompression bonding (TCB) process, the support substrate 200 is held at a stage temperature of 100 ° C., for example. The device wafer 100 may be picked up using a bond head at a staged temperature of 100 ° C., for example. Then, after the device wafer 100 is disposed on the support substrate 200, the bond head temperature is raised to a temperature (for example, 250 ° C. to 300 ° C.) higher than the liquid phase temperature of the solder bump 106. After maintaining the bond head temperature at a temperature (TAL) above the liquid phase temperature of the solder for a certain period, the bond head temperature is lowered to a temperature below the liquid phase temperature of the solder bump 106 (for example, 180 ° C.). At this point, the bonded structure may be removed from the pedestal for offline curing or on the pedestal at an elevated temperature in an in-line fashion to substantially fully cure the thermoset material 208. It may be held.

  FIG. 3 illustrates a “via last process” where the device wafer 100 is processed to form at least one via 120 (eg, TSV) that extends between the front surface 102 and the back surface 104 of the wafer. ing. Although only one via 120 is shown in FIG. 3, this is for illustrative purposes, and a plurality of vias may be formed in a device wafer according to an embodiment of the present invention. Also, although a “via last process” is illustrated, embodiments of the present invention are directed to a “via first” process and a “via intermediate” in which a via 120 is formed before the device wafer 100 is bonded to the support substrate 200. "Applicable to processing.

Prior to the formation of vias 120, by grinding and / or chemical mechanical polishing the back 104 (CMP), it may be thinned device wafer 100. For example, in one embodiment, the device wafer 100 may be thinned from about 50 μm to 100 μm. After the device wafer 100 is thinned, a passivation film or laminated film 130 may be formed on the back surface 104 to provide an airtight barrier. Although not shown, the device wafer 100 may be further processed to form redistribution lines (RDL) and other build-up structures before, during or after processing of the vias 120.

  After forming a photoresist material on the backside 104 of the thinned device wafer 100 to form the via 120, the photoresist material may be exposed and developed. After development, there are openings where it is desired to provide resist-coated vias 120. In the case of a silicon device wafer, plasma etching is performed so as to penetrate the passivation film or laminated film 130 and the bulk silicon 118, and etching is performed with a copper landing pad on the front surface 102 (device side) of the thinly processed device wafer 100. By stopping, a through silicon via (TSV) opening is formed. Then, the photoresist is removed, and the remaining etching polymer or residue is removed from the device wafer 100. Then, an insulating layer 124 is deposited on the wafer surface, and the bottom and side walls of the through silicon via (TSV) 120 are lined. Suitable materials include, but are not limited to, silicon dioxide, silicon nitride, silicon carbide, and various polymers. These materials can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating.

  Then, using an anisotropic etching process, the insulating layer 124 is removed from the bottom surface of the TSV 120 and the passivation film or the laminated film 130, and at the same time, an insulating layer having a certain thickness is left on the side wall of the TSV 120. A barrier layer 126 and seed layer may then be deposited on the surface of the device wafer. For example, the barrier layer 126 includes tantalum, titanium, or cobalt. The seed layer may be copper, for example. Then, a copper blanket layer is formed on the surface of the device wafer by electroplating, and the TSV is completely filled with the copper 122. As shown in FIG. 3, the excess portions appearing on the surface of the copper and the barrier layer are removed by CMP.

  As shown in FIG. 4, when the processing of the thinly processed device wafer 100 is completed, the support substrate 200 is selectively removed. In one embodiment, the support substrate 200 is copper and selectively etches the support substrate using, for example, a wet etchant such as Transcene's copper etchant 49-1, but is substantially affected. The support substrate is removed, leaving no reflowed solder bumps 106 and cured thermoset material 208 left. In another embodiment, the support substrate 200 is formed of a bulk substrate 206 such as a metal or plastic material with a thin layer 204. If the bulk substrate 206 is a plastic material, a wet etch may be performed to remove the thin layer 204 after removing the bulk substrate 206 using a solvent. In either aspect, removal of the support substrate 200 exposes a flat front bonding surface 140 that includes the reflowed solder bumps 106 and the at least partially cured thermoset material 208. In many embodiments, the thermosetting material 208 is already fully cured before the support substrate 200 is removed.

  After removal of the support substrate 200, the resulting plurality of structures formed on the substrate 100 may be individually separated and may or may not be further processed to form the chip 500. Well, the resulting chip may be incorporated into a 3D package structure. For example, the resulting structure may be further processed to include a build-up structure on the flat front joint surface 140 or back surface 104. An example of a 3D package structure is shown in FIG. 5, in which one or more chips 500 including TSVs formed in accordance with an embodiment of the present invention are stacked on a substrate 600 and connected to a solder element 502. Yes. The substrate 600 is, for example, a printed circuit board or a laminated board.

  FIG. 6 shows a computer system according to an embodiment of the present invention. System 690 includes a processor 610, a memory device 620, a memory controller 630, a graphics controller 640, an input / output (I / O) controller 650, a display 652, a keyboard 654, a pointing device 656, and peripherals 658, which are In embodiments, they may be communicatively coupled to each other via bus 660. The processor 610 may be a general purpose processor or an application specific integrated circuit (ASIC). The I / O controller 650 may include a communication module for wired communication or wireless communication. The memory device 620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or a combination of these memory devices. Thus, in certain embodiments, memory device 620 in system 690 need not include DRAM devices.

  One or more of the components shown in the system 690 may be included and / or included in one or more integrated circuit packages such as, for example, the chip 500 or 3D package structure of FIG. For example, an integrated circuit package in which at least a portion of processor 610, memory device 620, I / O controller 650, or a combination of these components includes at least one embodiment of the structure described in the various embodiments above. May be included.

  These elements have conventional functions well known in the art. In particular, the memory device 620 may be used as a long-term location for executable instructions for a method of forming a package structure according to embodiments of the present invention in some cases. In other embodiments, the memory device 620 may be used to store execution instructions of a method for forming a package structure according to embodiments of the present invention for a short period of time while being executed by the processor 610. . In addition, the instructions may be stored or associated with a machine-accessible medium that is communicatively coupled to the system, examples of which include compact disk read-only memory (CD-ROM). ), DVD (digital versatile disk), floppy disk, carrier wave, and / or other propagated signals. In one embodiment, memory device 620 may provide executable instructions to processor 610 for execution.

  The system 690 is a computer (eg, desktop, laptop, handheld server, web application, router, etc.), wireless communication device (eg, mobile phone, cordless phone, pager (registered trademark), personal digital assistance (PDA), etc.) Computer peripherals (eg printers, scanners, monitors, etc.), entertainment devices (eg TV, radio, stereo, tape and compact disc players, video cassette recorders, video cameras, MP3 (Motion Picture Experts Group, Audio Layer 3) Players, video games, watches, etc.).

  Although the invention has been specifically described as structural features and / or method operations, the invention as defined by the appended claims is not necessarily limited to the specific features or operations described. The particular features and operations disclosed are to be understood as normal implementations of the claimed invention useful for illustrating the invention.

Claims (21)

The semiconductor substrate having a front surface, a back surface, a microelectronic device, and vias extending through the semiconductor substrate between the back surface and the front surface;
And Handa bumps formed on the front surface,
And a cured thermosetting material formed around the front and on the previous SL Handa bumps,
Wherein the cured thermosetting material and before Symbol Handa bumps, to form a flat front mating surface that is exposed, the structure. The structure of claim 1, wherein the flat front joining surface does not have a polished surface. The structure of claim 1 or 2 , wherein the via comprises copper. 4. The cured thermosetting material according to any one of claims 1 to 3, wherein the cured thermosetting material is selected from the group consisting of a cured epoxy resin, a cured phenolic resin, a cured polyimide, and a cured polybenzoxazole (PBO). Description structure. A substrate,
A 3D package structure comprising a chip,
The chip is
The semiconductor substrate including a front surface, a back surface, a microelectronic device, and vias extending through the semiconductor substrate between the back surface and the front surface;
And Handa bumps formed on the front surface,
Anda cured thermosetting material formed around the front and on the previous SL Handa bumps,
Wherein the cured thermosetting material and before Symbol Handa bumps forms a flat front mating surface exposed,
The flat front joint surface is a 3D package structure attached to the substrate. The 3D package structure according to claim 5 , further comprising a second chip stacked on the chip. The 3D package structure of claim 6 , further comprising a system having a bus communicatively connected to the 3D package structure. Providing a device wafer having a front surface and solder bumps formed on the front surface;
Providing a support substrate having a flat wetting surface on which a layer of thermosetting material is formed;
Bonding the device wafer to the support substrate under heat and pressure;
Removing the support substrate to expose a flat front joint surface having the reflowed solder bumps and the at least partially cured thermoset material, and
The joining step includes
Passing the solder bumps through the layer of thermosetting material;
Wetting the flat wetting surface with the solder bumps during reflow of the solder bumps;
And a step of at least partially curing said thermosetting material, method of manufacturing a device structure.   9. The method of manufacturing a device structure according to claim 8, wherein the step of wetting the flat wetting surface with the solder bump and the step of at least partially curing the thermosetting material are performed simultaneously. The method for manufacturing a device structure according to claim 8, wherein the support substrate has the flat wet surface over one surface. The method of claim 8 , further comprising forming vias extending between the front and back surfaces of the device wafer after bonding the device wafer to the support substrate. Method for manufacturing the device structure . The method of manufacturing a device structure according to claim 11 , further comprising the step of forming the via before the step of removing the support substrate. Grinding or polishing the backside of the device wafer to reduce the thickness of the device wafer after bonding the device wafer to the support substrate and before forming the via A method for manufacturing a device structure according to claim 11 or 12 . The method of claim 8 , further comprising forming vias extending between the front and back surfaces of the device wafer prior to bonding the device wafer to the support substrate. Method for manufacturing the device structure . 15. The device structure fabrication according to any one of claims 8 to 14, wherein the flat wetting surface comprises a material selected from the group consisting of nickel, gold, platinum, palladium, cobalt, copper, iron and steel. Method. The device structure manufacturing method according to claim 8 , wherein the support substrate is a bulk substrate. The method of manufacturing a device structure according to claim 16 , wherein the bulk substrate is copper. The device structure manufacturing method according to claim 8 , wherein the support substrate has a bulk substrate and a coating layer including the flat wetting surface. The method of manufacturing a device structure according to any one of claims 8 to 18 , further comprising spin coating or laminating the layer of the thermosetting material on the flat wetting surface of the support substrate. 20. The method of manufacturing a device structure according to claim 19 , wherein the layer of thermosetting material is B-stage cured prior to the step of bonding the device wafer to the support substrate. Attaching a first die to the flat front joining surface;
21. The method of manufacturing a device structure according to any one of claims 8 to 20, further comprising: attaching a second die to a back surface of the device wafer.

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