JP5865769B2 - Manufacturing method of multilayer wiring board - Google Patents

Description

  The present invention relates to a method for manufacturing a multilayer wiring board in which a plurality of chip component connection terminals to which chip components can be connected are disposed on a main surface of a substrate.

  In recent years, semiconductor integrated circuit chips (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a semiconductor package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the semiconductor package is mounted on a motherboard.

  As the IC chip mounting wiring board constituting the package, a multilayer wiring board formed by laminating a plurality of resin insulation layers and a plurality of conductor layers is used. A plurality of IC chip connection terminals for connecting IC chips are provided on the main surface of the multilayer wiring board, and a plurality of mother board connection terminals for connecting to the mother board (mother board) on the back surface of the board. Is provided. In this type of multilayer wiring board, the wiring pattern of the conductor layer and the IC chip connection terminal are formed by copper plating in order to achieve a fine pitch (for example, see Patent Document 1).

JP 2005-272874 A

  By the way, in the multilayer wiring board, the area ratio of the copper plating layer formed on the inner layer side (area ratio of the conductor layer) is usually about 60% to 80%, whereas the area of the copper plating layer on the main surface of the board. The ratio (area ratio of each IC chip connection terminal) may be less than 10%. In general, the IC chip connection terminals are arranged in the center of the main surface of the substrate. In this case, when the copper plating layer of the IC chip connection terminal is formed, the concentration of the plating current occurs, and the thickness of the copper plating layer varies. As a result, the connection reliability between each IC chip connection terminal of the multilayer wiring board and the IC chip is lowered. In addition to the IC chip, some of the board main surfaces of the multilayer wiring board are provided with connection terminals for connecting chip components such as a chip capacitor. However, the connection terminals also vary in thickness. .

  Patent Document 1 discloses a method of gradually increasing the plating current density from the initial current density in order to suppress variations in the shape and height of the conductor bumps. Even if this method is adopted, if the IC chip connection terminal is arranged in the center of the main surface of the substrate, concentration of the plating current cannot be avoided, resulting in variations in the thickness of the copper plating layer. End up.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a multilayer wiring board capable of suppressing variation in thickness of chip component connection terminals and improving connection reliability with chip components. There is to do.

Means for solving the above problems (Means 1) have a substrate main surface and a substrate back surface, a structure in which a plurality of resin insulation layers and a plurality of conductor layers are laminated, and chip components can be connected. A method of manufacturing a multilayer wiring board in which a plurality of chip component connection terminals are disposed on the main surface of the substrate, wherein the plurality of chip component connection terminals are formed on the surface of the outermost resin insulation layer exposed on the main surface of the substrate. production of a multilayer wiring board, which comprises a plating layer forming step of forming a dummy plating layer around the chip component connecting a group of forming a product plating layer terminals and ing, or one group of the product plating layer There is a way.

  According to the invention described in Means 1, by performing the plating layer forming step, dummy plating is also performed around the product plating layer in addition to the product plating layer serving as the chip component connection terminal on the main surface of the multilayer wiring board. A layer is formed. In this case, the area ratio of the plating layer on the substrate main surface can be increased, the concentration of the plating current is avoided, and the thickness variation of the product plating layer is eliminated. As a result, each chip component connection terminal can be formed with a uniform thickness on the main surface of the multilayer wiring board, and the connection reliability between each chip component connection terminal and the chip component can be improved.

  In the method of manufacturing a multilayer wiring board, a resist forming step for forming an etching resist so as to cover the product plating layer on the substrate main surface side, and an exposed dummy plating layer on the substrate main surface side are removed by etching. It is preferable to further include a plating layer removing step. In this case, only the product plating layer that becomes the chip component connection terminal remains on the main surface of the multilayer wiring board. For this reason, plating for improving solder wettability can be reliably formed only on the surface of the product plating layer. Further, the problem that the chip component is erroneously connected to the dummy plating layer is avoided.

  In the plating layer forming step, the dummy plating layer is preferably formed so that the area ratio of the plating layer to the surface area of the substrate main surface is 60% or more and 95% or less. In this way, concentration of the plating current can be reliably avoided, and the product plating layer can be formed with a uniform thickness.

  Also, when manufacturing a multilayer wiring board that does not have a core substrate, it is supported at the interface between the metal foil and the laminating step of laminating multiple resin insulation layers and multiple conductor layers via a metal foil on a supporting substrate. A base material separation step of separating the base material and exposing the metal foil on the back surface side of the substrate. When the plating layer removal step is performed after the base material separation step, the metal foil on the back surface side of the substrate can be removed by etching at the same time as the dummy plating layer on the substrate main surface side is removed by etching. For this reason, a multilayer wiring board can be manufactured with the same man-hour compared with the conventional manufacturing method, and manufacturing cost can be restrained low.

  On the main surface of the multilayer wiring board, a plurality of IC chip connection terminals to which an IC chip can be connected and a plurality of capacitor connection terminals to which a chip capacitor can be connected may be provided as chip component connection terminals. In this case, the product plating layers of the plurality of IC chip connection terminals and the plurality of capacitor connection terminals can be formed with a uniform thickness, and the connection reliability with the IC chip and the chip capacitor can be improved.

  The pattern shape of the dummy plating layer is not particularly limited, and can be appropriately changed according to the shape and area ratio of the product plating layer. Specifically, the dummy plating layer may be a plain pattern (solid pattern) having a large area, or may be a plain pattern having a mesh. Furthermore, the dummy plating layer may have a pattern corresponding to the shape and size of the adjacent product plating layer.

  In the plating layer forming step, it is preferable to form a filled via for connecting the inner layer side conductor layer and the chip component connection terminal simultaneously with the product plating layer and the dummy plating layer.

  Further, it is preferable to form the dummy plating layer so that the dummy plating layer has an area ratio of 10 times or more of the product plating layer. In this way, even when the area ratio of the product plating layer is small, it is possible to reliably avoid current concentration during plating by providing a dummy plating layer having a large area.

  The product plating layer and the dummy plating layer are preferably formed by copper plating. Thus, when the product plating layer is formed by copper plating, the electrical resistance of the chip component connection terminal can be kept low.

  The resin insulating layer constituting the multilayer wiring board is preferably formed using a buildup material mainly composed of a thermosetting resin. Specific examples of the material for forming the resin insulating layer include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, and polyimide resins. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used.

  The conductor layer constituting the multilayer wiring board is mainly made of copper, and is formed by a known method such as a subtractive method, a semi-additive method, or a full additive method. Specifically, for example, techniques such as etching of copper foil, electroless copper plating, or electrolytic copper plating are applied. Note that a conductor layer can be formed by etching after forming a thin film by a technique such as sputtering or CVD, or a conductor layer can be formed by printing a conductive paste or the like.

In addition to the IC chip and the chip capacitor, examples of the chip component include electronic components such as a chip resistor and a chip inductor. Examples of the IC chip include an IC chip used as a computer microprocessor, an IC chip such as a DRAM (Dynamic Random Access Memory) and an SRAM (Static Random Access Memory).
In the plating layer forming step, the area ratio of the dummy plating layer in the dummy plating layer forming region defined by the outer edge of the dummy plating layer can be arbitrarily set. For example, it is set to 30% or more and 100% or less. Also good. In this case, it is preferable to form the dummy plating layer so that the distance between the product plating layer and the dummy plating layer is 0.1 mm or more and 10 mm or less. By doing in this way, the current concentration at the time of plating can be avoided more reliably. In addition, when the area ratio of a dummy plating layer is comparatively large, it is good to set the said distance large. On the contrary, when the area ratio of the dummy plating layer is relatively small, the distance is preferably set to be small.
Here, it is assumed that the plurality of chip component connection terminals are a plurality of IC chip connection terminals to which an IC chip as a chip component can be connected. Further, the vertical dimension of the rectangular chip mounting area formed by arranging a plurality of IC chip connection terminals in an array is X (cm) and the horizontal dimension is Y (cm), and product plating is performed on the plurality of IC chip connection terminals. Assume that the design value of the layer thickness is Z (μm). At this time, the standard deviation σ (μm) of the actual measurement value of the thickness of the product plating layer is expressed by the following equation. The design value Z (μm) can also be expressed as an average value (μm) of the thickness of the product plating layer in the plurality of IC chip connection terminals.

Sectional drawing which shows schematic structure of the multilayer wiring board in 1st Embodiment. The top view which shows schematic structure of the multilayer wiring board in 1st Embodiment. Explanatory drawing which shows the manufacturing method of the multilayer wiring board in 1st Embodiment. Explanatory drawing which shows the manufacturing method of the multilayer wiring board in 1st Embodiment. Explanatory drawing which shows the manufacturing method of the multilayer wiring board in 1st Embodiment. Explanatory drawing which shows the manufacturing method of the multilayer wiring board in 1st Embodiment. Explanatory drawing which shows the manufacturing method of the multilayer wiring board in 1st Embodiment. Explanatory drawing which shows the manufacturing method of the multilayer wiring board in 1st Embodiment. Explanatory drawing which shows the manufacturing method of the multilayer wiring board in 1st Embodiment. Explanatory drawing which shows the manufacturing method of the multilayer wiring board in 1st Embodiment. Explanatory drawing which shows the manufacturing method of the multilayer wiring board in 1st Embodiment. Explanatory drawing which shows the manufacturing method of the multilayer wiring board in 1st Embodiment. The graph which shows the measurement result of the thickness variation of the product plating layer in the manufacturing method of 1st Embodiment. The graph which shows the measurement result of the thickness variation of the product plating layer in the manufacturing method of a prior art. The graph which shows the relationship between the size of an IC chip mounting area | region and the thickness variation of a product plating layer in each of the manufacturing method of 1st Embodiment, and the manufacturing method of a prior art. Sectional drawing which shows schematic structure of the multilayer wiring board in 2nd Embodiment. Explanatory drawing which shows the manufacturing method of the multilayer wiring board in 2nd Embodiment. Explanatory drawing which shows the manufacturing method of the multilayer wiring board in 2nd Embodiment. Explanatory drawing which shows the manufacturing method of the multilayer wiring board in 2nd Embodiment.

[First Embodiment]
Hereinafter, a first embodiment in which the present invention is embodied in a multilayer wiring board will be described in detail with reference to the drawings. FIG. 1 is an enlarged cross-sectional view showing a schematic configuration of the multilayer wiring board of the present embodiment, and FIG. 2 is a plan view of the multilayer wiring board as viewed from the upper surface side.

  As shown in FIGS. 1 and 2, the multilayer wiring board 10 of the present embodiment is a coreless wiring board formed without including a core board. The multilayer wiring board 10 includes a plurality of resin insulation layers 20, 21, 22, 23, 24, 25, 26, 27 mainly composed of the same resin insulation material and a plurality of conductor layers 28 made of copper, which are alternately laminated. A multilayered wiring stack 30 is provided. Each of the resin insulating layers 20 to 27 is formed using, for example, a buildup material mainly composed of a thermosetting epoxy resin.

  In the multilayer wiring board 10 of the present embodiment, a plurality of IC chip connection terminals 41 (chip component connection) whose connection target is an IC chip (chip component) are provided on the upper surface 31 side (substrate main surface side) of the wiring laminate 30. Terminals) and a plurality of capacitor connection terminals 42 (chip component connection terminals) whose connection objects are chip capacitors (chip components). On the upper surface 31 side of the wiring laminated portion 30, the plurality of IC chip connection terminals 41 are arranged in an array in a chip mounting region 43 provided at the center of the substrate. The capacitor connection terminal 42 is a connection terminal having a larger area than the IC chip connection terminal 41, and is disposed on the outer peripheral side of the chip mounting region 43. As shown in FIG. 2, the chip mounting area 43 of this embodiment is a rectangular chip mounting area 43 having a vertical dimension of X (cm) and a horizontal dimension of Y (cm).

  The plurality of IC chip connection terminals 41 and the plurality of capacitor connection terminals 42 are projected on the outermost resin insulation layer 27. The IC chip connection terminal 41 and the capacitor connection terminal 42 are mainly composed of a copper layer, and the upper surface and side surfaces of the copper layer are covered with a plating layer 46 (specifically, a nickel-gold plating layer) other than copper. Have a structure.

  On the other hand, a plurality of mother board connection terminals 45 whose connection target is a mother board (mother board) are arranged in an array on the lower surface 32 side (substrate rear face side) of the wiring laminated portion 30. These mother board connection terminals 45 are connection terminals having a larger area than the IC chip connection terminal 41 and the capacitor connection terminal 42 on the upper surface 31 side.

  A plurality of openings 37 are formed in the outermost resin insulation layer 20 on the lower surface 32 side of the wiring laminated portion 30, and a mother board connection terminal 45 is arranged corresponding to the plurality of openings 37. Specifically, the mother board connection terminal 45 is disposed in the opening 37 such that the height of the outer surface of the terminal is lower than the surface of the resin insulating layer 20, and the outer peripheral portion of the outer surface of the terminal is the outermost layer. The resin insulation layer 20 is covered. The mother board connection terminal 45 is mainly composed of a copper layer, and only the lower surface of the copper layer exposed in the opening 37 is covered with a plating layer 48 (specifically, a nickel-gold plating layer) other than copper. It has a covered structure.

  The resin insulating layers 21 to 27 are provided with via holes 33 and filled via conductors 34, respectively. Each via conductor 34 has a shape whose diameter is increased in the same direction (from the lower surface side to the upper surface side in FIG. 1), and each conductor layer 28, IC chip connection terminal 41, capacitor connection terminal 42, and mother The board connection terminals 45 are electrically connected to each other.

  The multilayer wiring board 10 having the above configuration is manufactured, for example, by the following procedure.

  First, a support substrate 50 (such as a glass epoxy substrate) having sufficient strength is prepared, and the resin insulating layers 20 to 27 and the conductor layer 28 are built up on the support substrate 50 to form the wiring laminated portion 30.

  More specifically, as shown in FIG. 3, a base resin insulating layer 51 is formed by attaching a sheet-like insulating resin base material made of epoxy resin on the support substrate 50, whereby the support substrate 50 and the base resin are formed. A base material 52 made of the insulating layer 51 is obtained. Then, the laminated metal sheet body 54 is disposed on the upper surface of the base resin insulating layer 51 of the base material 52. Here, by arranging the laminated metal sheet body 54 on the base resin insulating layer 51, the adhesiveness to the extent that the laminated metal sheet body 54 is not peeled off from the base resin insulating layer 51 in the subsequent manufacturing process is ensured. The laminated metal sheet body 54 is formed by closely attaching two copper foils 55 and 56 in a peelable state. Specifically, the laminated metal sheet body 54 in which the copper foil 55 and the copper foil 56 are disposed is formed through metal plating (for example, chromium plating, nickel plating, titanium plating, or a composite plating thereof).

Next, on the base material 52, the sheet-like resin insulation layer 20 is disposed so as to wrap the laminated metal sheet body 54, and the resin insulation layer 20 is attached. Here, the resin insulating layer 20 is in close contact with the laminated metal sheet body 54, and in close contact with the base resin insulating layer 51 in the peripheral region of the laminated metal sheet body 54, thereby sealing the laminated metal sheet body 54 ( (See FIG. 4). Then, for example, by performing laser processing using an excimer laser, a UV laser, a CO ₂ laser, or the like, an opening 37 that exposes a part of the copper foil 55 is formed at a predetermined position of the resin insulating layer 20. Thereafter, electroless copper plating is performed to form a whole plating layer covering the opening 37 and the resin insulating layer 20.

  Then, a dry film for forming a plating resist is laminated on the upper surface of the resin insulating layer 20, and the plating resist is formed on the resin insulating layer 20 by exposing and developing the dry film. Thereafter, electrolytic copper plating was selectively performed in the state where the plating resist was formed, thereby forming the metal conductor portion 58 on the copper foil 55 of the laminated metal sheet body 54 and forming the conductor layer 28 on the resin insulating layer 20. Thereafter, the plating resist is removed (see FIG. 5). Further, the entire plating layer covering the resin insulating layer 20 exposed by peeling of the plating resist is removed.

The sheet-like resin insulation layer 21 is disposed on the upper surface of the resin insulation layer 20 on which the metal conductor portion 58 and the conductor layer 28 are formed, and the resin insulation layer 21 is attached. Then, via holes 33 are formed at predetermined positions (positions above the metal conductor portions 58) of the resin insulating layer 21 by performing laser processing using, for example, excimer laser, UV laser, CO ₂ laser, or the like. Next, a desmear process is performed to remove smear in each via hole 33 using an etching solution such as a potassium permanganate solution. As the desmear process, in addition to treatment with an etchant, for example it may perform processing of plasma ashing using O ₂ plasma.

  After the desmear process, via conductors 34 are formed in the via holes 33 by performing electroless copper plating and electrolytic copper plating according to a conventionally known method. Further, the conductor layer 28 is patterned on the resin insulating layer 21 by performing etching by a conventionally known method (for example, semi-additive method) (see FIG. 6).

  The other resin insulating layers 22 to 27 and the conductor layer 28 are also formed by the same method as the resin insulating layer 21 and the conductor layer 28 described above, and are laminated on the resin insulating layer 21. Then, a via hole 33 is formed by laser drilling the outermost resin insulation layer 27 (see FIG. 7). Next, a desmear process is performed to remove smear in each via hole 33 using an etching solution such as a potassium permanganate solution. Further, electroless copper plating is performed to form a whole plating layer covering the inside of the via hole 33 of the resin insulating layer 27 and the resin insulating layer 27.

  Then, a dry film for forming a plating resist is laminated on the upper surface of the resin insulating layer 27, and the plating resist is formed on the resin insulating layer 27 by exposing and developing the dry film. Thereafter, electrolytic copper plating is selectively performed with the plating resist formed (plating layer forming step). As a result, as shown in FIG. 8, the via conductor 34 is formed in the via hole 33 of the resin insulating layer 27, and the copper chip of the IC chip connection terminal 41 and the capacitor connection terminal 42 is formed on the via conductor 34. A plating layer 61 is formed. Further, a dummy plating layer 62 is formed around the product plating layer 61. Thereafter, the entire plating layer is removed while leaving the product plating layer 61 and the dummy plating layer 62 on the upper surface of the resin insulating layer 27. In addition to the connection terminals connected to the inner conductor layer 28 via the via conductors 34, the IC chip connection terminals 41 include connection terminals that are not connected to the inner conductor layer. Although only the IC chip connection terminal 41 connected to the via conductor 34 is shown in FIG. 8, the IC chip connection terminal 41 not connected to the via conductor 34 is also present in the chip mounting region 43 on the resin insulating layer 27. Is formed.

As shown in FIG. 9, the dummy plating layer 62 of the present embodiment has an IC chip connection terminal 41 formation region (chip mounting region 43) and a capacitor connection terminal 42 formation region on the upper surface of the resin insulation layer 27. It is formed as a conductor layer of a plain pattern (solid pattern) so as to cover almost the entire surface except for the above. Here, the area ratio of the product plating layer 61 (IC chip connection terminal 41 and capacitor connection terminal 42) to the surface of the resin insulating layer 27 (the upper surface 31 serving as the main surface of the substrate) is about 7%. The dummy plating layer 62 is formed so that the area ratio of the entire plating layer obtained by adding the dummy plating layer 62 to 90% or more.
After the plating layer forming step, a heat treatment may be performed on the resin surface of the outermost resin insulation layer 27 by applying hot air of, for example, 180 ° C. from above. When this heat treatment is performed, the resin surface of the exposed resin insulating layer 27 is discolored. On the other hand, the resin surface of the resin insulating layer 27 covered with the dummy plating layer 62 is not discolored. Therefore, for example, if a predetermined pattern shape is provided in the dummy plating layer 62, a difference in color shading according to the pattern shape can be generated on the resin surface. Since the heat treatment at this stage also serves as annealing, there is an advantage that the internal stress applied to the product plating layer 61 can be released while the resin insulating layer 27 is cured.

  By performing the build-up process described above, the wiring laminate 60 is formed by laminating the laminated metal sheet body 54, the resin insulating layers 20 to 27, the conductor layer 28, the product plating layer 61, and the dummy plating layer 62 on the base material 52. Is done.

  Then, a dry film for forming an etching resist is laminated on the upper surface of the wiring laminate 60, and the dry film is exposed and developed to thereby etch the etching resist 65 (FIG. 10) so as to cover the surface of the product plating layer 61. (Refer forming step).

  After the etching resist 65 is formed, the wiring laminate 60 is cut by a dicing device (not shown), and the peripheral region of the portion that becomes the wiring laminate 30 is removed. By this cutting, the outer edge portion of the laminated metal sheet 54 sealed with the resin insulating layer 20 is exposed. That is, due to the removal of the surrounding region, the close contact portion between the base resin insulation layer 51 and the resin insulation layer 20 is lost. As a result, the wiring laminated portion 30 and the base material 52 are connected via the laminated metal sheet body 54 only.

  Here, as shown in FIG. 11, the substrate 52 is removed from the wiring laminated portion 30 by peeling at the interface between the pair of copper foils 55 and 56 in the laminated metal sheet body 54. The copper foil 55 on the lower surface 32 is exposed (base material separation step).

  Thereafter, the dummy laminated layer 62 exposed on the upper surface 31 side of the wiring laminated portion 30 is removed by etching the wiring laminated portion 30 (plating layer removing step). At the same time, the copper foil 55 exposed on the lower surface 32 side of the wiring laminated portion 30 is removed as a whole, and a part of the lower side of the metal conductor portion 58 is removed. As a result, the opening 37 is formed in the resin insulating layer 24 and the metal conductor 58 remaining in the opening 37 becomes the mother board connection terminal 45 (see FIG. 12).

  Further, the etching resist 65 formed on the upper surface 31 of the wiring laminated portion 30 is removed. Thereafter, electroless nickel plating and electroless gold plating are sequentially performed on the surface of the IC chip connection terminal 41, the surface of the capacitor connection terminal 42, and the surface of the mother board connection terminal 45. As a result, plating layers 46 and 48 are formed on the surfaces of the connection terminals 41, 42 and 45. The multilayer wiring board 10 of FIG. 1 is manufactured through the above steps.

  In the multilayer wiring board 10 manufactured as described above, the inventors measured the thickness variation of each product plating layer 61 in the IC chip connection terminal 41 and the capacitor connection terminal 42 formed on the substrate main surface 31 side. . The result is shown in FIG. Moreover, the thickness variation of each product plating layer 61 was measured also in the case of the conventional manufacturing method in which the product plating layer 61 was formed without forming the dummy plating layer 62. The result is shown in FIG. Here, the thickness variation of the four measurement locations P1 to P4 was measured.

  Specifically, the first measurement location P1 is the product plating layer 61 of the IC chip connection terminal 41 that is not connected to the via conductor 34 in the outer periphery of the chip mounting region 43, and the second measurement location P2 is This is a product plating layer 61 of the IC chip connection terminal 41 connected to the via conductor 34 at the outer periphery of the chip mounting region 43. The third measurement location P3 is the product plating layer 61 of the IC chip connection terminal 41 in the center of the chip mounting region 43, and the fourth measurement location P4 is the product plating layer 61 of the capacitor connection terminal 42. . In addition, about the 1st-3rd measurement location P1-P3, thickness variation is measured about the product plating layer 61 of 60 IC chip connection terminals 41. FIG. Further, at the fourth measurement location, thickness variations were measured for the product plating layers 61 of the 48 capacitor connection terminals 42.

  As shown in FIG. 14, in the conventional manufacturing method, since the dummy plating layer 62 is not formed, the thickness variation of each product plating layer 61 becomes large. Specifically, the average value of the plating thickness at the first measurement location P1 was 24.72 μm, and the standard deviation was 2.50. The average value of the plating thickness at the second measurement location P2 was 20.99 μm, and the standard deviation was 5.20. The average value of the plating thickness at the third measurement location P3 was 10.08 μm, and the standard deviation was 2.31. The average value of the plating thickness at the fourth measurement location P4 was 36.58 μm, and the standard deviation was 8.92.

  As described above, in each product plating layer 61 (measurement points P1 to P3) to be the IC chip connection terminal 41, the thickness varies depending on the presence or absence and the formation position of the via conductor 34 to be connected. Further, the product plating layer 61 (measurement location P4) to be the capacitor connection terminal 42 is provided in a scattered manner on the outer peripheral side of the main surface of the substrate, so that current concentration tends to occur. For this reason, the plating thickness of the product plating layer 61 is relatively thick, and the thickness variation is also large.

  On the other hand, as shown in FIG. 13, in the manufacturing method of the present embodiment, the thickness variation of each product plating layer 61 is reduced. Specifically, the average value of the plating thickness at the first measurement location P1 was 12.85 μm, and the standard deviation was 1.16. The average value of the plating thickness at the second measurement location P2 was 12.51 μm, and the standard deviation was 1.53. The average value of the plating thickness at the third measurement location P3 was 12.90 μm, and the standard deviation was 1.47. The average value of the plating thickness at the fourth measurement location P4 was 12.51 μm, and the standard deviation was 1.21. Thus, by providing the dummy plating layer 62 around the product plating layer 61, the thickness variation of each product plating layer 61 could be suppressed.

これに対して、ダミーめっき層６２を形成せずに、製品めっき層６１のみを形成した従来の製造方法にて多層配線基板１０をいくつか作製した。そして、同様の方法により、製品めっき層６１の厚さ（μｍ）を、ＩＣチップ搭載領域４３のコーナー部と中央部とにおいて各々５ポイント測定し、製品めっき層６１の厚さの実測値の標準偏差σ（μｍ）を求めた。その結果も図１５のグラフに示す。それによると、従来の製造方法による場合には、明らかに標準偏差σの値が大きくなり、厚さバラツキが増大することがわかった。ゆえに、これらについては上記関係式を満たさないものとなった。
従って、本実施の形態によれば、以下の効果を得ることができる。 Furthermore, the present inventors performed the following in order to investigate the relationship between the size of the IC chip mounting region 43 and the thickness variation of the product plating layer 61. Here, the size of the IC chip mounting area 43 was changed (that is, the values of X and Y were changed), and several multilayer wiring boards 10 were produced by the manufacturing method of the first embodiment. In addition, the design value of the thickness of the product plating layer 61 in the IC chip connection terminal 41 formed on the substrate main surface 31 side is Z (μm). More specifically, the product plating layer 61 was formed with Z = 15 μm. Further, the area ratio of the dummy plating layer 62 occupying the dummy plating layer forming region is set within a range of 30% to 100%, and the distance between the product plating layer 61 and the dummy plating layer 62 is 0.1 mm to 10 mm. Set within the range. Then, the thickness (μm) of the product plating layer 61 was measured at 5 points each at the corner and the center of the IC chip mounting region 43. The standard deviation σ (μm) of the actually measured value of the thickness of the product plating layer 61 at this time was determined. The result is shown in the graph of FIG. Incidentally, in the graph of FIG. 15, the vertical axis is the standard deviation σ, and the horizontal axis is half the length of the diagonal line of the IC chip mounting area 43 (in other words, the separation distance between the corner portion and the central portion of the IC chip mounting area 43). It has become.
As shown in FIG. 15, in the multilayer wiring board 10 manufactured by the manufacturing method of the first embodiment, the value of the standard deviation σ is the following relational expression regardless of the size of the IC chip mounting region 43. It became clear to satisfy.

On the other hand, several multilayer wiring boards 10 were produced by a conventional manufacturing method in which only the product plating layer 61 was formed without forming the dummy plating layer 62. Then, by the same method, the thickness (μm) of the product plating layer 61 is measured at each of five points at the corner and the center of the IC chip mounting region 43, and the standard of the actual measurement value of the thickness of the product plating layer 61 is measured. Deviation σ (μm) was determined. The results are also shown in the graph of FIG. According to this, it was found that when the conventional manufacturing method is used, the value of the standard deviation σ is clearly increased and the thickness variation increases. Therefore, these do not satisfy the above relational expression.
Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the present embodiment, on the upper surface 31 of the multilayer wiring board 10, in addition to the product plating layer 61 to be the IC chip connection terminal 41 and the capacitor connection terminal 42, the dummy plating layer 62 is provided around the product plating layer 61. Is formed. In this case, the area ratio of the plating layers 61 and 62 on the upper surface 31 of the multilayer wiring board 10 can be increased, the concentration of the plating current is avoided, and the thickness variation of the product plating layer 61 is eliminated. As a result, a plurality of IC chip connection terminals 41 and a plurality of capacitor connection terminals 42 can be formed with a uniform thickness in the multilayer wiring board 10. Therefore, if the multilayer wiring board 10 is used, the connection reliability between the IC chip and the chip capacitor and the connection terminals 41 and 42 can be improved.

  (2) In this embodiment, after forming an etching resist so as to cover the product plating layer 61 in the resist formation step, the dummy plating layer is removed by etching in the plating layer removal step. In this case, only the product plating layer 61 to be the connection terminals 41 and 42 remains on the upper surface of the multilayer wiring board 10. For this reason, the plating layer 46 for improving solder wettability can be reliably formed only on the surface of the product plating layer 61. Further, since the dummy plating layer 62 is removed, a problem that an IC chip or a chip capacitor is erroneously connected to the dummy plating layer 62 is also avoided.

  (3) In the present embodiment, the plating layer removal step is performed after the base material separation step. In this case, the copper foil 55 on the lower surface 32 side can be removed by etching at the same time as the dummy plating layer 62 on the upper surface 31 side of the multilayer wiring substrate 10 is removed by etching. For this reason, the multilayer wiring board 10 can be manufactured with the same man-hour as the conventional manufacturing method, and manufacturing cost can be suppressed low.

(4) In this embodiment, the area ratio of the product plating layer 61 of the IC chip connection terminal 41 and the capacitor connection terminal 42 with respect to the upper surface 31 of the resin insulating layer 27 is about 7%, and the area ratio of the product plating layer 61 is Relatively small. For this reason, the dummy plating layer 62 having a large area is formed such that the area ratio of the plating layer on the upper surface 31 of the resin insulating layer 27 is 90% or more. In this case, the dummy plating layer 62 is provided so as to have an area ratio 10 times or more that of the product plating layer 61. In this way, concentration of the plating current can be surely avoided, and the product plating layer 61 of each connection terminal 41, 42 can be formed with a uniform thickness.
[Second Embodiment]

  Hereinafter, a second embodiment in which the present invention is embodied in a multilayer wiring board will be described in detail with reference to the drawings. FIG. 16 is an enlarged cross-sectional view showing a schematic configuration of the multilayer wiring board of the present embodiment. In the first embodiment, the coreless wiring substrate is formed without including the core substrate. In the present embodiment, the coreless wiring substrate is embodied in a multilayer wiring substrate having the core substrate.

  As shown in FIG. 16, the multilayer wiring substrate 100 of the present embodiment includes a rectangular plate-shaped core substrate 101, a first buildup layer 111 formed on the core main surface 102 of the core substrate 101, a core The second buildup layer 112 is formed on the core back surface 103 of the substrate 101.

  The core substrate 101 according to the present embodiment is made of, for example, a resin insulating material (glass epoxy material) obtained by impregnating a glass cloth as a reinforcing material with an epoxy resin. In the core substrate 101, a plurality of through-hole conductors 106 are formed so as to penetrate the core main surface 102 and the core back surface 103. Note that the inside of the through-hole conductor 106 is filled with a closing body 107 such as an epoxy resin. Further, a conductor layer 121 made of copper is patterned on the core main surface 102 and the core back surface 103 of the core substrate 101, and each conductor layer 121 is electrically connected to the through-hole conductor 106.

  The first buildup layer 111 formed on the core main surface 102 of the core substrate 101 includes three resin insulating layers 133, 135, and 137 made of thermosetting resin (epoxy resin), and a conductor layer 122 made of copper. Are alternately stacked. On the upper surface 141 (substrate main surface) of the outermost resin insulation layer 137, as in the first embodiment, a plurality of IC chip connection terminals 41 (chip component connection terminals) are arranged in an array at the center of the substrate. A plurality of capacitor connection terminals 42 (chip component connection terminals) are disposed outside the IC chip connection terminals 41. These IC chip connection terminal 41 and capacitor connection terminal 42 are mainly composed of a copper layer, and have a structure in which the upper surface and side surfaces of the copper layer are covered with a plating layer 46. In addition, via holes 33 and filled via conductors 34 are formed in the resin insulating layers 133, 135, and 137, respectively. Each via conductor 34 is electrically connected to the conductor layers 121 and 122 and the connection terminals 41 and 42.

  The second buildup layer 112 formed on the core back surface 103 of the core substrate 101 has substantially the same structure as the first buildup layer 111 described above. That is, the second buildup layer 112 has a structure in which three resin insulating layers 134, 136, 138 and the conductor layer 122 are alternately stacked. On the lower surface 142 (substrate back surface) of the outermost resin insulation layer 138, a plurality of mother substrate connection terminals 45 are formed. These mother board connection terminals 45 are mainly composed of a copper layer, and have a structure in which the lower and side surfaces of the copper layer are covered with a plating layer 48. Also, via holes 33 and via conductors 34 are formed in the resin insulating layers 134, 136, and 138. Each via conductor 34 is electrically connected to the conductor layers 121 and 122 and the connection terminal 45.

  Next, a method for manufacturing the multilayer wiring board 100 of the present embodiment will be described.

  First, a copper clad laminate in which a copper foil is pasted on both sides of a substrate made of glass epoxy is prepared. And a drilling process is performed using a drill machine, and the through-hole (illustration omitted) which penetrates the front and back of a copper clad laminated board is previously formed in the predetermined position. And the through-hole conductor 106 is formed in a through-hole by performing the electroless copper plating and the electrolytic copper plating with respect to the inner surface of the through-hole of a copper clad laminated board. Thereafter, the cavity of the through-hole conductor 106 is filled with an insulating resin material (epoxy resin) to form a closing body 107.

  Furthermore, after performing electroless copper plating and electrolytic copper plating to form a copper plating layer on the surface of the copper-clad laminate including the exposed portion of the closure body 107, the copper plating layer and the copper foil are subjected to, for example, a subtractive method. To pattern. As a result, as shown in FIG. 17, the core substrate 101 on which the conductor layer 121 and the through-hole conductor 106 are formed is obtained.

  Then, by performing the same build-up process as in the first embodiment, the first build-up layer 111 is formed on the core main surface 102 of the core substrate 101 and the core back surface 103 of the core substrate 101 is formed. A second buildup layer 112 is also formed thereon. At this time, a product plating layer 61 to be the connection terminals 41 and 42 is formed on the upper surface 141 of the resin insulating layer 137 to be the outermost layer of the first buildup layer 111 and a dummy plating layer is provided around the product plating layer 61. 62 is formed (see FIG. 18). In this step, a product plating layer 61 to be the mother board connection terminal 45 is formed on the lower surface 142 of the resin insulating layer 138 which is the outermost layer of the second buildup layer 112 and a dummy is also formed around the product plating layer 61. A plating layer 62 is formed (see FIG. 18).

  Thereafter, a dry film for forming an etching resist is laminated on the surface of the first buildup layer 111 (the upper surface 141 of the resin insulating layer 137), and the dry film is exposed and developed, whereby the product plating layer 61 is formed. An etching resist 65 covering the surface is formed (see FIG. 19). Further, by laminating a dry film for forming an etching resist on the surface of the second buildup layer 112 (the lower surface 142 of the resin insulating layer 138), and exposing and developing the dry film, An etching resist 65 covering the surface is formed (see FIG. 19).

  Etching is performed after the formation of the etching resist 65 to remove the dummy plating layer 62 exposed on the surfaces of the build-up layers 111 and 112, and then the etching resist 65 is removed. Then, electroless nickel plating and electroless gold plating are sequentially performed on the surface of the IC chip connection terminal 41, the surface of the capacitor connection terminal 42, and the surface of the mother board connection terminal 45. As a result, plating layers 46 and 48 are formed on the surfaces of the connection terminals 41, 42 and 45. The multilayer wiring board 100 of FIG. 16 is manufactured through the above steps.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) Also in the present embodiment, on the upper surface 141 of the resin insulating layer 137, in addition to the product plating layer 61 to be the IC chip connection terminal 41 and the capacitor connection terminal 42, the dummy plating layer 62 is provided around the product plating layer 61. Is formed. In this case, the area ratio of the plating layers 61 and 62 on the upper surface 141 of the resin insulating layer 137 can be increased, the concentration of the plating current is avoided, and the thickness variation of the product plating layer 61 is eliminated. As a result, in the multilayer wiring board 100, the plurality of IC chip connection terminals 41 and the plurality of capacitor connection terminals 42 can be formed with a uniform thickness. Therefore, if the multilayer wiring substrate 100 is used, the connection reliability between the IC chip and chip capacitor chip components and the connection terminals 41 and 42 can be improved.

  (2) In the present embodiment, the dummy plating layer 62 is formed around the product plating layer 61 to be the mother board connection terminal 45 on the lower surface 142 of the resin insulating layer 138. In this way, concentration of the plating current can be avoided, and variation in the thickness of the product plating layer 61 of each connection terminal 45 can be suppressed. As a result, in the multilayer wiring board 100, the plurality of mother board connection terminals 45 can be formed with a uniform thickness, and the connection reliability with the mother board connection terminals 45 can be improved.

  In addition, you may change embodiment of this invention as follows.

  In the above embodiments, the dummy plating layer 62 is removed by etching, but the multilayer wiring boards 10 and 100 may be completed with the dummy plating layer 62 left. In this case, since the dummy plating layer 62 is not electrically connected to the conductor layers 28 and 122 on the inner layer side, the electrical performance of the multilayer wiring boards 10 and 100 does not deteriorate even if the dummy plating layer 62 exists. In addition, since the multilayer wiring boards 10 and 100 are configured to include the dummy plating layer 62 having a relatively large area, heat dissipation can be improved. Furthermore, in the multilayer wiring board 10 having no core like the multilayer wiring board 10 of the first embodiment, the board strength is weak, but the provision of the dummy plating layer 62 can increase the board strength. . As a result, warpage of the multilayer wiring board 10 can be suppressed.

  In each of the above embodiments, the IC chip connection terminal 41 and the capacitor connection terminal 42 are provided as the chip component connection terminals on the upper surfaces 31 and 141 of the multilayer wiring boards 10 and 100, but the capacitor connection terminal 42 is omitted. However, only the IC chip connection terminal 41 may be formed. In addition to the IC chip connection terminal 41 and the capacitor connection terminal 42, other chip component connection terminals for mounting chip components such as chip inductors may be provided on the upper surfaces 31 and 141 of the multilayer wiring boards 10 and 100. Good.

  In each of the above embodiments, on the upper surfaces 31 and 141 of the multilayer wiring boards 10 and 100, in addition to the product plating layer 61 that becomes the IC chip connection terminal 41, the product plating layer 61 that becomes the capacitor connection terminal 42 is also provided around the product plating layer 61. Although the dummy plating layer 62 is formed, it is not limited to this. For example, chip capacitors can be connected even if the capacitor connection terminal 42 has a thickness variation, and the IC chip connection terminal 41 is more problematic than the capacitor connection terminal 42 in terms of the thickness variation of the connection terminals. Therefore, in the plating layer forming step, the dummy plating layer 62 is formed only around the product plating layer 61 to be the IC chip connection terminal 41, and the dummy plating layer 62 is formed around the product plating layer 61 to be the capacitor connection terminal 42. Avoid forming. Even in this case, the thickness variation of the IC chip connection terminal 41 can be suppressed, and the connection reliability with the IC chip can be sufficiently secured.

  In each of the above embodiments, the dummy plating layer 62 formed in the plating layer forming step is a solid pattern that does not have a mesh, but is not limited thereto. For example, a plain dummy plating layer 62 having a mesh may be formed 7. Thus, by forming the plain dummy plating layer 62 having a mesh, the area ratio of the plating layer can be adjusted more accurately.

  In each of the above embodiments, the connection terminals 41 and 42 having the same thickness as the inner conductor layers 28 and 122 (thickness of about 10 μm) are formed. However, the present invention is not limited to this. is not. For example, post-shaped connection terminals (post electrodes) that are thicker than the inner conductor layers 28 and 122 and have a thickness of, for example, 30 μm or more may be formed. Even when a relatively thick connection terminal is formed in this way, each connection terminal can be formed with a uniform thickness by forming the dummy plating layer 62.

  In each of the above embodiments, the product plating layer 61 and the dummy plating layer 62 are formed by copper plating, but the product plating layer 61 and the dummy plating layer 62 are formed by other plating such as tin plating or nickel plating. May be. However, when the product plating layer 61 and the dummy plating layer 62 are formed by copper plating, the electrical resistance of the IC chip connection terminal 41 and the capacitor connection terminal 42 can be kept low, which is practically preferable.

  Next, in addition to the technical ideas described in the claims, the technical ideas grasped by the respective embodiments described above are listed below.

  (1) In the means 1, a plurality of IC chip connection terminals to which an IC chip can be connected and a plurality of capacitor connection terminals to which a chip capacitor can be connected are provided on the main surface of the substrate as the chip component connection terminals. A method for manufacturing a multilayer wiring board.

  (2) In the method 1, the method of manufacturing a multilayer wiring board, wherein the dummy plating layer is a plain pattern.

  (3) The method for manufacturing a multilayer wiring board according to means 1, wherein the dummy plating layer is a plain pattern having a mesh.

  (4) The method for manufacturing a multilayer wiring board according to means 1, wherein the dummy plating layer has a pattern corresponding to the shape and size of the adjacent product plating layer.

  (5) A method for manufacturing a multilayer wiring board according to means 1, wherein in the plating layer forming step, a filled via connected to the conductor layer on the inner layer side and the chip component connection terminal is formed simultaneously with the plating layer.

  (6) Manufacturing the multilayer wiring board characterized in that, in the means 1, in the plating layer forming step, the dummy plating layer is formed so that the dummy plating layer has an area ratio of 10 times or more of the product plating layer. Method.

  (7) The method for manufacturing a multilayer wiring board according to means 1, wherein the product plating layer and the dummy plating layer are formed by copper plating.

  (8) The method for manufacturing a multilayer wiring board according to means 1, wherein the resin insulation layer is formed using a build-up material mainly composed of a thermosetting resin.

DESCRIPTION OF SYMBOLS 10,100 ... Multilayer wiring board 20-27, 133-138 ... Resin insulation layer 28, 122 ... Conductor layer 31,141 ... Upper surface as a substrate main surface 32, 142 ... Lower surface as a substrate back surface 41 ... As a chip component connection terminal IC chip connection terminal 42 ... Capacitor connection terminal 52 as a chip component connection terminal 52 ... Support base material 55 ... Copper foil as metal foil 61 ... Product plating layer 62 ... Dummy plating layer 65 ... Etching resist

Claims (6)

The substrate has a main surface and a back surface, and has a structure in which a plurality of resin insulation layers and a plurality of conductor layers are laminated, and a plurality of chip component connection terminals to which chip components can be connected are arranged on the substrate main surface. A manufacturing method of a multilayer wiring board provided,
On the surface of the resin insulating layer of the outermost layer exposed at the substrate main surface, around the plurality of chip parts connecting terminals and a group of forming a product plating layer ing, or One group of the product plating layer A method of manufacturing a multilayer wiring board comprising a plating layer forming step of forming a dummy plating layer. On the substrate main surface side, a resist forming step of forming an etching resist so as to cover the product plating layer;
The method for manufacturing a multilayer wiring board according to claim 1, further comprising a plating layer removing step of removing the dummy plating layer exposed on the substrate main surface side by etching.   3. The multilayer according to claim 1, wherein in the plating layer forming step, the dummy plating layer is formed so that an area ratio of the plating layer to a surface area of the substrate main surface is 60% or more and 95% or less. A method for manufacturing a wiring board. A laminating step of laminating the plurality of resin insulation layers and the plurality of conductor layers via a metal foil on a supporting substrate;
A base material separation step of separating the metal foil and the support base material to expose the metal foil on the back side of the substrate,
The plating layer removing step is performed after the base material separating step, and the dummy plating layer on the substrate main surface side is removed by etching, and at the same time, the metal foil on the back surface side of the substrate is removed by etching. A method for manufacturing a multilayer wiring board according to claim 2 or 3.   In the plating layer forming step, when the area ratio of the dummy plating layer in the dummy plating layer forming region defined by the outer edge of the dummy plating layer is 30% or more and 100% or less, the product plating layer and the dummy plating 5. The method for manufacturing a multilayer wiring board according to claim 1, wherein the dummy plating layer is formed so that a distance from the layer is 0.1 mm or more and 10 mm or less. The plurality of chip component connection terminals are a plurality of IC chip connection terminals to which an IC chip as the chip component can be connected, and a rectangular chip mounting in which the plurality of IC chip connection terminals are arranged in an array When the vertical dimension of the region is X (cm) and the horizontal dimension is Y (cm), and the design value of the thickness of the product plating layer in the plurality of IC chip connection terminals is Z (μm), the product plating 6. The method for manufacturing a multilayer wiring board according to claim 5, wherein the standard deviation σ (μm) of the actually measured value of the layer thickness is expressed by the following formula.

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