JP5691311B2 - Save processing device, save processing method, and save processing program - Google Patents

Description

  The present invention relates to an evacuation processing apparatus, for example, an evacuation processing apparatus that shortens the processing time required for backup processing when a power failure occurs in a RAID apparatus.

  RAID (Redundant Arrays of Independent (Inexpensive) Disks) is widely known as a technique for combining a plurality of HDDs (Hard Disk Drives) and constructing a disk system excellent in high speed, large capacity, and high reliability.

  Generally, in a RAID device, user data is read / written using a cache memory in order to reduce processing time required for data access from a host device (for example, a host computer, hereinafter referred to as a host). Yes.

  As the cache memory, a semiconductor storage device such as a DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) is usually used.

  When the RAID device receives a user data read request from the host, the RAID device retrieves the user data from a cache memory (hereinafter simply referred to as a cache) and acquires the user data corresponding to the read request. Notify the host of the data.

  On the other hand, when user data is not acquired from the cache, user data stored in a hard disk device (hereinafter simply referred to as a disk) is acquired and written to the cache.

  When a user data write request is received, the host is notified of the completion of the write process when the user data is stored in the cache. Thereafter, when a predetermined condition is satisfied, the user data stored in the cache is stored in the disk.

  By the way, since the cache described above uses a volatile semiconductor storage device, the user data in the cache is erased if the power supply to the cache is lost. For this reason, when a power failure occurs, it is necessary to back up all data on the cache in a non-volatile storage device (eg, NAND flash, compact flash (registered trademark), etc.).

  For example, as shown in FIG. 14, when a power failure occurs, the RAID device 20 saves the cache data 24a stored in the cache 24 in the NAND flash 23 without distinguishing between read data and write data.

In addition, when a power failure occurs, the power supply to the RAID device 20 is changed to PSU (Power Supply).
The unit 20 is switched to a system capacity unit (SCU) 27, and the RAID device 20 performs the above-described saving process using the power stored in the SCU 27.

  Based on a technique for efficiently performing a write-back (writing of write data to a hard disk) at the time of a power failure and saving power at the time of the power failure (for example, refer to Patent Document 1) and access information of the disk. A technique for relocating a logical disk device to a physical disk device is known (see, for example, Patent Document 2).

JP-A-9-330277 JP 2006-59374 A

  However, in the above-described conventional technology, all cache data is targeted for backup, and backup processing may take longer than necessary.

  For example, in the situation where a large amount of cache data 24a is stored in the cache 24 shown in FIG. 14, if a power failure occurs in the RAID device 20, the backup processing may take more processing time than necessary. It was.

  In this case, within the power supply time of the SCU 27, saving of the cache data 24a to the NAND flash 23 may not be completed, and some cache data may be lost.

  The disclosed technique has been made in view of the above, and an object thereof is to provide an evacuation processing apparatus or the like that shortens the processing time required for backup.

In view of the above-described conventional problems, the present technology, when storing data in the cache memory, according to the type of data, information on whether or not the data is saved in the nonvolatile memory, and saving of the data saved in the nonvolatile memory Management means for storing information for determining priority in the management table, information on whether or not the data is saved in the nonvolatile memory and data saved in the nonvolatile memory when a power failure occurs based on the information for determining the priority of saving the data to be saved in non-volatile memory of the data stored in the cache memory, in order from the highest priority data to lower priority data according to the priority And a power failure processing unit that executes a process of writing in the nonvolatile memory.

  According to the present technology, it is possible to shorten the processing time required for the backup of the cache memory in the event of a power failure and to improve the backup speed.

It is a functional block diagram which shows the structure of the RAID apparatus shown to this Embodiment. It is a figure which shows an example of the data structure of the NAND flash of this Embodiment. It is a figure which shows an example of the data structure of the cache memory shown in this Embodiment. It is a functional block diagram which shows the structure of FPGA shown in this Embodiment. It is a figure which shows an example of the data structure of the backup management table shown to this Embodiment. It is a figure which shows an example of the data structure of the bad block management table shown to this Embodiment. It is a figure which shows an example of the data structure of the backup completion flag shown in this Embodiment. 6 is a flowchart showing processing during energization in the save processing device of the present embodiment. It is a flowchart which shows the process at the time of a power failure in the evacuation processing apparatus of this Embodiment. It is explanatory drawing explaining the process at the time of a power failure in the evacuation processing apparatus of this Embodiment. It is explanatory drawing explaining the process at the time of a power failure in the evacuation processing apparatus of this Embodiment. It is explanatory drawing explaining the process at the time of a power failure in the evacuation processing apparatus of this Embodiment. It is explanatory drawing explaining the process at the time of a power failure in the evacuation processing apparatus of this Embodiment. It is a figure for demonstrating a prior art.

  Hereinafter, embodiments of a save processing device, a save processing method, and a storage system disclosed in the present application will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

  Next, the RAID device (Redundant Arrays of Independent (Inexpensive) Disks) shown in the present embodiment will be described. FIG. 1 is a functional block diagram showing a configuration of the RAID device shown in the present embodiment.

  In FIG. 1, a RAID device 200 is stored in an HDD (Hard Disk Drive) in response to requests from a plurality of host devices (for example, host computers A, B, C... Various user data and program data are transmitted. Further, when a power failure occurs, the RAID device 200 executes a process of saving cache data required for backup to a NAND memory.

  The RAID device 200 includes a CM (Controller Module) 201, a PSU (Power Supply Unit) 202, and HDDs (Hard Disk Drives) 203a to 203z.

  The CM 201 is a control unit that performs cache memory management, host interface control, and HDD control, and includes a NAND flash 201a, a cache 201b, an FPGA (Field Programmable Gate Array) 201c, and a RoC (RAID-on-). (Chip) 201d, SCU (Super Capacitor Unit) 201e, and Exp (Expander) 201f.

  The NAND flash 201a is a NAND memory in which cache data stored in the cache 201b is backed up when a power failure occurs in the RAID device 200.

  The NAND flash 201a has a structure that is accessed in units of blocks, and the cache data of the cache 201b is written by sequential writing.

  FIG. 2 is a diagram showing a data structure of the NAND flash 201a of the present embodiment. The NAND flash 201a of FIG. 2 has a plurality of blocks a01 to a20.

  Each of the blocks a01 to a20 is a data area for storing cache data, and the cache data is written for each block. Note that the data area per block of the NAND flash 201a of the present embodiment is 4 Mbytes.

  Of these blocks a01 to a20, blocks a01 to a018 are data storage areas in which the cache data of the cache 201b is backed up. The blocks a19 and a20 are defective block management table 213B storage areas in which information indicating whether or not Dirty, information indicating defective blocks of the NAND flash 201a, and the like are stored. In the storage area (block a19.a20) of the defective block management table 213B, various data are managed by the RoC 201d.

  Next, the cache 201b in FIG. 1 will be described. The cache 201b is a cache memory that temporarily stores user data transferred between the host and the HDDs 203a to 203z. As described above, user data stored in the cache 201b is used as cache data.

  FIG. 3 is a diagram illustrating an example of the data structure of the cache memory described in this embodiment. The cache 201b illustrated in FIG. 3 includes a plurality of tables b01 to b10 that temporarily store cache data.

  Each table b01 to b10 shown in FIG. 3 has a capacity to store 4 Mbytes of user data. This user data is assumed to be managed by RoC 201d in units of 64 kB data length.

  Examples of user data include read data and write data. “Read data” is temporarily stored data obtained by reading user data stored in any of the HDDs 203a to 203z.

  When there is a user data read request from the host to the RAID device 200, the CM 201 acquires the cache data acquired from the tables b01 to b10 in the cache 201b if the user data corresponding to the read request can be acquired. Output data to the host.

  On the other hand, when the cache data cannot be acquired from the cache 201b, the CM 201 acquires user data corresponding to the read request from the HDD 203a or the like, and copies the acquired user data to the cache 201b. In this manner, acquiring user data corresponding to a read request from the HDD 203a or the like is hereinafter referred to as “staging”.

  As described above, since the read data is data acquired from the HDDs 203a to 203z, even if the cache data disappears from the cache 201b, the read data can be reacquired from the HDDs 203a to 203z.

  On the other hand, “write data” is user data for which a write request from the host to the RAID device 200 is temporarily stored in the cache memory, and is written to each HDD after satisfying a predetermined condition. For this reason, the write data may be data that has not been written to any of the HDDs 203a to 203z.

  Next, returning to the description of FIG. 1, the FPGA 201c will be described. The FPGA 201c represents an integrated circuit controlled by a predetermined program, and has a DMA (Direct Memory Access) engine.

  The DMA engine is a method for transferring data between a device and a RAM (Random Access Memory) without going through a CPU (Central Processing Unit). In this embodiment, cache data is saved in the NAND flash 201a at the time of a power failure. A DMA 201 to which functions necessary for restoration are added is installed in the FPGA 201c.

  As an example of the DMA engine, in the event of a power failure, a write DMA (TRN) for saving cache data, a read DMA (RCV) for returning the saved data to the cache 201b, and a command issuing DMA (for performing erase and check of the NAND flash 201a) UCE) and the like. The DMA transfers data in hardware by an instruction of RoC 201d.

  The FPGA 201c will be described with reference to the drawings. FIG. 4 is a functional block diagram showing the configuration of the FPGA shown in the present embodiment. The FPGA 201c executes processing for saving predetermined data in the cache 201b to the NAND flash 201a when a power failure occurs. Further, the FPGA 201 returns the data saved in the NAND flash 201a to the cache 201b at the time of power recovery or power failure.

  The FPGA 201c includes an IF (Interface) control unit 211, an access controller 212, an access management table 213, a TRN 214, and an IF control unit 215.

  The IF control unit 211 is an interface that controls the exchange of various data between the RoC 201d and the TRN 214 shown in FIG. 1 and the exchange of various data between the RoC 201d and the access controller 212 described later.

  The access controller 212 is a control unit that controls the exchange of various data between the access management table 213 and the RoC 201d via the IF control unit 211.

  The access management table 213 includes a backup management table 213a and a bad block management table 213b for managing the above-described bad blocks. First, the data structure of the backup management table 213a will be described.

  FIG. 5 is a diagram illustrating an example of a data structure of the backup management table 213a. As shown in FIG. 5, the backup management table 213a has a plurality of 3-bit flags c01 to c10 corresponding to the tables b01 to b10 of the cache 201b.

  Each bit of the 3-bit flag is composed of 3 bits, ie, [2] bit, [1] bit, and [0] bit. For each of the data stored in the corresponding table at the time of power failure, Is a flag for identifying whether or not to perform the process, and the flag of each bit in the present embodiment has the following meaning.

  First, the [2] bit of the 3-bit flag is a bit indicating whether or not double writing (Dual) is performed. Next, the [1] -th bit is a flag indicating a priority, and a flag that is set (that is, 1 is stored) indicates that a priority that is not set is low (Stay). Further, the [0] bit is a flag for determining whether to skip the backup, and if “1” is set, it indicates that the backup need not be performed in the event of a power failure.

  This backup management table 213a is managed by the RoC 201d.

  Next, the bad block management table 213b shown in FIG. 4 will be described. The bad block management table 213b is a table for managing bad blocks in which a write failure (Program Fail), an erase failure (Erace Fail), and a read failure (Load Fail) due to deterioration of the NAND flash 201a shown in FIG. This corresponds to the invalid table. Each data is managed by the firmware of the RoC 201d.

  This will be specifically described with reference to the drawings. FIG. 6 is a diagram showing an example of the data structure of the defective block management table 213b shown in the present embodiment. The defective block management table 213b in the present embodiment has items c01 to c20 corresponding to the blocks a01 to a20 of the NAND flash. Each item has a flag for identifying “Dirty” and “Invalid”.

  The “Dirty” flag is a flag for identifying whether or not a user data transfer error has occurred at the time of backup and writing to the NAND flash 201a did not end normally.

  As shown in FIG. 6, when the flag 1 is set, the Dirty state is indicated, and when the flag 1 is indicated, the transfer of the user data is normally completed.

  The “Invalid” flag is a flag for identifying that the block of each NAND flash 201a is a “bad block”. The block of the NAND flash 201a corresponding to the item in which “1” is stored in this flag indicates that it cannot be used for backup.

  Next, returning to the description of FIG. 4, the TRN 214 will be described. The TRN 214 indicates a DMA for saving user data in the cache 201b, and includes a main control unit 214a, a read unit 214b, an error control unit 214c, a data buffer unit 214d1, a CRC generation unit 214d2, and a NAND write control unit 214e. Have

  The main control unit 214a is a processing unit that updates the Invalid flag and the Dirty flag stored in the bad block management table 213b.

  The main control unit 214a includes an address specification unit 214a1, an invalid determination unit 214a2, and a Dirty update unit 214a3.

  The address specifying unit 214a1 performs address management of the bad block management table 213b. The invalid determining unit 214a2 determines whether the block of the target NAND flash 201a is defective based on the invalid flag of each item stored in the defective block management table 213b. Furthermore, the Dirty update unit 214a3 updates the Dirty flag of each item stored in the bad block management table 213b.

  The main control unit 214a also performs control to request the read unit 214b to start reading the cache 201b when a power failure occurs.

  Next, the read unit 214b is a control unit that saves at least part of the data in the cache 201b to the NAND flash 201a when a power failure occurs.

  The read unit 214 b includes a flag determination unit 220, a cache address management unit 221, and a read control unit 222.

  The flag determination unit 220 includes a backup completion table 220a as shown in FIG. As shown in FIG. 7, the backup completion table 220a is formed of 3 bits [0] [1] [2].

  Each bit is a flag indicating whether or not the backup processing of each first backup has been completed.

  The flag determination unit 220 instructs the read control unit 222, which will be described later, to read data of three different types during a power failure.

  The first backup processing is performed by the cache 201b corresponding to the 3bit flag in which “0” is stored in the [1] bit (Stay) and the [0] bit (skip) of the 3 bit flag in the backup management table 213a. This is a backup process of data stored in the block. That is, the first backup process is a process for saving the data of the block of the cache 201b which is not low in priority and not skipped to the NAND flash 201a.

  The second backup process is stored in the block of the cache 201b corresponding to the 3 bit flag in which “1” is stored in the [1] bit (Stay) of the 3 bit flag in the backup management table 213a. Data backup processing. That is, the second backup process is a process of saving the block data in the cache 201b to the NAND flash 201a.

  Further, the third backup process is stored in the block of the cache 201b corresponding to the 3 bit flag in which “1” is stored in the [2] bit (Dual) of the 3 bit flag in the backup management table 213a. Data backup processing. Since the data to be backed up for the third time is data that has already been saved in the NAND flash 201a in the first backup processing, the data is written twice.

  The cache address management unit 221 is a processing unit that manages a cache address indicating the position of cache data in the cache 201 b and outputs the managed cache address to the flag determination unit 220.

  The read control unit 222 reads the cache data of each table of the cache 201b instructed by the flag determination unit 220. The read data is output to the error control unit 214c and the data buffer control unit 214d1.

  When a transfer error occurs, the error control unit 214c notifies the main control unit 214a of an address for identifying the NAND block in which the transfer error has occurred. When the Dirty Update 214a3 of the main control unit 214a receives this notification, it requests an update of the Dirty flag of the bad block management table 213b.

  The data buffer unit 214d1 generates parity data by performing an XOR (exclusive OR) operation to prevent garbled data of the cache data input from the read control unit 222, and adds the XOR parity to the cache data. To do.

  The CRC generation unit 214d2 has a buffer for adding redundant bits made up of CRC (Cyclical Redundancy Check) and AID (Area ID) to user data and holding the added user data, and is stored in the buffer The user data is output to the NAND write control unit 214e.

  The NAND write control unit 214e has an address for identifying each block of the NAND flash 201a, and further outputs the user data output from the CRC generation unit 214d2 to the NAND flash 201a via the IF control unit 215. Write.

  Further, when a transfer error occurs when writing the cache data to the NAND flash 201a and the writing fails, the NAND write control unit 214e outputs the identification data of the corresponding block to the error control unit 214c.

  The IF control unit 215 is an interface that controls the exchange of various data between the TRN 214 and the NAND flash 201a.

  A supplement will be made to the SCU (Super Capacitor Unit) 201e shown in FIG. The SCU 201e indicates a large-capacity capacitor, and supplies power to the RoC 201d in a battery-free manner when a power failure occurs in the RAID device 200. Note that, in order to supply charged power, unlike the PSU 202, the supplied power is limited.

  The SCU 201e physically stores charges by using an “electric double layer” (an insulator is sandwiched between conductors and charges are accumulated when a voltage is applied). Accordingly, the battery is less deteriorated due to charging or discharging than a battery that stores electricity chemically, and charging is performed at a charge transfer rate.

  The EXP (expander) 201f is a processing unit that relays user data transmitted and received between the RoC 201d and the HDD 203a to the HDD 203z.

  The PSU (Power Supply Unit) 202 is a device for supplying power to the RAID device 200 from the outside. When the power supply from the outside is lost, that is, when a power failure occurs, the power supply to the RAID device 200 is stopped. Resulting in. At the time of this power failure, the SCU 201e is discharged to supply power to the RAID device 200.

  The HDD 203a to HDD 203z constitute a RAID group, and data is distributed according to the high speed and safety level, and includes a storage medium (disk) for storing user data and storing programs.

  Next, processing when the RAID apparatus according to the present embodiment is energized will be described with reference to FIG.

  First, when the RoC 201d of the RAID device 200 according to the present embodiment receives a request from a host (not shown) (step S1001), it determines whether or not the content of the request is a read request (S1002).

  In S1002, when the request received from the host is a read request, the RoC 201d acquires a disk address indicating the access position in the HDDs 203a to 203z included in the PSU 202 read request. Then, the RoC 201d searches whether the data corresponding to the disk address is stored in each of the tables b01 to b10 in the cache 201b (step S1003).

  Here, when the RoC 201d can acquire the data requested from the host from any of the tables b01 to b10 of the cache 201b (step S1004, Yes), the process proceeds to step S1008.

  On the other hand, when the read data is not acquired from the cache 201b (No in step S1004), the RoC 201d reserves a table for storing the disk address data included in the request from the host in the cache 201b (step S1005). . Specifically, the RoC 201d has free tables (tables that do not contain cache data) in the tables b01 to b10 in the cache 201b that only store data for a capacity for storing the data of the disk address included in the request. If it exists, secure it. If there is no free table, the RoC 201d creates a free table by releasing the data of the table storing the long-time stored data among the cache data stored in the tables b01 to b10. To secure the table. When the table is released, all bits of the 3 bit flag of the backup management table 213a corresponding to the table to be released are updated to “0”.

  Then, the RoC 201d notifies the FPGA 201c of the table to be staged (S1006). The main control unit 214a of the FPGA 201c that has received this notification updates the cache address management unit 221 to [0] bit of the 3-bit flag of the backup management table 213a corresponding to the target table, that is, to update the skip flag to “1”. .

  Thereafter, the RoC 201d performs staging processing (S1007).

  Specifically, in this staging process, first, the RoC 201d acquires the data of the disk address included in the read request from the HDD 203a to the HDD 203z via the Exp 201f. The RoC 201d is executed by copying the acquired data to the reserved area of the cache 201b.

  Then, the RoC 201d transmits the acquired data to the host, and proceeds to the process of step S1001.

  In the read request determination process in S1002, the RoC 201d determines whether this request is a write request if the request received from the PSU 202 is not a read request (S1002: NO) (S1009).

  If it is determined in this processing that the answer is Yes, that is, a write request (S1009: Yes), the RoC 201d confirms whether data having the same address as the address included in the write request is stored in the cache 201b (S1010). .

  Here, when it is determined that there is no cache data (S1010: No), the RoC 201d performs a process of securing the cache area of the cache 201b (S1011). Since this process is the same as the process of S1005 described above, a description thereof will be omitted.

  Next, the RoC 201d confirms whether the write request is a write to a specific area including configuration information or the like (S1012). In this confirmation, when it is determined that the writing is in the specific area, the RoC 201d notifies the FPGA 201c (S1013). Upon receiving this notification, the main control unit 214a of the FPGA 201c sets the [2] bit (Dual) flag of the 3-bit flag corresponding to the table that is the cache allocation area of the backup management table 213a to the cache address management unit 221. To 1 ”.

  Then, the RoC 201d stores the data sent following the Write request from the PSU 202 to the table of the cache 201b that has become the cache securing area (S1014).

  Then, the RoC 201d controls the Exp 201f and writes the data sent from the host following the Write request to the disk address included in the Write request among the HDDs 203a to 203z (S1016).

  In the processing of S1010, when the data included in the disk address included in the Write request already exists in the cache 201b, the RoC 201d sends the data existing in the cache 201b from the host following the Write request. The data is updated (S1015), and the process proceeds to S1016.

  When the process of S1016 is completed, the RoC 201d proceeds to the process of S1001.

  Furthermore, when the RoC 201d determines in the processing of S1009 that the received request is not a write request, the RoC 201d determines whether the received request is a copy request (S1017).

  Here, when the RoC 201d determines that the received request is not a copy request (S1017: No), the RoC 201d performs other processing according to the request (S1023), and proceeds to the processing of S1001.

  In addition, when the RoC 201d determines that the received request is a copy request (S1017: Yes), the RoC 201d checks whether the copy source data is stored in any of the tables b01 to b10 of the cache 201b (S1018). ).

  Here, when the data to be copied is not stored in any of the tables b01 to b10 of the cache 201b (S1018: No), processing for securing the cache area of the cache 201b is performed (S1019). Since this process is the same as that of S1005 described above, description thereof is omitted.

  The RoC 201d notifies the FPGA 201c that staging processing has been performed based on the copy request (S1020). Upon receiving this notification, the main control unit 214a of the FPGA 201c sets the [1] bit (Stay) flag of the 3-bit flag corresponding to the table that is the cache allocation area of the backup management table 213a to the cache address management unit 221. To 1 ”.

  Next, the RoC 201d controls the Exp 203 to read the data of the copy source HDD specified by the copy request and write it in the table of the cache 201b in which the area is secured (S1021).

  The RoC 201d controls the Exp 203 to perform copy processing by writing the copy source data written in the cache 201 to the copy destination HDD (S1022).

  If the RoC 201d determines that the copy source data is stored in any of the tables b01 to b10 of the cache 201b in the process of S1018, the RoC 201d does not perform the process related to the staging of S1019 to S1021. The process proceeds to S1022.

  When the RoC 201d completes the process of S1022, the RoC 201d proceeds to the process of S1001. As described above, by the processing of the RoC 201d and the FPGA 201c, the 3-bit flags c01 to c10 of the backup table 213a have the following status.

  First, the [2] bit (Dual) of the backup table 213a corresponding to the table of the cache 201b in an important area that contains configuration information and the like is “1”. That is, the data stored in this table is a target of double writing at the time of backup at the time of a power failure.

  Also, the first [1] bit (Stay) of the backup table 213a corresponding to the staged cache 201b table is “1” based on the copy instruction. When copying is performed again, the load on the HDD storing the copy source data can be reduced if the data exists in the cache 201b. Therefore, the copy source data is preferably stored in the cache 201b. However, in the first place, in the case of a copy command, the copy source data exists in any of the HDDs 203a to 203z, and the data is not lost, so the priority is set lower than the data in other areas.

  Further, based on the read instruction, the [0] bit (Skip) of the backup management table 213a corresponding to the staged cache 201b table is “1”. The target data of the read instruction exists in any of the HDDs 203a to 203z, and the data is not lost. In addition, unlike the Copy instruction, the Read instruction does not repeat the same instruction immediately after the power recovery, and the load acquired during the power recovery increases because the data acquired by the Read instruction is not in the cache 201b. Less likely.

  Therefore, in this embodiment, the target data for which the Read command has been acquired is skipped, that is, is not backed up because the necessity for backup is small.

  Note that as a result of the processing of the RoC 201d, a 3-bit flag in which all bits of the backup management table 213a indicate “0” indicates that data based on the Write instruction is being cached. Data based on the Write command is data received from the host, and depending on the timing of a power failure, data before being stored in any of the HDDs 203a to 203z may be included. Therefore, at the time of a power failure, it is necessary to back up with higher priority than the HDDs 203a to 203z.

  Therefore, in the processing at the time of a power failure described later, this Write command is backed up to the NAND flash 201a together with specific information such as configuration information that is the target of double backup.

  Next, FIG. 9 and subsequent drawings of processing performed in the RAID device 200 when a power failure occurs using the cache 201b, the backup management table 213a, the bad block management table 213b, and the NAND flash 201a described above. It explains using.

  In the present embodiment, the state of the cache 201b, the backup management table 213a, the FPGA flash 201a, the bad block management table 213b, and the backup completion flag 220a immediately before the power failure occurs will be supplementarily described with reference to FIG. .

  Note that the state of FIG. 10 is merely an example, and at the time of energization, the content of data stored in the cache 201b is updated as needed, and does not necessarily become FIG. 10 immediately before a power failure.

  First, by the above processing, the contents of the 3-bit flags c01 to c10 of the backup management table 213a are determined according to the type of data stored in the tables b01 to b10 of the corresponding cache 201b.

  In the present embodiment, as shown in FIG. 10, since the configuration information is stored in the table b01 of the cache 201b, “1” is stored in the [2] bit (Dual) of the corresponding 3-bit table c01. Has been.

  Further, “1” is stored in the “1” bit flag (Stay) of the 3 bit flags c04 and c10 corresponding to the data in the tables b04 and b10 acquired based on the Copy instruction.

  Furthermore, “1” is stored in the “0” bit flag (Skip) of the 3-bit flags c02 and c08 corresponding to the data in the tables b02 and b08 acquired based on the Read instruction.

  Further, “1” is stored in the [Invalid] flag of the item d05 of the defect management table 213b of the FPGA flash 201. That is, the block a05 of the FPGA 201a corresponding to the item d05 indicates that it is a defective block.

  When a power failure is detected in the above state (FIG. 9: S2001), each component of the CM 201 is operated by power supply from the SCU 201e and performs the following processing.

First, the FPGA 201c notifies the read control unit 222 that both the [1] bit (Stay) and the [0] bit (Skip) are not “1” among the 3 bit flags c01 to c10 of the backup management table 213a. The corresponding data in the cache 201b is written to the NAND flash (S2002).
Specifically, each component of the FPGA 201c performs the following processing.

  First, the main control unit 214a informs the read control unit 222 that both the [1] bit (Stay) and the [0] bit (Skip) of the 3 bit flags c01 to c10 of the backup management table 213a are “1”. The data of the cache 201b corresponding to the data that does not exist is read out.

  In this embodiment, since the backup management tables c01, c03, c05, c06, c07, and c09 are applicable, the read control unit 222 stores the tables b01, b03, b05, b06, b07, and b09 in the cache 201b. Read data.

  The data read by the read control unit 222 is given a CRC code via the CRC control unit 214d2. As shown in FIG. 11, the data to which the CRC code is added is a block that does not correspond to an item for which the Invalid flag of the NAND flash 201a is set as needed by the NAND write control unit 214e (in FIG. 11, other than the block a05). Written to the block. At this time, a table name (such as b01) of the cache 201b that is a reading source may be assigned together with the CRC code. In this way, when restoring the cache at the time of power recovery, the FPGA 201c refers to the assigned table name and is stored in each of the tables b01 to b10 of the cache 201b at the time of power failure. It is possible to re-store the same data as the data.

  At this time, each time the NAND write control unit 214e writes to the block of the NAND flash 201a, the NAND write control unit 214e performs error verification using the CRC code attached to the written data.

  If it is determined that there is an error in the written data, the NAND write control unit 214e rewrites the next block after the previously written block.

  That is, as shown in FIG. 11, when the data of the table b09 of the cache 201b is stored in the block a07 of the NAND flash 201a and an error is detected in the verification, the NAND write control unit 214e re-reads the next block a08. Write.

  In this rewriting, the NAND write control unit 214e notifies the main control unit 214a of the block having an error. In response to this, “1” is stored in the Dirty flag of the item d05 of the Dirty update 214a3 of the main control unit 214a.

  Through the processing as described above, in the present embodiment, the table b01 including the configuration information and the data of the tables b03, b05 to b07, and b09 storing the cache data not based on the Read instruction and the Copy instruction are converted to NAND. The data are stored in the blocks a01 to a04, a06, and a08 of the flash 201a.

  When this processing is completed, the main control unit 214a sets the [0] (1st) Bit flag of the backup completion table 220a to “1”.

  Next, the FPGA 201c NANDs the data in the cache 201b corresponding to the [1] bit (Stay) of “1” among the 3 bit flags c01 to c10 of the backup management table 213a. Writing to the flash (S2003).

  That is, this processing is performed after the data of the cache 201b corresponding to the case where the [1] bit (Stay) and the [0] bit (Skip) are not “1”.

  Specifically, each component of the FPGA 201c performs the following processing.

  First, the main control unit 214a notifies the read control unit 222 of the cache 201b corresponding to the 3 bit flags c01 to c10 of the backup management table 213a corresponding to those whose [1] bit (Stay) is “1”. The data is read out.

  In the present embodiment, as shown in FIG. 12, since the backup management tables c04 and c10 correspond, the read control unit 222 reads the data in the tables b04 and b10 in the cache 201b.

  The data read out by the read control unit 222 is given a CRC code via the CRC control unit 214d2, and as shown in FIG. 12, the NAND write control unit 214e, as needed, the invalid flag of the NAND flash 201a. It is written in the block of the block that does not correspond to the item that stands.

  Also at this time, the NAND write control unit 214e performs error verification using the CRC code attached to the written data every time data is written to the block of the NAND flash 201a.

  If it is determined that there is an error in the written data, the NAND write control unit 214e rewrites the next block after the previously written block.

  Through the processing as described above, in the present embodiment, the data in the tables b04 and b10 acquired by the Copy instruction is stored in the blocks a09 to a10 of the NAND flash 201a.

  When this processing is completed, the main control unit 214a sets the [1] (2nd) bit flag of the backup completion table 220a to “1”.

  Furthermore, the FPGA 201c sends the data in the cache 201b corresponding to the 3rd flags c01 to c10 of the backup management table 213a corresponding to the [2] bit (Dual) being “1” to the read control unit 222 by NAND flash. Is written into (S2004). Since this data is the data written in S2002, the data is written again.

  Specifically, each component of the FPGA 201c performs the following processing.

  First, the main control unit 214a notifies the read control unit 222 of the cache 201b corresponding to the 3 bits flags c01 to c10 of the backup management table 213a corresponding to the [2] bit (Dual) being “1”. The data is read out.

  In the present embodiment, as shown in FIG. 13, since the backup management table c01 corresponds, the read control unit 222 reads the data in the table b01 of the cache 201b.

  The data read by the read control unit 222 is given a CRC code via the CRC control unit 214d2, and as shown in FIG. 13, the invalid flag of the NAND flash 201a is occasionally given by the NAND write control unit 214e. It is written in the block of the block that does not correspond to the item that stands.

  Also at this time, the NAND write control unit 214e performs error verification using the CRC code attached to the written data every time data is written to the block of the NAND flash 201a.

  If it is determined that there is an error in the written data, the NAND write control unit 214e rewrites the next block after the previously written block.

  Through the processing as described above, in the present embodiment, the data of the table b01 storing the data of the specific address where the configuration information and the like are stored is stored in the block a012 of the NAND flash 201a.

  When this processing is completed, the main control unit 214a sets the [1] (2nd) bit flag of the backup completion table 220a to “1” and completes the backup processing.

  In this process, the data stored in the tables b02 and b08 of the cache b01 corresponding to the 3-bit flags c02 and c08 in which “1” is stored in the Skip flag is not stored in the NAND flash 201a. That is, these data are not backed up.

  As described above, in this embodiment, when the cache data is backed up to the NAND flash 201a in the event of a power failure, the backup data backup priority and the availability of the backup are determined based on the 3-bit flag.

  With this configuration, important information such as configuration information and data that may not be stored in any of the HDDs 203a to 203z such as write data can be stored in the NAND flash 201a first in the event of a power failure. It becomes. As described above, since the SCU 201e can supply power only temporarily, the reliability of data backup is increased by performing backup first. That is, in this embodiment, important data is backed up preferentially.

  Furthermore, for particularly important data, more reliable backup is possible by performing double writing after backup of other data. In the mobile phone of this embodiment, the double writing is performed for the second time after the storage of data having a low backup priority such as a Copy instruction is completed. This is because the data is stored in the NAND flash 201a at an early time after the occurrence of a power failure and after a write check by CRC once, and the data can be saved to a certain extent once, so the second write This is because it has a meaning to be stored as insurance in case the data is lost.

  In the present embodiment, the backup process is performed by the process of the FPGA 201c. This is due to the high speed and power saving of the FPGA 201c. However, if the SCU 201e has sufficient power capacity, the above-described backup processing may be realized by the Loc 201d executing a predetermined program.

200 RAID device 201 CM
201a NAND flash 201b cache 201c FPGA
201d RoC
201e SCU
201f Exp
202 PSU
203a to 203z HDD
211, 215 IF control unit 212 access controller 213 access management table 213a backup management table 213b bad block management table (BM)
214 TRN
214a Main control unit 214b Read unit 214c Error control unit 214d1 Data buffer unit 214d2 CRC generation unit 214e NAND write control unit 220a Backup completion flag

Claims (8)

A cache memory for storing data acquired when accessing the storage device;
Non-volatile memory;
Management for storing information on whether or not the data stored in the cache memory is data to be saved in the nonvolatile memory and information for determining the priority of saving the data to be saved in the nonvolatile memory Table,
When storing data in the cache memory, according to the type of data, information on whether or not the data is to be saved in the nonvolatile memory, and information for determining the priority of saving the data to be saved in the nonvolatile memory Management means for storing in the management table;
Based on the information stored in the management table whether or not the data is to be saved in the nonvolatile memory and the information for determining the priority of saving the data to be saved in the nonvolatile memory when a power failure occurs A power failure processing unit that executes processing for writing data to be saved in the nonvolatile memory out of data stored in the cache memory in order from data with a high priority to data with a low priority according to a priority order And an evacuation processing apparatus. The management means, as information for determining the priority order of the save, at least information for identifying data acquired when executing a data copy process between storage devices based on a copy command from the host device Store in the management table;
The power failure processing unit refers to the management table, and lowers the priority of the order of writing the data acquired when the copy process is executed among the data stored in the cache memory to the nonvolatile memory. The evacuation processing apparatus according to claim 1. The management means, as information for determining the priority order of the saving, at least information for identifying data acquired when a data read process from the storage device is executed based on a read command from the host device Store in the management table;
The power failure processing unit refers to the management table and does not write the data acquired when the read process is executed among the data stored in the cache memory to the nonvolatile memory. The evacuation processing apparatus according to claim 2. The management means, as information for determining the priority of evacuation, at least information for identifying acquired data from the host device based on an access command to a specific storage address of the storage device Memorize it on the table,
The power failure processing unit refers to the management table, and among the data stored in the cache memory, the data acquired based on an access command to a specific storage address of the storage device is stored in the nonvolatile memory a plurality of times. 4. The save processing apparatus according to claim 1, wherein writing is performed. A cache memory for storing data acquired at the time of accessing the storage device, a nonvolatile memory, information on whether or not the data stored in the cache memory is data to be saved in the nonvolatile memory, and the nonvolatile memory A processing device having a management table for storing information for determining the priority of saving data to be saved in the memory,
When storing data in the cache memory, according to the type of data, information on whether or not the data is to be saved in the nonvolatile memory, and information for determining the priority of saving the data to be saved in the nonvolatile memory Is stored in the management table,
Based on the information stored in the management table whether or not the data is to be saved in the nonvolatile memory and the information for determining the priority of saving the data to be saved in the nonvolatile memory when a power failure occurs A process of writing data to be saved in the nonvolatile memory out of data stored in the cache memory in order from data having a higher priority to data having a lower priority in accordance with a priority order is executed. The save processing method. The processor further comprises:
When storing information for determining the priority order of saving in the management table, as information for determining the priority order of saving, at least a copy of data between storage devices based on a copy command from the host device Information for identifying the data acquired when the process is executed is stored in the management table;
When storing data in the cache memory, the priority of the order of writing to the non-volatile memory of the data acquired when the copy process is executed among the data stored in the cache memory with reference to the management table The evacuation processing method according to claim 5, wherein: A cache memory for storing data acquired at the time of accessing the storage device, a nonvolatile memory, information on whether or not the data stored in the cache memory is data to be saved in the nonvolatile memory, and the nonvolatile memory In a processing apparatus having a management table for storing information for determining the priority of saving data to be saved in the memory,
When storing data in the cache memory, according to the type of data, information on whether or not the data is to be saved in the nonvolatile memory, and information for determining the priority of saving the data to be saved in the nonvolatile memory Is stored in the management table,
Based on the information stored in the management table whether or not the data is to be saved in the nonvolatile memory and the information for determining the priority of saving the data to be saved in the nonvolatile memory when a power failure occurs A process of writing data to be saved in the nonvolatile memory out of data stored in a cache memory in order from data having a higher priority to data having a lower priority in accordance with a priority order is executed. A save processing program. Further to the processing device
When storing information for determining the priority order of saving in the management table, as information for determining the priority order of saving, at least a copy of data between storage devices based on a copy command from the host device Storing information for identifying data acquired when the process is executed in the management table;
When storing data in the cache memory, the priority of the order of writing to the non-volatile memory of the data acquired when the copy process is executed among the data stored in the cache memory with reference to the management table The evacuation processing program according to claim 7, wherein