JP2006099802A - Storage controller and cache memory control method - Google Patents

Abstract

The processing performance of a storage controller with a write cache is improved.
In a storage control device 2000 including a non-volatile cache 2400 that is interposed between a plurality of disk devices 3000 and a host computer 1000 and temporarily holds read data / write data exchanged between them. Management of user data on the cache 2400 is managed in a cache management information area 2420 in the cache 2400 and a local memory management information area 2221 in the volatile local memory 2210 that can be accessed at higher speed. The normal management information is referred to from the high-speed local memory management information area 2221, and when a failure occurs, the management information is restored from the nonvolatile cache management information area 2420 to the local memory management information area 2221. Cache 240 without compromising reliability Increase the speed of the access process.
[Selection] Figure 1

Description

  The present invention relates to a storage control technique and a cache memory control technique, and more particularly to a technique that is effective when applied to a storage control device or the like equipped with a nonvolatile cache memory for temporarily storing user data.

  As recent market trends, there are increasing demands for higher performance, larger capacity, and lower price of storage devices, and the importance of RAID (Redundant Array of Inexpensive Disks) technology. In RAID, a plurality of disk devices are configured in an array, and at the time of data writing, in addition to the write data, redundant data is written to a disk device different from the disk device storing the write data. Even in the event of a disk device failure, the data integrity of the disk device is improved by making it possible to recover data on the failed disk device from the data of another disk device and the redundant data. However, RAID improves data integrity, but increases the processing time for generating / writing redundant data, and the write performance from the host is greatly degraded.

  For this reason, conventionally, write cache technology is indispensable for RAID support. The write cache is a cache that is mounted in the controller and temporarily writes data. In a write request from the host, an end report is returned to the host when the cache is written. Then, generation of redundant data and storage of write data and redundant data in a disk device are performed asynchronously with host I / O processing, thereby preventing performance degradation during write processing.

  The above prior art is a technique for performing generation of redundant data / write data and writing of redundant data to the disk device asynchronously without synchronizing with the host I / O. This technique improves response performance, It does not improve the processing performance of the control device itself.

  In addition, when a write cache is used, since completion is reported to the host when data is written on the cache, there is host data that is not reflected in the disk device on the cache. Therefore, this write cache needs to be non-volatile in order to prevent lost user data when a failure such as a sudden power failure occurs. At this time, it is necessary to store not only the user data but also management information for managing the user data on the write cache or other nonvolatile memory.

  This write cache and non-volatile memory are generally located outside the processor. For this reason, the access from the processor to the write cache and the non-volatile memory is extremely slow compared to the access to the local memory in the processor. This leads to a decrease in processing performance.

  An object of the present invention is to reduce processing time associated with cache memory control and improve processing performance as a storage control device without reducing reliability in a storage control device including a cache memory.

  Another object of the present invention is to improve not only the write performance but also the read performance in a storage control device having a cache memory.

  Another object of the present invention is to provide a cache memory capable of reducing processing time associated with control of a cache memory such as a write cache while maintaining reliability, and improving processing speed of data transfer via the cache memory. To provide control technology.

  The present invention is a storage control device including a cache memory that is interposed between a host device and a storage device, controls data exchange between the host device and the storage device, and temporarily stores data. The management information of the data stored in the cache memory is stored in multiple in the nonvolatile first storage means and the second storage means whose access operation is faster than the first storage means. The management information is updated with respect to the second storage means, and the management information is updated with respect to the first and second storage means.

  According to another aspect of the present invention, there is provided a cache memory control method that intervenes in a data transfer path and temporarily retains data, and management information of data stored in the cache memory is stored in a nonvolatile first storage unit; Multiple storage is performed in the second storage means, which is faster in access operation than the first storage means, management information is referred to the second storage means, and management information is updated in the first and second storage means. This is executed for the storage means.

  More specifically, as an example, a stand-alone type or host that is located between a host computer and a storage device such as a disk and performs storage device control or storage device control with RAID control based on an instruction from the host computer In an integrated or device-integrated storage control device, the storage control device has a nonvolatile cache mechanism for temporarily storing user data, and the management information of the user data on the cache is transferred at a low speed. There are two types of management on a non-volatile memory and a high-speed but volatile memory. The normal management information is referred to from a high-speed volatile memory to increase the speed. When a failure such as a sudden power failure occurs, the user data / management information on the nonvolatile memory prevents data loss and improves reliability.

  In order to realize these control functions, as a control logic of the storage control device, a means for double-writing user data management information on a low-speed nonvolatile memory and a high-speed volatile memory, and when normal, the management information is high-speed Means for referring from the volatile memory, means for referring to the management information from the nonvolatile memory in the event of a failure such as a sudden power failure, and means for restoring the reference information on the volatile memory are provided.

  According to the storage control device of the present invention, in a storage control device equipped with a cache memory, the processing time associated with the control of the cache memory is reduced and the processing performance as the storage control device is improved without reducing the reliability. The effect that it can be obtained.

  According to the storage control device of the present invention, in the storage control device provided with the cache memory, it is possible to improve not only the write performance but also the read performance in the same manner.

  According to the cache memory control method of the present invention, it is possible to reduce the processing time associated with the control of a cache memory such as a write cache while maintaining reliability and to improve the processing speed of data transfer via the cache memory. The effect of is obtained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  Note that the configuration shown in the following embodiment is merely an example, and can be realized by another configuration.

  FIG. 1 is a conceptual diagram showing an example of a configuration when a storage control device and a cache memory control method according to an embodiment of the present invention are applied to a disk array device.

  In FIG. 1, 1000 is a host computer as a central processing unit that performs data processing, 2000 is a storage control device that controls a disk device, and 3000 is a disk device that stores host data. Here, the storage control device 2000 can be inserted into a slot directly connected to the host bus and incorporated into the host housing, the storage control device 2000 can be incorporated into an independent housing, or can be implemented as a housing incorporating a disk device. It may be configured.

  As an example, a plurality of disk devices 3000 constitute a disk array, and user data received from the host computer 1000 and redundant data generated from the user data are distributed to the plurality of disk devices 3000 by RAID control of the storage control device 2000. And stored.

  The storage controller 2000 includes a host I / F control unit 2100 that performs protocol control with the host computer 1000, a microprocessor (hereinafter referred to as a processor) 2200 that controls the entire controller, and a data transfer control unit 2300 that performs data transfer. , A non-volatile cache memory (hereinafter referred to as a cache) 2400 used for temporary storage of user data such as read data and write data during data transfer between the host computer 1000 and the disk device 3000, and each disk device The DRVI / F control unit 2500 performs protocol control with 3000.

  The processor 2200 includes a local memory 2210 inside.

  The contents of the cache 2400 will be described with reference to FIG. The cache 2400 includes a user data area 2410 and an in-cache management information area 2420 for managing the user data. In the user data area 2410, actual user data is temporarily stored, and in the cache management information area 2420, data attributes (write data / read data) necessary for managing the user data, host computer are stored. Information such as logical address of the user data designated by 1000, empty area information, management information of priority in replacement of cache storage contents, and the like are stored. In the present embodiment, the management information area is placed in the cache, but other memories may be used as long as they are nonvolatile memories.

  The contents of the local memory 2210 will be described with reference to FIG. The local memory 2210 includes a local memory management information area 2221 storing information equivalent to the above-described cache management information area 2420, and a program area 2222 storing a microprogram for controlling the entire storage control device 2000. Consists of. In the present embodiment, the management information area is placed in the local memory 2210, but other memories may be used as long as the speed is high.

  The processor 2200 executes the program area while decoding the sequential program area, and controls the storage controller 2000. Further, the processor 2200 performs dual management by double-writing management information of data stored in the user data area 2410 in the management information area 2420 in the cache and the management information area 2221 in the local memory.

  Here, since the local memory 2210 is located inside the processor 2200, access from the processor can be performed at high speed. In contrast, since the cache 2400 corresponds to an external memory, access from the processor 2200 is extremely slow. In recent years, with the development of the PCI bus described later, the posted write method has been adopted, and the write (update) speed of the external memory such as the cache 2400 has been increased to the same level as the internal memory (local memory 2210). The read speed is much faster in the internal memory. Accordingly, when referring to the management information area 2420 in the cache, referring to the management information area 2221 in the local memory can reduce the overhead associated with memory access.

  As an example, FIG. 4 illustrates a connection configuration when the processor 2200, the host I / F control unit 2100, the subordinate data transfer control unit 2300, the cache 2400, and the DRVI / F control unit 2500 are controlled using the PCI bus 4000. An example is shown. In this case, in the processor 2200, a microprocessor unit (MPU) 2201 that operates according to a microprogram stored in the program area 2222 of the local memory 2210, a bus that realizes a PCI bus I / F between the MPU 2201 and the outside. A controller 2202 is provided.

  In the above-described posted write, for example, when data is written from the MPU 2201 to the cache 2400 via the bus controller 2202, the data write processing in the MPU 2201 is completed when the data write to the bus controller 2202 is completed. There is no need to wait for completion, and high-speed data writing to the outside becomes possible. On the other hand, in the data read processing from the external cache 2400 or the like to the MPU 2201, high-speed data read (referring to the in-cache management information area 2420 of the cache 2400) is expected because it depends on the access speed of the cache 2400. Can not.

  Therefore, in this embodiment, instead of referring to the in-cache management information area 2420 of the cache 2400, by referring to the local memory management information area 2221 of the local memory 2210 that holds equivalent management information, Speeding up the control of the cache 2400 is realized.

  Next, I / O processing from the host computer 1000 in the disk subsystem according to the present embodiment will be described with reference to FIGS. 1, 2, 3, and 6. FIG. Write processing from the host computer 1000 will be described.

  At the time of a write request from the host computer 1000, the processor 2200 receives the write logical data by the host I / F control unit 2100, writes the data to the user data area 2410 through the data transfer control unit 2300, and terminates in the host computer 1000 To report. In order to write to the user data area 2410 on the cache, it is necessary to search for an empty area. In this search, the processor 2200 searches using the high-speed local memory management information area 2221 instead of the low-speed cache management information area 2420. If a free area is found, data is written to the area, and both the in-cache management information area 2420 and the local memory management information area 2221 are updated. In this update, the processor 2200 may update both, and the data transfer control unit 2300 automatically writes the data in the cache management information area 2420 and the local memory management information area 2221 in accordance with an instruction from the processor 2200. It doesn't matter.

  Thus, when referring to the management information of the data on the cache 2400, it is referred from the high-speed local memory 2210, and when updating, both the cache 2400 and the local memory 2210 are updated. As described above, the read access speed of the cache 2400 is extremely low (for example, about 20 times that of the local memory 2210), whereas the write access speed of the cache 2400 is similar to that of the local memory due to the adoption of posted write. The method is useful.

  That is, the overhead reduction by changing the management information from the cache read to the local memory read is much greater than the increase in the overhead for double-writing the management information of the cache 2400 in the local memory 2210.

  In the above description, the writing process from the host computer 1000 to the cache 2400 has been described. According to the present embodiment, the generation of redundant data, the write data and the redundant data disk that are performed asynchronously with the host computer 1000 thereafter. Similarly, overhead can be reduced in writing to the device 3000. For example, when writing write data to the disk device 3000, it is necessary to search for write data in the user data area 2410, and to determine the write position of the write data to the disk device 3000, the logical address of the data is determined. Reference is needed. By referring all of these data management information from the high-speed local memory management information area 2221, the overhead is reduced, and the processing performance is improved by increasing the data transfer speed via the cache 2400 in the storage controller 2000. Can be realized.

  This increase in speed can also be achieved in the reading process from the host computer 1000. For example, in order to determine whether or not the data requested from the host computer 1000 exists in the user data area 2410 (hit / miss), it is necessary to refer to the management information. If the user data area 2410 does not exist, it is necessary to search for an empty area in the user data area 2410 in order to read from the disk device 3000 to the user data area 2410, and management information must be referred to. .

  Thus, whether it is a read process or a write process, most of the overhead of the processor 2200 that controls data transfer between the host computer 1000 and the disk device 3000 is management information for managing data in the user data area 2410. Reference and update of (2420 and 2221). Of these, the present embodiment is a method for reducing the overhead of reference processing, which has been conventionally low, and realizes a significant reduction in overhead in all access modes, thereby increasing the speed of the storage controller 2000. Can be achieved. An example of the host I / O process described above is shown together in the flowchart of FIG.

  Next, a recovery method in the event of a failure such as a sudden power failure will be described with reference to FIG. 1, FIG. 2, FIG. 3, and FIG.

  When power supply to the processor 2200 is stopped due to a failure such as a sudden power failure, the local memory 2210 that is a processor internal memory is generally a volatile memory, and all the information in the local memory 2210 is lost. On the other hand, the cache 2400 is a non-volatile memory, and both the user data area 2410 and the in-cache management information area 2420 hold information.

  Here, when the failure is recovered and the power is turned on again, the processor 2200 first restores the information in the management information area 2221 in the local memory where the information has been lost. The management information area 2221 in the local memory is restored using the information inside. This restoration may be performed by the processor 2200 itself, or by the data transfer control unit 2300 according to an instruction from the processor 2200.

  While this restoration process is being performed, I / O processing from the host computer 1000 is temporarily stopped (the request from the host computer 1000 may not be accepted, the request is only accepted and only queued and executed) The data management information can be referred to by referring from the management information area 2420 in the cache.

  When the restoration of the management information area 2221 in the local memory is completed, the I / O processing as before is executed. A series of processing at the time of power-on is exemplified in the flowchart of FIG.

  In this way, the management data in the in-cache management information area 2420 on the non-volatile cache 2400 is used at the time of failure while it seems that the user data on the cache 2400 is managed by the local memory 2210 that volatilizes normally. Thus, data loss can be prevented and the data transfer speed via the cache 2400 can be increased without lowering the reliability.

  As described above, according to the storage control device and cache memory control method of the present embodiment, in a storage control device equipped with a write cache, access to user data on the cache without degrading data reliability. The management overhead can be greatly reduced, and the processing performance of the storage controller can be improved in any access mode.

  Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

1 is a conceptual diagram illustrating an example of a configuration when a storage control device and a cache memory control method according to an embodiment of the present invention are applied to a disk array device; FIG. It is a conceptual diagram which shows an example of the information content in the cache memory in the storage control apparatus which is one embodiment of this invention, and the control method of a cache memory. It is a conceptual diagram which shows an example of the information content in the local memory in the storage control apparatus which is one embodiment of this invention, and the control method of a cache memory. Concept showing an example of a configuration in a case where information transfer between a microprocessor and the outside is performed using a PCI bus in a disk array device to which a storage control device and a cache memory control method according to an embodiment of the present invention are applied FIG. It is a flowchart which shows an example of an effect | action of the storage control apparatus which is one embodiment of this invention, and the control method of cache memory. It is a flowchart which shows an example of an effect | action of the storage control apparatus which is one embodiment of this invention, and the control method of cache memory.

Explanation of symbols

  1000: Host computer (host device), 2000: Storage controller, 2100 ... Host I / F control unit, 2200 ... Microprocessor, 2201 ... Microprocessor unit (MPU), 2202 ... Bus controller, 2210 ... Local memory, 2221 ... Local memory management information area (second storage area) 2222... Program area, 2300... Data transfer control unit, 2400... Cache memory, 2410... User data area, 2420. ) 2500... DRVI / F control unit, 3000... Disk device (storage device), 4000.

Claims (25)

  A storage control device comprising a cache memory that is interposed between a host device and a storage device, controls data exchange between the host device and the storage device, and temporarily stores the data. The management information of the data stored in the cache memory is stored in a multiplex manner in a nonvolatile first storage means and a second storage means whose access operation is faster than the first storage means, The storage control device is characterized in that the management information is referred to the second storage means, and the management information is updated to the first and second storage means.   2. The storage control device according to claim 1, wherein the cache memory is configured by a nonvolatile storage medium, the first storage unit is set as a part of the nonvolatile storage medium, and the second storage unit is A storage control device, characterized in that it is set in a part of a local memory in which a control program for a microprocessor for controlling the operation of the storage control device is stored.   3. The storage control device according to claim 1, wherein the sound management information held in the first storage unit is copied to the second storage unit when the storage control device is restarted after a failure stop. The storage control device is characterized by restarting operation.   A control method of a cache memory that is interposed in a data transfer path and temporarily holds the data, the management information of the data stored in the cache memory, a non-volatile first storage means, The information is stored in the second storage means, which has a higher access speed than the first storage means, the management information is referred to the second storage means, and the management information is updated in the first storage means. And a control method for the cache memory, which is executed for the second storage means.   5. The cache memory control method according to claim 4, wherein the cache memory is constituted by a nonvolatile storage medium, the first storage means is set as a part of the nonvolatile storage medium, and the second storage means is provided. A method for controlling a cache memory, comprising: setting a part of a local memory in which a microprocessor control program for controlling the operation of the cache memory is stored. A storage control device for exchanging user data between a host device and a storage device,
At least one microprocessor;
A local memory for the control program and in-memory management information, but not for the user data;
A cache memory for user data, in which the cache memory stores in-cache management information; the in-memory management information represents the in-cache management information; and the in-memory management information and the in-cache management information Each having a cache memory that is information related to user data stored in the cache memory,
An access time for performing an access operation between the microprocessor and the local memory is shorter than an access time between the microprocessor and the cache memory for the same access operation,
The local memory and the cache memory store management information used only by the at least one microprocessor;
The local memory and the cache memory do not include management information used by a microprocessor different from the at least one microprocessor;
The control program accesses the local memory to access the in-memory management information, and whether or not the read data related to the read request is stored in the cache memory based on the in-memory management information. Determining, accessing the cache memory when the read data is stored in the cache memory, and accessing the read data; and when the read data is not stored in the cache memory The data storage device is accessed to access the read data, the read data in the cache memory is stored, the in-memory management information and the in-cache management information are updated, and the cache memory is updated. By performing the pointing process, Storage control apparatus characterized by black actuate the processor is configured to process the read request. The storage control device according to claim 6.
The control program accessing the local memory to access the in-memory management information;
Identifying an empty area in the cache memory based on the in-memory management information;
Storing write data associated with the write request in the empty area;
And further configured to operate the microprocessor to process the write request by updating the in-memory management information and the in-cache management information to indicate an update of the cache memory. A storage control device. The storage control device according to claim 6.
A storage controller, wherein the local memory is accessible only by the microprocessor. The storage control device according to claim 8.
The storage control device, wherein the local memory is a component of the microprocessor. A disk subsystem having a storage control device and a plurality of storage devices for storing data from a host device,
A cache memory for user data transferred between the storage device and the host device;
At least one processor operable to control the storage controller and having a local memory for control programs and management information associated with data stored in the cache memory;
The processor is capable of accessing the local memory faster than the cache memory;
The local memory and the cache memory store management information used only by the at least one processor;
The local memory and the cache memory do not include management information used by a processor different from the at least one processor;
The local memory does not store the user data;
Space available in the cache memory for the control program to operate the processor to access the management information in the local memory and store data associated with the write operation in response to a write operation , And in response to a read operation, access the management information in the cache memory to determine whether the requested data associated with the read operation is included in the cache memory. If not, identify the available space in the cache memory to access the management information in the local memory and store the requested data, and request the requested information from the storage device. To acquire data and store the requested data in the available space in the cache memory Disk subsystem, characterized in that it is made. The disk subsystem of claim 10, wherein
A disk subsystem, wherein the memory in the processor is a non-volatile memory. The disk subsystem of claim 10, wherein
The disk subsystem characterized in that the management information is also stored in the cache memory. The disk subsystem of claim 12,
The disk subsystem, wherein the processor updates the management information in the cache memory together with the management information in the processor. The disk subsystem of claim 10, wherein
A disk subsystem, wherein the storage device has a RAID configuration. The disk subsystem of claim 10, wherein
A disk subsystem, wherein the storage device is a magnetic disk device. A storage control device for data communication between a plurality of storage devices and at least one host device,
A first control unit for communication with the host device;
A second control unit for communication with the storage device;
A cache memory for storing management information related to user data stored therein, which is for user data transferred between the host device and the storage device;
A data transfer control unit configured to transfer data between the first control unit and the cache memory and between the second control unit and the cache memory;
At least one processor having a local memory therein for controlling the storage controller and storing the management information;
The local memory and the cache memory store management information used only by the at least one processor;
The local memory and the cache memory do not contain management information used by a processor different from the at least one processor;
The local memory does not store the user data;
The processor responsive to an operation on write data or read data accesses the management information stored in the local memory to determine whether the cache memory is adaptable to the operation; A storage control device configured to access the cache memory and store the write data or the read data in the cache memory when the memory is adaptable to the operation. The storage control device according to claim 16, wherein
An access control speed between the processor and the local memory is faster than an access speed between the processor and the cache memory. The storage control device according to claim 16, wherein
The storage control device, wherein the data transfer control unit copies the management information from the cache memory to the local memory. The storage control device according to claim 16, wherein
The storage control device, wherein the data transfer control unit copies the management information from the local memory to the cache memory. A disk subsystem having a storage control device and a plurality of storage devices for storing data from a host device,
A cache memory that temporarily stores data transferred between the host device and the storage device, and stores management information related to user data stored therein;
And at least one processor that controls the storage controller and has a local memory therein,
The processor is configured to store in the local memory at least a portion of the management information associated with the data stored in the cache memory;
The processor accesses the management information in the local memory to determine whether the cache memory can be adapted to an operation on write data or read data, and accesses the cache memory to access the cache memory Is further adapted to store write data or read data in the cache memory,
The local memory and the cache memory store management information used only by the at least one processor;
The local memory and the cache memory do not include management information used by a processor different from the at least one processor;
The disk subsystem, wherein the local memory does not store the user data. The disk subsystem of claim 20,
The disk subsystem characterized in that the memory in the processor stores a control program for controlling the storage controller. The disk subsystem of claim 20,
A disk subsystem characterized in that the local memory is a non-volatile memory. The disk subsystem of claim 20,
The management information includes a data attribute for managing the data in the cache memory, a logical address of the data in the cache memory, usable storage area information in the cache memory, and cache storage of the cache memory. A disk subsystem comprising at least one of priority management information in content replacement. 24. The disk subsystem of claim 23.
The disk subsystem further comprising a data transfer control unit for transferring the user data in the cache memory between the host device and the storage device. The disk subsystem of claim 20,
The disk subsystem, wherein the processor updates the management information in the cache memory and the local memory.

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