JP5349775B2 - Memory controller and control method thereof - Google Patents

Description

  The present invention relates to a memory controller that reads / writes data from / to a plurality of memory devices having different access cycles, and a control method therefor.

  FIG. 1 is a diagram showing an example of a configuration in a conventional memory system. 1 is an ASIC (Application Specific Integrated Circuit) including a memory controller. Reference numeral 101 denotes a memory controller included in the ASIC 100. Reference numeral 102 denotes a chip internal bus that connects the memory controller 101 and a functional module (not shown) in the ASIC 100. Reference numeral 103 denotes a register that stores conditions of devices connected to the memory controller 101.

  A command issuing circuit 104 issues an access command to a memory device connected to the memory controller 101. Reference numeral 105 denotes a data issue / reception circuit that transmits / receives data to / from a memory device connected to the memory controller 101. Reference numerals 106 to 109 denote memory devices connected to the memory controller 101.

  Next, the operation of the memory controller 101 in the conventional ASIC 100 will be described with reference to FIG. First, an access request from a functional module (not shown) in the ASIC 100 to the memory devices 106 to 109 is transmitted to the memory controller 101 via the chip internal bus 102. On the other hand, the memory controller 101 analyzes the received access request, and the command issuing circuit 104 generates a command for satisfying the requested access to any of the corresponding memory devices 106 to 109. Then, the command is issued to the corresponding memory device using a connection signal (RAS, CAS, ADDR, CS0 to CS3) to the outside of the chip, and data transmission / reception is performed by the data issuing / receiving circuit 105.

  The state of signals outside the chip at this time is shown in FIG. In FIG. 2, RAS, CAS, and ADDR are combined into one command. Further, the memory controller 101 sequentially receives read requests to the memory devices 106 to 109 via the chip internal bus 102 and issues read commands to the memory devices 106 to 109 in order.

Normally, the memory devices 106 to 109 are divided into a plurality of areas called banks, and a part of each area can be accessed, and the other parts can be accessed after a predetermined procedure is performed. This predetermined procedure requires many clock cycles, but the accessible portion for each bank of each device can be set independently. Therefore, in many cases, the memory controller 101 analyzes the requested command, determines whether or not a predetermined procedure is necessary for access, and changes the access order. Even when these operations are performed, as shown in Fig. 2, if read commands are continuous and the corresponding devices are different, the read command issue timing is controlled so that read data (DQ and DQS) do not collide. There is a need to.
JP 2003-271445 A

  However, with the recent improvement in the operating frequency of memory devices, the wiring delay on the board, which has been ignored by conventional memory controllers, is becoming a situation that cannot be ignored. This situation will be described with reference to FIGS.

  FIG. 3 is a diagram in which the relationship between the memory controller and the memory device is rewritten in a layout image on the substrate. The numbers shown in FIG. 3 are the same as those in FIG. As shown in FIG. 3, when a plurality of memory devices 106 to 109 are connected, the distances from the memory controller 101 of each memory device are different from each other, and the memory devices 109 are arranged gradually away from the memory device 106 in order. Become.

  In such an arrangement, when the memory controller 101 performs reading to each memory device, read data reception timing differs depending on the memory device due to a difference in distance from each memory device. In particular, when the clock cycle is shortened, the read data may be returned to the memory controller 101 at a timing exceeding the clock cycle.

  FIG. 4 is a diagram showing the number of wait cycles between memory devices when the layout is such that read data is fetched later by one cycle as the memory device becomes farther from the memory controller. Here, when the memory devices are different, data collision occurs unless the waiting cycles corresponding to the maximum number of waiting cycles are given, so that the operation timing on the data bus of the memory controller 101 is inefficient as shown in FIG. It becomes.

  The present invention aims to improve the efficiency on the memory data bus.

The present invention provides a memory controller that reads / writes data from / to a plurality of memory devices having different access cycles, a holding unit that holds a memory access request to the plurality of memory devices, and latency information indicating latency for each of the plurality of memory devices A first register for storing wiring, a second register for storing wiring delay information indicating a wiring delay for each of the plurality of memory devices, and when issuing a memory access request held in the holding means to the memory device, based on the wiring delay information stored in the second register and latency information stored in the first register, it has a control means for controlling to change the order in which issues the memory access request, The control means responds to the top memory access request held in the holding means. When the first memory access request has a longer access waiting time than the second memory access request, the second delay is caused by the line delay information and the wiring delay information for the second memory access request held in the holding means. The memory access request is issued and the order is changed .

According to the present invention, control is performed so as to change the order of issuing memory access requests to each memory device based on the information indicating the wiring delay between the plurality of memory devices and the latency information of each of the plurality of memory devices. As a result, the efficiency on the memory data bus can be improved.

  The best mode for carrying out the invention will be described below in detail with reference to the drawings.

[First Embodiment]
Processing for controlling the order in which commands are issued to the memory device based on the device latency information and the wiring delay information on the board when the memory controller issues a command to the memory device will be described with reference to FIGS. .

  First, the configuration and operation of the memory controller in the first embodiment will be described with reference to FIGS.

  FIG. 6 is a diagram illustrating an example of the configuration of the memory system according to the first embodiment. Reference numeral 600 shown in FIG. 6 denotes an ASIC including a memory controller. Reference numeral 601 denotes a memory controller in the first embodiment. Reference numeral 602 denotes a chip internal bus that connects the memory controller 601 and a functional module (not shown) in the ASIC 600. Transactions between a functional module (not shown) and the memory controller are transmitted / received via a chip internal bus.

  Reference numeral 603 denotes a register that holds a latency condition of a device connected to the memory controller 601. A register 604 holds wiring delay information of a device connected to the memory controller 601.

  A command issue circuit 605 issues an access command to a memory device connected to the memory controller 601. Reference numeral 606 denotes a data issuing / receiving circuit that transmits and receives data to and from a memory device connected to the memory controller 601. Reference numerals 607 to 610 denote memory devices connected to the memory controller 601. Hereinafter, the memory device is simply referred to as “device”.

  FIG. 7 is a diagram showing an example of the configuration of the command issuing circuit 605 shown in FIG. A buffer 701 shown in FIG. 7 temporarily stores a memory access request received from the chip internal bus 602. Reference numeral 702 denotes a determination circuit, which controls to change to an efficient order based on latency information and wiring delay information when a plurality of requests stored in the buffer 701 are issued to the device.

  First, when a memory access request is transmitted from a function module (not shown) to the memory controller 601 via the chip internal bus 602, the request is transmitted to the command issuing circuit 605. As a result, the transmitted memory access request is temporarily stored in the buffer 701 in the command issuing circuit 605 as shown in FIG. Then, when the buffer 701 is not empty, the determination circuit 702 extracts the request from the buffer 701, issues it as a command to the device, and transmits the information of the issue command to the data issue / reception circuit 606 shown in FIG.

  On the other hand, the data issue / reception circuit 606 generates data to the device, the timing of data received from the memory device, and the selection signal for the reception function module in the chip based on the issue command information received from the determination circuit 702.

  Here, when the determination circuit 702 extracts the request 0, the buffer 701 shifts all the requests by one. That is, request 1 at the present time (before the shift) is moved to the position of request 0 when request 0 is extracted from determination circuit 702, and request 2 at the current time is newly moved to the position of request 1. To do. Further, when the determination circuit 702 extracts the request 1, the request 0 is not changed, and the current request 2 is newly moved to the position of the request 1.

  FIG. 8 is a flowchart showing the determination process executed by the determination circuit 702. FIG. 9 is a diagram illustrating timing when a request to be extracted from the buffer 701 is determined. Here, for the sake of simplicity of explanation, it is assumed that all requests are read requests, and all the areas to be requested are accessible.

  Requests are stored in the buffer 701 in the order of request 0 (device 607) → request 1 (device 610) → request 2 (device 608) → request 3 (device 609) → request 4 (device 610). And It is assumed that the command issued before the request to the device 607 is sufficiently spaced.

  First, in step S801, the determination circuit 702 determines whether there is only one request in the buffer 701, and if there is only one, issues a command for that request in step S805. However, in step S801, if there is not only one request in the buffer 701 as assumed, it is determined in step S802 whether the interval from the previously issued command is sufficient.

  Here, since the command interval is sufficient from the above-mentioned assumption, the first command in the buffer 701 is issued (reading to the device 607) at t0 shown in FIG. In the buffer 701, the above-described shift is performed for all requests. With this shift, the requests are in the order of request 0 (device 610), request 1 (device 608), request 2 (device 609), and request 3 (device 610).

  Next, since the inside of the buffer 701 is not empty, the determination circuit 702 starts determining the next request. In step S803, the determination circuit 702 determines the access waiting time of the request 0 (device 610) and the request 1 (device 608) in the buffer 701. Here, the request access waiting time is the time that must be waited until the next command issuance after issuing the read request for each device obtained from the register 603 holding the latency information and the register 604 holding the wiring delay information. It is shown.

  Now, assuming that the latencies of the devices are all the same, the difference in request access waiting time depends on the wiring delay information. As described above, the memory controller 601 reads / writes data from / to a plurality of memory devices having different access cycles. However, if the required waiting time between the devices is given by the table shown in FIG. 4, the access to the device 610 of the request 0 requires a waiting time of 3 cycles. On the other hand, only one cycle of waiting time is required for accessing the device 608 of the request 1. Accordingly, since the first request access waiting time is longer than the second access waiting time, the determination circuit 702 determines No in step S803, and the second (request 1) command in the buffer 701 at t3 shown in FIG. Issue.

  In the buffer 701, the above-described shift is performed for all requests. As a result, request 0 (device 610) remains unchanged, request 2 (device 609) is newly moved to the position of request 1, and request 3 (device 610) is newly moved to the position of request 2. .

  Next, since the inside of the buffer 701 is not empty, the determination circuit 702 starts determining the next request. In step S803, the determination circuit 702 determines the access waiting time of the request 0 (device 610) and the request 1 (device 609) in the buffer 701. Similar to the above result, the determination circuit 702 determines No, and issues the second (request 1) command in the buffer 701 at t6 shown in FIG.

  In the buffer 701, the above-described shift is performed for all requests. As a result, the request 2 (device 610) is newly moved to the position of request 1 while the request 0 (device 610) remains unchanged.

  Next, since the inside of the buffer 701 is not empty, the determination circuit 702 starts determining the next request. In step S803, the determination circuit 702 determines the access waiting time of the request 0 (device 610) and the request 1 (device 610) in the buffer 701. Here, since the devices to be accessed are the same device, the determination circuit 702 determines Yes and executes the first request in the buffer 701 at t9 shown in FIG.

  In the buffer 701, the above-described shift is performed for all requests, and as a result, the request 1 (device 610) is newly moved to the position of the request 0.

  Next, since the inside of the buffer 701 is not empty, the determination circuit 702 starts determining the next request. In this case, since the request inside the buffer 701 is only the request to the device 610 in the request 0, the determination circuit 702 determines Yes in step S801, and in step S805, the buffer 701 stores the request at t11 shown in FIG. Execute the first request. At this time, since the immediately preceding command issue target device and the current command issue target device are the same, the command is issued so that there is no empty cycle on the memory data bus.

  As described above, the operation based on the wiring delay information in the substrate has been described. However, the present invention has the same effect as the above description even when a device having a different read latency is connected to each memory device to be connected. In such a case, the above-described wiring delay information may be read as latency difference information between memory devices.

[Second Embodiment]
Next, a second embodiment according to the present invention will be described in detail with reference to the drawings. In the first embodiment, the wiring delay information of each memory device is held by the holding means in the memory controller. However, the wiring delay information of each memory device may be supplied from the outside of the memory controller at a terminal.

  FIG. 10 is a diagram illustrating an example of the configuration of the memory system according to the second embodiment. Note that 1000 to 1010 shown in FIG. 10 correspond to 600 to 610 shown in FIG. 6 of the first embodiment. However, in the first embodiment, the wiring delay information of each memory device is held in the register 604 shown in FIG. 6, but in the second embodiment, an external terminal is provided so as to be supplied from the outside. is there.

  Further, when the wiring delay information of each memory device described above is changed to the difference information of the read latency of each memory device, the same effect as that of the first embodiment can be obtained.

[Third Embodiment]
Next, a third embodiment according to the present invention will be described in detail with reference to the drawings. In the first embodiment, the latency information common to the memory devices and the wiring delay information of the individual devices are respectively held in the registers. However, the second embodiment includes storage means for storing delay information for each individual device including common latency information.

  FIG. 11 is a diagram illustrating an example of a configuration of a memory system according to the third embodiment. Note that 1000 to 1002 and 1005 to 1010 shown in FIG. 11 correspond to 600 to 602 and 605 to 610 shown in FIG. 6 of the first embodiment.

  Reference numerals 1111 to 1114 shown in FIG. 11 are registers for holding device latency information and device wiring delay information, respectively.

  According to the third embodiment, an effect similar to that of the first embodiment can be obtained.

  Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), it is applied to an apparatus (for example, a copier, a facsimile machine, etc.) composed of a single device. It may be applied.

  In addition, a recording medium in which a program code of software for realizing the functions of the above-described embodiments is recorded is supplied to the system or apparatus, and the computer (CPU or MPU) of the system or apparatus stores the program code stored in the recording medium. Read and execute. It goes without saying that the object of the present invention can also be achieved by this.

  In this case, the program code itself read from the computer-readable recording medium realizes the functions of the above-described embodiments, and the recording medium storing the program code constitutes the present invention.

  As a recording medium for supplying the program code, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

  In addition, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also the following cases are included. That is, based on the instruction of the program code, an OS (operating system) running on the computer performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing. .

  Further, the program code read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. After that, based on the instruction of the program code, the CPU of the function expansion board or function expansion unit performs part or all of the actual processing, and the function of the above-described embodiment is realized by the processing. Needless to say.

It is a figure which shows an example of a structure in the conventional memory system. It is a figure which shows the mode of the signal in the chip exterior. It is the figure which rewrote the relationship between a memory controller and a memory device like the layout image on a board | substrate. It is a figure which shows the number of waiting cycles between memory devices in the case where the layout is such that read data is fetched later by one cycle as the memory device becomes farther from the memory controller. FIG. 4 is a diagram illustrating operation timing on a data bus of the memory controller 101. It is a figure which shows an example of a structure of the memory system in 1st Embodiment. FIG. 7 is a diagram illustrating an example of a configuration of a command issuing circuit 605 illustrated in FIG. 6. 5 is a flowchart illustrating a determination process executed by a determination circuit 702. It is a figure which shows the timing when the request | requirement taken out from the buffer 701 is determined. It is a figure which shows an example of a structure of the memory system in 2nd Embodiment. It is a figure which shows an example of a structure of the memory system in 3rd Embodiment.

Explanation of symbols

600 ASIC with memory controller
601 Memory controller 602 Chip internal bus 603 Register holding device latency condition 604 Register holding device wiring delay information 605 Command issuing circuit 606 Data issuing / receiving circuit 607 Memory device (Dev 0)
608 Memory device (Dev 1)
609 Memory device (Dev 2)
610 Memory Device (Dev 3)
701 Buffer 702 decision circuit

Claims (2)

In a memory controller that reads and writes data to multiple memory devices with different access cycles,
Holding means for holding memory access requests for the plurality of memory devices;
A first register storing latency information indicating latency for each of the plurality of memory devices;
A second register for storing wiring delay information indicating a wiring delay for each of the plurality of memory devices;
When issuing the memory access request held in the holding means to the memory device, the memory is based on the latency information stored in the first register and the wiring delay information stored in the second register. have a control means for controlling to change the order in which issues an access request,
The control means uses the wiring delay information for the first memory access request held in the holding means and the wiring delay information for the second memory access request held in the holding means to determine whether the first memory access request is the 2 A memory controller , wherein when the access waiting time is longer than that of the second memory access request, the order is changed so that the second memory access request is issued . Holding means for holding memory access requests for a plurality of memory devices; a first register for storing latency information indicating the latency for each of the plurality of memory devices; and wiring delay information indicating a wiring delay for each of the plurality of memory devices. A memory controller control method for reading and writing data to and from a plurality of memory devices having different access cycles.
When issuing the memory access request held in the holding means to the memory device, the memory is based on the latency information stored in the first register and the wiring delay information stored in the second register. have a control step for controlling to change the order in which issues an access request,
In the control step, the first memory access request is generated by the wiring delay information for the first memory access request held in the holding unit and the wiring delay information for the second memory access request held in the holding unit. A method for controlling a memory controller, comprising: changing an order so that the second memory access request is issued when an access waiting time is longer than a second memory access request .

Images