WO2005101219A1 - Memory controller and semiconductor device - Google Patents

Abstract

A memory controller (121) is connected to an SRAM (122) which can be accessed only by a row address and an NOR-type flash memory and to an SDRAM (124) which can be accessed by specifying a row address and a column address. A data bus (107) is shared by time division and the other control lines are individually connected to the SRAM (122), the NOR-type flash memory (123), and the SDRAM (124). An access request for each of the memory devices as the access destination is accumulated in a FIFO memory (201). A data bus idle section which cannot be accessed by the SDRAM (124) is detected by an SDRAM access section judgment device (204). If an access request to the SRAM (122) following the access-disabled section can be executed, the access request order in the FIFO memory (201) is changed so that the access request to the SRAM (122) is placed at the head.

Description

 Specification

 Memory controller and semiconductor device

 Technical field

 The present invention relates to both a memory device that accesses by designating a row address and a column address typified by SDRAM, and a memory device that accesses by designating only a row address typified by SRAM. The present invention relates to a memory controller accessible to a device and a semiconductor device integrated with the memory controller.

 Background art

 Conventionally, a memory controller of a memory device that specifies a row address and a column address typified by an SDRAM, and a memory controller of a memory device that specifies only a row address typified by an SRAM are known as respective memory devices. Due to the difference in the access interface, a method in which the semiconductor device is provided as a separate bus has been considered.

 [0003] Fig. 1 shows an example in which an SRAM 1122, a NOR flash memory 1123, and an SDRAM 1124 are connected to a memory controller 1120. Address bus 1102, clock signal (CLK) line 1103, write enable signal (WE) line 1104, read enable signal (RE) line 1105, byte enable signal (BE) line 1106, data bus 1107, SRAM 1122 and NOR type The flash memory 1123 is connected as a common external terminal.

 [0004] Also, an address bus 1111, a clock signal (CLK) line 1113, a clock enable signal (C1¾ :) line 1114, a write enable signal (WE) line 1115, a read enable signal (RE) line 1116, a bank The select signal (BA) line 1117, byte enable signal (BE) line 1118, and data bus 1121 are connected only to the SDRAM 1124.

 [0005] Chip select signal (CS) lines 1101, 1108, and 1112 are connected to the SRAM 1122, the NOR flash memory 1123, and the SDRAM 1124, respectively.

 [0006] In these configurations, the SDRAM 1124 and the SRAM 1122 or the NOR flash memory 1123 have a mechanism that allows simultaneous access to any of them! /

[0007] Further, in controlling a memory device to be accessed by specifying a row address and a column address, and a memory device to be accessed by specifying a row address, all the external devices other than the CS signal are controlled. A method of sharing the terminal as much as possible has been considered.

 [0008] On the other hand, as a representative of a memory device that specifies only a row address, attention has been paid to the similarity of controllers of flash memories, and signals are classified into signals that can be shared and those that are individually connected, and flexible memory access control has been realized. (See, for example, Patent Document 1). By the way, about sharing to SDRAM!

 Patent Document 1: JP-A-2003-131940

 Disclosure of the invention

 Problems to be solved by the invention

However, if a memory device controller that specifies a row address and a column address typified by SDRAM and a memory device controller that specifies only a row address typified by SRAM are separately mounted, the number of terminals increases. Problem arises. On the other hand, if the external terminals of the two types of memory devices described above are shared as much as possible, the SRAM side adopts a serial interface, while the SDRAM side adopts a knock-line method in which data and addresses are separated. In such cases, if switching between SRAM and SDRAM occurs frequently, the effect of pipeline control on the SDRAM side cannot be achieved. For this reason, a section in which the data bus cannot be used occurs, and a problem occurs in that the efficiency of memory access is reduced.

 An object of the present invention is to control a memory device capable of transferring data by designating a row address and a memory device capable of data transfer by designating a row address and a column address. An object of the present invention is to provide a memory controller and a semiconductor device capable of improving the use efficiency of a data bus while suppressing an increase in the number of terminals.

 Means for solving the problem

[0011] The memory controller controls a first memory device that can transfer data by specifying a single address, and a second memory device that can transfer data by specifying a row address and a column address. In this case, the configuration was such that the data bus was shared in a time-sharing manner, and other control lines were connected independently to each memory device.

The invention's effect According to the present invention, the first memory device capable of transferring data by designating a single address and the second memory device capable of transferring data by designating a row address and a column address are controlled. In this regard, it is possible to provide a memory controller capable of improving the use efficiency of the data bus while suppressing an increase in the number of terminals of the semiconductor device, and a semiconductor device including such a memory controller.

 Brief Description of Drawings

 FIG. 1 is a diagram showing a connection example of a conventional memory controller

 FIG. 2 is a diagram showing a connection example of a memory controller according to one embodiment of the present invention;

 [FIG. 3] Configuration diagram of the memory controller shown in FIG.

 [FIG. 4] Data configuration diagram of access requests stored in the FIFO shown in FIG.

 [FIG. 5] Timing chart when the access requests shown in FIG. 6 are executed without prioritizing

 FIG. 6 is a diagram showing an example of an access request stored in a FIFO

 [FIG. 7] Timing chart when the access requests shown in FIG. 6 are ranked

 BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, an embodiment in which the present invention is applied to a memory controller and a semiconductor device will be specifically described with reference to the drawings.

 FIG. 2 shows a connection example of a memory controller 121 according to the present embodiment, an SRAM 122 as a memory device, a NOR flash memory 123, and an SDRAM 124. An SRAM 122 and a NOR flash memory 123 are connected to the memory controller 121 as a memory device that can transfer data by specifying a row address, and a memory device that can transfer data by specifying a row address and a column address. Is connected to the SDRAM 124.

 [0016] The memory controller 121 is a memory interface (terminal portion) in an LSI as a semiconductor device, and functions to control read / write to a memory device in response to a memory access request from the LSI. For example, the CPU, DSP, DMA, accelerator, etc. issue an access request to the memory controller 121 due to the configuration of the LSI.

The memory controller 121 reads data from the SRAM 122, the NOR flash memory 123, and the SDRAM 124. The Z write is performed via the common data bus 107. The As the bus width of the data bus 107, a larger bus width is selected from the bus width used in the SRAM 122 and the NOR flash memory 123 and the bus width used in the SDRAM 124.

 As described above, by sharing the data bus 107 for memory devices having different interfaces, for example, a 32-bit data bus is separately provided from the memory controller 121 to each of the memory devices (122, 124). The number of 32 terminals can be reduced compared to the case of connection.

 The SRAM 122 and the NOR flash memory 123 share the address bus 102 and control lines (103, 104, 105, 106) for control signals excluding the chip select signal. Control lines (112 to 118) are connected independently! That is, address buses 102 and 111, synchronous clock signal (CLK) lines 103 and 118, write enable signal (WE) lines 104 and 115, read enable signal (RE) lines 105 and 116, byte enable signal (BE ) Lines 106 and 118 are connected to the respective memory devices, one set each, and chip select signal (CS) lines 101, 108, 112 are connected for each memory device. A bank select signal (BA) line 117 is connected to the SDRAM 124, and a data bus 107 is connected as a shared signal for each memory device.

 In the above configuration, a data access to the SRAM 122 or the NOR flash memory 123 and a data access to the SDRAM 124 are performed on the data bus 107 in a time division manner.

 Next, the configuration and operation of the memory controller 121 will be described with reference to FIG. As shown in FIG. 3, the memory controller 121 includes a FIFO memory 201, a memory control signal generation device 202, a next access control device 203, and an SDRAM access section determination device 204.

The FIFO memory 201 is a buffer that manages the order of memory access requests given from the LSI. FIG. 4 illustrates the specific contents of the memory access request. As shown in the drawing, the memory device includes an access length 301 to the memory device, read / write polarity information 302, address information 303, and access destination information 304 indicating the CS space of the memory device to be accessed. Yes. The FIFO memory 201 notifies the memory access request stored at the head to the memory control signal generation device 202 via the path 215.

 [0023] The memory control signal generation device 202 generates a control signal (other than a data bus signal) for accessing various memory devices according to the content of the memory access request. In addition, the memory control signal generation device 202 notifies the SDRAM access state determination device 204 of the access state of the SDRAM using the path 216. The access status of the SDRAM 124 includes information on the operation status of the SDRAM 124 such as precharge, self-refresh, and power down mode. Such access status information is notified to the SDRAM access section determination device 204 via the path 216.

 The access destination information 304, address information 303, and read / write polarity information of the access request stored in the FIFO memory 201 are transmitted to the SDRAM access section determination device 204 via the path 211. The SDRAM access section determination device 204 determines from the access destination information 304 that SDRAM access is continuous! /, And that the address information 303 requests continuous access to the same bank. 302 makes it possible to observe the transition of the access from the read access to the write access. Then, the SDRAM access section determination device 204 detects a data bus idle section in the case where the SDRAM access occurs continuously based on the information obtained through the paths 211 and 216, and uses the path 212 to Notify the access control device 203.

 The next access control device 203 compares the notified data bus idle period with the threshold value (the number of clocks) stored in the register 205. The threshold value stored in the register 205 is desirably the number of clocks corresponding to the minimum access length for the SRAM 122 or the NOR flash memory 123. The information is transmitted to the next access control device 203 via the route 217. In the idle period of the data bus, the number of clocks (the number of cycles) for determining whether or not the access to the SRAM 122 or the NOR flash memory 123 can be performed is stored.

When the data bus idle period is larger than the threshold, the order of the access requests accumulated in the FIFO memory 201 may be controlled. Specifically, the data bus idle section that occurs when SDRAM accesses occur consecutively is processed by the subsequent access request processing. If it can be filled, an access request for the subsequent SRAM 122 or NOR flash memory 123 is moved up to the top. The order of the access request of the FIFO 201 is transmitted to the next access control device 203 via the path 213, and the control of the access request is transmitted to the FIFO 201 via the path 214.

 Here, with reference to FIG. 5, a description will be given of the occurrence of a data bus idle section when SDRAM access is continuous. The time chart shown in FIG. 5 shows the use status of the data bus 107 when the access requests are accumulated in the FIFO memory 201 in the order shown in FIG. ing. Particularly, a case where different row addresses are successively accessed in the same bank will be exemplified. Such a case is one of typical examples in which a data bus idle section occurs.

 When an access request to the SDRAM 124 is located at the beginning of the FIFO memory 201, the memory controller 121 selects the SDRAM 124 by the chip select signal (CS) line 112 and uses the data bus 107 to access the SDRAM 124 It can be so. Then, a row address is issued by the SDRAM command Activate, and after a predetermined time elapses, a column address is issued by the SDRAM command read (A). After a lapse of a predetermined time from the issuance of the column address, the head (AO) of the read data read from the target bank (for example, bank A) is output on the data bus 107. The remaining three bursts of read data (A1 to A3) are output on the data bus 107 continuously from the first read data (AO).

 The time required from the issuance of a row address to the issuance of a column address and the time required to issue a column address and the time required for the head data to appear on the data node 107 are fixed according to the system design. Value.

[0030] The SDRAM 124 specifies an address by a combination of a row address and a column address. It takes one clock each to issue a row address and a column address. Therefore, when newly accessing the SDRAM 124, the total time of the above-mentioned fixed value and the time required for address issuance is the data bus idle section. As shown in FIG. 5, the first data bus idle period occurs before the first read data AO of the SDRAM 124 is output to the data bus 107. The data read from the target bank into the buffer is returned to the original position by the SDRAM command, precharge.

 The example shown in FIG. 5 shows a case where access requests for accessing different row addresses in the same bank A of the SDRAM 124 are continuous. That is, in the access order shown in FIG. 6, the second access request is an access request that accesses the same bank A as the first access request and a different row address.

 By the way, the SDRAM 124 cannot issue an Activate to select a different row address in the same bank unless the SDRAM 124 is precharged and capable. Therefore, the memory control signal generation device 202 issues a precharge command to perform precharge, and selects a row address in synchronization with the clock at the next timing when the last read data (A3) is output to the data bus 107. Issue Activate.

 In the execution of the second access request in FIG. 6, a row address is issued by Activate, a column address is issued by read (B), and then read data (B 0 to B 3) is placed on the data bus 107. Output continuously.

 As described above, even when the second access request is executed, even if a different row address is accessed in the same bank A, it is necessary to issue a row address and a column address after precharging. And a data bus idle section similar to the above occurs.

 Next, in FIG. 6, the third access request, which is an access request to the SRAM 122, comes to the top of the SFIFO memory 201. When the access (read B) to the SDRAM 124 is completed, the memory controller 121 activates the chip select signal (CS) line 101 for the SRAM 122 in synchronization with the next clock, and also writes the SRAM command “write” (C). Outputs a write address (single address) on the address bus 102. In the case of the SRAM 122, the address specification at the time of access needs to specify only a single address, and there is no space unlike the address specification for the SDRAM 124. In the SRAM 122, the write data C is output onto the data bus 107 simultaneously with the write request, and the data C is written into the SRAM 122.

Next, an access request to the SRAM 122, which is the fourth access request in FIG. 6, comes to the head of the FIFO memory 201. Then, after the execution of the third access request is completed In synchronization with this clock, a read address by read D is issued, and read data D is read from the read address of the SRAM 122 and output on the data bus 107.

 [0038] As described above, in accessing the SDRAM 124, the row address is specified, then the column address is specified, and then the use of the data node 107 is started. However, a band (data bus idle section) occurs.

 In the present embodiment, the data bus idle section that occurs when accessing the SDRAM 124 is determined, and the time width for interrupting the subsequent access request to the SRAM 122 or the NOR flash memory 123 is determined in the data bus idle section. If so, the order of the access requests in the FIFO memory 201 is manipulated to execute the access request to the subsequent SRAM 122 or NOR type flash memory 123 first.

 FIG. 7 is a time chart when the order of access requests in the FIFO memory 201 is manipulated. The order of the access requests initially stored in the FIFO memory 201 is as shown in FIG. Analyzing the contents and order of the access requests shown in FIG. 6, as shown in FIG. 5A and FIG. 5B, the SDRAM 124 is accessed by the first access request and different row addresses of the same bank A are accessed. It is found that a data bus idle period occurs at each of the access requests.

 The SDRAM access section determination device 204 fetches the access request data stored in the FIFO memory 201 and detects a data bus idle section at the time of accessing the SDRAM 124 from the access request to the SDRAM 124. Further, the memory control signal generation device 202 manages and controls each operation timing of the precharge, the self refresh, and the power down mode in the SD RAM 124. If there is no subsequent SDRAM access, a section occurs in which the precharge is issued and the power bus 107 is not used. Also, when returning from the self-refresh or power-down mode, a section in which the data bus 107 is not used occurs. In this way, an event in which an interval in which the data bus 107 is not used may occur is notified to the SDRAM access interval determination device 204 as an SDRAM access status.

The SDRAM access section determination device 204 detects the data bus idle section during the SDRAM access shown in FIG. 5 from the access request information of the FIFO memory 201 shown in FIG. Then, the detected data bus idle section information is notified to the next access control device 203. . In addition, the SDRAM access section determination device 204 determines whether or not there is a section in which the data bus 107 is not used during the access period of the SDRAM 124 based on the SDRAM access status received from the memory control signal generation device 202. If an unused section, that is, a data bus idle section occurs, the access control device 203 is notified of the next time.

 The next access control device 203 compares the threshold value previously stored in the register 205 with the data bus idle period notified from the SDRAM access period determination device 204. In the example shown in FIG. 5, each of the first data bus idle section and the second data bus idle section is larger than the threshold. That is, the third access request (write C) in FIG. 6 can be executed earlier in the first data bus idle section shown by the left arrow in FIG. 7, and the second access request shown by the right arrow in FIG. In the data bus idle period, the fourth access request (read D) in FIG. 6 can be executed earlier.

 Therefore, the next access control device 203 moves the third access request (write C) in FIG. 6 to the top of the FIFO memory 201 and transfers the fourth access request (read D) in FIG. Go to the third position immediately after the request (lead A). In this way, the order operation is performed so that the data bus idle section generated by the preceding SD RAM access request is filled with the subsequent SRAM access request or NOR type flash memory access request. By sequentially executing access requests in the order after the order operation, the use efficiency of the data bus 107 can be increased as shown in FIG.

 According to the present embodiment as described above, in the case where an inexpensive NOR flash memory or an SRAM in which an inexpensive SDRAM is frequently used is infrequently used, the efficiency of use of a data bus is increased. Performance can be maintained, and an increase in the number of terminals can be suppressed.

 Note that the above configuration is an example, and does not limit the memory devices to be configured.

 If a dedicated control signal depending on the device to be used is required, a configuration for adding the signal is also within the scope of the present invention.

In the above description, the case where one memory controller 121 is used has been described. However, a plurality of the same memory controllers as those in the above embodiment are provided on a semiconductor device, and each memory controller has a data bus. May be shared in a time-sharing manner. In this case, memory accesses are executed in cooperation with each other so that accesses between memory controllers do not conflict with each other. The order of the access requests stored in the FIFO in the controller may be operated in accordance with the algorithm described above. Furthermore, one or more memory controllers capable of controlling a memory device capable of transferring data by designating a single address on such a semiconductor device are provided, and each controller operates in a cooperative manner. You can.

[0048] The present specification is based on Japanese Patent Application No. 2004-117918 filed on April 13, 2004. All of this content is included here.

 Industrial applicability

The present invention relates to controlling a memory device capable of transferring data by designating a row address and a memory device capable of transferring data by designating a row address and a column address. It is possible to increase the efficiency of using the data bus while suppressing an increase in the number of terminals, and it is applicable to a memory controller and a semiconductor device.

Claims

The scope of the claims  [1] A memory controller for controlling a first memory device capable of transferring data by designating a single address and a second memory device capable of transferring data by designating a row address and a column address, A memory controller in which a data bus for each memory device is shared in a time-division manner, and control lines connected to each memory device are independent.  2. The memory controller according to claim 1, wherein the bus width of the data bus selects a larger one of a bus width of the first memory device and a bus width of the second memory device.  [3] A FIFO memory that manages an access request to each of the memory devices to be accessed, an access section determination unit that detects the start and end of a section in which the second memory device cannot access, and If it is possible to execute an access request to the subsequent first memory device stored in the FIFO memory during the access disabled section detected as inaccessible by the section determination unit, the access request to the first memory device will be the first 2. The memory controller according to claim 1, further comprising: an access control unit configured to change the order of access requests in the FIFO memory so that the order of the access requests is changed.  [4] The access request stored in the FIFO memory includes a type of a memory device to be accessed, an access length, read / write polarity, and an address. 4. The memory controller according to claim 3, wherein a start and an end of a section in which the second memory device disables access are detected based on the included information.  [5] The access section determination unit is configured to determine, for the second memory device, the second memory device based on operation states of a precharge, a self-refresh, and a power-down mode and information included in the access request. The memory controller according to claim 4, wherein the memory controller detects a section inaccessible to the controller.  [6] The access control section compares the inaccessible section detected by the access section determining section with a preset threshold, and if the detected inaccessible section exceeds the threshold, the access request is issued. 4. The memory controller according to claim 3, wherein the order is changed.  7. A semiconductor device comprising a plurality of the memory controllers according to claim 1, wherein the memory controllers operate in cooperation with each other.