JP5087831B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to, for example, a semiconductor device having a plurality of element regions formed on a semiconductor substrate and a method for manufacturing the same.

  As a conventional technique, there is a peripheral isolation structure used for a reverse blocking element using an IGBT (Insulated Gate Bipolar Transistor) (Non-Patent Document 1).

Proceedings of 2004 International Symposium on Power Semiconductor Devices & ICs, Kitakyushu p.121-124

  However, in the above prior art, in order to prevent a leakage current path, it is necessary to form an isolation region made of a deep (for example, 120 μm) semiconductor between elements, so that the process for forming the isolation region is complicated. In addition, since the surface area of the isolation region is increased, the effective element area is reduced. Further, when the peripheral structure is formed by junction isolation, the back surface and the periphery are surrounded by a P-type region, which increases the number of minority carriers injected at the time of forward bias of the PN junction, which causes deterioration of switching characteristics. It was.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device having a simple process for forming an isolation region and a large element effective area, and a manufacturing method thereof.

In order to achieve this object, in the present invention, the semiconductor substrate and the isolation region are formed from conductive materials having different band gaps, and a heterojunction having monopolar characteristics is formed at the interface between the semiconductor substrate and the isolation region. .

  In the present invention, since it is not necessary to form a deep isolation region between elements, the process for forming the isolation region is simplified, and the area of the surface of the isolation region is reduced, so that the effective area of the element is increased. .

(First embodiment)
A first embodiment of the present invention will be described with reference to FIG. First, the configuration will be described. N− type SiC regions 1 a, 1 b, 1 c (first conductivity type semiconductor substrate) are formed on the first main surface side of the P + type poly Si substrate region 2 (support substrate). Here, the N− type SiC regions 1 a, 1 b and 1 c may be heteroepitaxially grown on the P + type poly Si substrate region 2. As another method, a P + type poly Si substrate region 2 may be formed on the second main surface side with respect to the N− type SiC regions 1a, 1b, and 1c prepared in advance. Alternatively, bonding of a SiC substrate and a Si substrate may be used. The polytype of the N-type SiC regions 1a, 1b, and 1c may be 4H, 6H, 3C, or the like. N-type SiC regions 1a, 1b, 1c have a thickness of 0. A typical value is between several μm and several tens of μm. Functional elements such as switch elements and circuits are formed in the N− type SiC regions 1a, 1b and 1c. As an example, a power MOSFET can be considered as the switch mechanism, which will be described later in detail. A back electrode 3 is formed on the second main surface side of the P + type poly-Si substrate region 2. Grooves that reach the P + type poly Si substrate region 2 from the first main surface side of the N− type SiC regions 1a, 1b, and 1c are formed, and isolation regions 4a and 4b are formed so as to fill the inside of the grooves. . The groove can be easily formed by dry etching such as RIE, and the separation regions 4a and 4b can be realized by forming a film of poly-Si so as to fill the inside of the groove. As an example, the isolation regions 4a and 4b may be made of poly-Si doped into P + type (high concentration second conductivity type). In the present embodiment, the potential of back electrode 3 and isolation regions 4a and 4b are connected by an external electrode so as to be equipotential, and are fixed to, for example, the ground potential. The connection of the back electrode 3 may be left floating. In that case, it is possible to fix to the ground potential through the isolation regions 4a and 4b. In addition, as shown in FIG. 2, an example in which an insulating film 5 is formed instead of the back electrode 3 on the second main surface side of the P + type poly-Si substrate region 2 is also conceivable. It is possible to fix to the ground potential through the regions 4a and 4b.

  In the method of manufacturing the semiconductor device of the present embodiment, a groove reaching the P + type poly-Si substrate region 2 from the first main surface side of the N− type SiC regions 1a, 1b, 1c is provided, and the groove is formed inside the groove. The isolation regions 4a and 4b are formed by embedding a material having a band gap different from the material of the N− type SiC regions 1a, 1b and 1c, for example, P + type poly-Si, and the N− type SiC regions 1a, 1b and 1c are separated from the isolation region 4a. Heterojunction is formed at the interface with 4b.

  Next, the operation of the present embodiment will be described. As described above, each of the N− type SiC regions 1a, 1b, and 1c functions as an isolated element region in a state where the P + type poly Si substrate region 2 and the isolation regions 4a and 4b are fixed to the ground potential. Heterojunctions resulting from different band gaps are formed at the interfaces between the isolation regions 4a and 4b and the N-type SiC regions 1a, 1b and 1c. When the potential of each element region rises, the reverse breakdown voltage of the diode due to the heterojunction is high, so that each element region is electrically isolated. In particular, when the isolation regions 4a and 4b are P + type, the barrier height at the heterojunction is high, and high breakdown voltage isolation is possible.

  Thus, in the present embodiment, high breakdown voltage element isolation by heterojunction is possible, interaction between a plurality of element regions is reduced, and noise resistance performance of the semiconductor device can be improved. Further, in the conventional complete isolation by the insulating film, there is a problem that heat is generated in the element region and the temperature of the element region is increased to an allowable value or more. Since relatively good poly-Si is used, element isolation can be performed while maintaining good thermal conductivity between the element regions. Further, it is not necessary to form a deep isolation region between the element regions, and the trenches in the isolation regions 4a and 4b have a thickness of 0. Since it can be realized with several μm to several tens of μm, the process for forming the isolation regions 4a and 4b is simplified and the surface area of the isolation region is reduced, so that the effective element area is increased. In addition, when used as a switch element, the on-resistance normalized by area can be sufficiently reduced. In addition, since there is a barrier at the heterointerface, a monopolar operation in which minority carrier injection due to a forward bias does not occur. Therefore, when used as a switch element, switching characteristics are good. Also, in the transient state where the potential of the element region changes rapidly, the monopolar operation in which minority carrier injection due to the forward bias does not occur, so that the element isolation can be performed without hindering the high-speed operation of the element region. is there.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIG. First, the configuration will be described. P-type base regions 9a and 9b are formed in part of the N-type SiC regions 1a and 1b on the first main surface side. N + type source regions 11a and 11b (source regions having a high concentration of the first conductivity type) and P + type base contact regions 10a and 10b are formed on the surface on the main surface side. Further, a source electrode 12a in contact with the P + type base contact region 10a and the N + type source region 11a is formed, and a source electrode 12b in contact with the P + type base contact region 10b and the N + type source region 11b is formed. On the first main surface side of the P-type base regions 9a and 9b and on the surface, gate electrodes 8a and 8b are formed in contact with the N + type source regions 11a and 11b and via the gate insulating films 7a and 7b. Has been. N + type drain contact regions 13a and 13b are formed at positions spaced apart from some of the gate electrodes 8a and 8b on the first main surface side of the N− type SiC regions 1a and 1b, and the N + type drain contact regions 13a and 13b are formed. Drain electrodes 14a and 14b in contact with are formed. As described above, the lateral power MOSFET having the N + type source regions 11a and 11b, the gate insulating films 7a and 7b, and the N + type drain regions 13a and 13b is formed.

  In the semiconductor device shown in FIG. 3 as well, high breakdown voltage element isolation by heterojunction is possible, the interaction between a plurality of element regions can be reduced, and the noise resistance performance of the semiconductor device can be improved. It is possible to perform element isolation while maintaining good thermal conductivity between element regions. Further, the process for forming the isolation region 4a is simplified, and the surface area of the isolation region is reduced, so that the effective element area is increased.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG. First, the configuration will be basically the same as the configuration described in the first embodiment. If only different parts are described, the N-type SiC regions 1a, 1b, 1c An insulating film 6 is formed. The insulating film 6 can also be formed by depositing an insulating material, and each N-type SiC region 1a, 1b, 1c can be heteroepitaxially grown on the insulating substrate. You may comprise by bonding. Isolation regions 4a and 4b are formed to reach insulating film 6 from the first main surface side of each of N-type SiC regions 1a, 1b and 1c. The isolation regions 4a and 4b are fixed to the ground potential.

  Next, the operation of the present embodiment will be described. As described above, each of the N-type SiC regions 1a, 1b, and 1c functions as an isolated element region while the isolation regions 4a and 4b are fixed to the ground potential. Further, the element region is insulated by the insulating film 6 in the vertical direction, and complete isolation by the insulating film 6 is possible in the vertical direction. In addition, the element region can be separated with high breakdown voltage by a heterojunction at the interface between the isolation regions 4a and 4b and the N-type SiC regions 1a, 1b and 1c in the lateral direction. Thus, the interaction between a plurality of element regions is reduced, and the noise resistance performance of the semiconductor device can be improved. In addition, the process for forming the isolation region 4a is simplified, and the surface area of the isolation region is reduced, so that the effective element area is increased.

(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIG. The basic configuration of the isolation structure is the same as that described in the first embodiment, and the basic configuration of the lateral power MOSFET shown in FIG. 3 in the element region formed by the N-type SiC regions 1a and 1b. A horizontal power MOSFET having a similar structure is formed. The power MOSFETs formed in the two element regions have a symmetric structure, and the P-type base regions 9a and 9b and the P + type base contact regions 10a and 10b are in contact with the isolation region 4a, and the isolation regions 4a and P + type Source electrodes 12 in contact with the base contact regions 10a and 10b and the N + type source regions 11a and 11b are formed. The heterojunction between the P + type poly Si substrate region 2 and the N− type SiC regions 1a and 1b and the heterojunction between the isolation region 4 and the N− type SiC regions 1a and 1b are the main currents at which the switch mechanism is turned on / off. It is a diode that blocks the reverse current. When this configuration is represented by a circuit diagram, the configuration shown in FIG. 6 is obtained, and the common source electrode S of the two power MOSFETs 21 and 22 is at the ground potential. Also, the drain terminals D1 and D2 and the gate terminals G1 and G2 are independent.

  Such a semiconductor device is used for, for example, a plurality of low-side switches for driving a load, and a plurality of switch mechanisms common to the source ground can be densely configured, and the area of the isolation region can be further reduced. .

  Next, a switch mechanism using a heterojunction will be described with reference to FIG. The isolation region 4a and the hetero semiconductor regions 17a and 17b are formed of a common P + type poly-Si. Further, N-type hetero semiconductor regions 16a and 16b are formed in contact with the hetero semiconductor regions 17a and 17b. The gate electrodes 19a and 19b are in contact with the N-type hetero semiconductor regions 16a and 16b and through the gate insulating films 18a and 18b. The source electrode 12 is formed in contact with the hetero semiconductor regions 17a and 17b, and the gate electrodes 19a and 19b are insulated from the source electrode 12 by the interlayer insulating films 20a and 20b. In addition, drain electrodes 14a and 14b are formed at positions spaced from the gate electrodes 19a and 19b on the first main surface side of the N-type SiC regions 1a and 1b. The switch mechanism using two heterojunctions has a symmetrical structure, and the basic operation is the same as that of a power MOSFET.

  In this semiconductor device, since the isolation region 4a and the hetero semiconductor regions 17a and 17b are formed of a common P + type poly-Si, the element isolation configuration and the switch mechanism using the heterojunction are densely configured. And the area of the isolation region can be reduced.

(Fifth embodiment)
A fifth embodiment of the present invention will be described with reference to FIG. N− type SiC regions 1 a and 1 b are formed on the first main surface side of the P + type poly Si substrate region 2. Here, the N− type SiC regions 1 a and 1 b may be heteroepitaxially grown on the P + type poly Si substrate region 2. As another method, a P + type poly-Si substrate region 2 may be formed on the second main surface side with respect to the N− type SiC regions 1a and 1b prepared in advance. Alternatively, the SiC substrate and the Si substrate may be bonded together. The polytype of the N-type SiC regions 1a and 1b may be 4H, 6H, 3C, or the like. N-type SiC regions 1a and 1b have a thickness of 0. A typical value is between several μm and several tens of μm. In this N− type SiC region 1b, functional elements such as a switch element and a circuit are formed, but the details are omitted here. A back electrode 3 is formed on the second main surface side of the P + type poly-Si substrate region 2. Further, a groove reaching the P + type poly Si substrate region 2 from the first main surface side of the N− type SiC regions 1a, 1b is formed, and an isolation region 4a is formed so as to fill the inside of the groove. The groove can be easily formed by dry etching such as RIE, and the isolation region 4a can be realized by depositing poly-Si so as to fill the inside of the groove. As an example of this isolation region 4a, poly Si doped into P + type can be considered. In this embodiment, the back electrode 3 and the isolation region 4a are connected by an external electrode so as to be equipotential, and are fixed to, for example, the ground potential.

  Further, in the method of manufacturing the semiconductor device of the present embodiment, a groove reaching the P + type poly Si substrate region 2 from the first main surface side of the N− type SiC regions 1a and 1b is provided, and the N− The isolation region 4a is formed by embedding a material having a band gap different from that of the type SiC regions 1a and 1b, for example, P + type poly-Si, and a heterojunction is formed at the interface between the N− type SiC regions 1a and 1b and the isolation region 4a. To do.

  A feature of the present embodiment is that a separation region 4a is formed in the peripheral portion (outer peripheral portion) of the semiconductor substrate, and the dicing side surface 15 and the element region are separated by the separation region 4a. By the way, generally, at the final stage of chip manufacture, the chip is cut out from the wafer. For this reason, the chip outer peripheral portion has a dicing side surface 15 having a large crystal strain and a high crystal defect density. When an electric field from the element region is applied to this region, carriers that are constantly generated due to crystal defects are transported by the electric field and become a large leakage current, so that the breakdown voltage in the reverse direction is lowered. . For this reason, separation from the element region on the dicing side surface 15 is indispensable, and conventionally, a large area is required to form an isolation region by deep P-type impurities. On the other hand, in this embodiment, the heterojunction enables a high breakdown voltage and low leakage current separation structure, and further has an effect of reducing the chip area. In addition, since there is a barrier at the heterointerface, a monopolar operation in which minority carrier injection due to a forward bias does not occur. Therefore, when used as a switch element, switching characteristics are good. Furthermore, in a transient state where the potential of the element region changes rapidly, monopolar operation in which minority carriers are not injected due to forward bias in the isolation region 4a enables element isolation without hindering high-speed operation of the element region. There is an effect that.

(Sixth embodiment)
A sixth embodiment of the present invention will be described with reference to FIG. N− type SiC regions 1 a and 1 b are formed on the first main surface side of the P + type poly Si substrate region 2. Here, the N− type SiC regions 1a and 1b may be heteroepitaxially grown on a P + type poly Si substrate region 2 as a support substrate. As another method, a P + type poly-Si substrate region 2 may be formed on the second main surface side with respect to the N− type SiC regions 1a and 1b prepared in advance. Alternatively, the SiC substrate and the Si substrate may be bonded together. The polytype of the N-type SiC regions 1a and 1b may be 4H, 6H, 3C, or the like. Further, the thickness of the N-type SiC regions 1a and 1b is 0. A typical value is between several μm and several tens of μm. The N− type SiC region 1 a is in contact with the dicing side surface 15, and a switch mechanism using a heterojunction described in Japanese Patent Application Laid-Open No. 2003-318398 is formed in the N− type SiC region 1 b. A back electrode 3 is formed on the second main surface side of the P + type poly-Si substrate region 2. Further, a groove reaching the P + type poly-Si substrate region 2 from the first main surface side of the N− type SiC region 1b is formed, and an isolation region 4a is formed so as to fill the inside of the groove. The groove can be easily formed by dry etching such as RIE, and the isolation region 4a can be realized by depositing poly-Si so as to fill the inside of the groove. As an example of this isolation region 4a, poly Si doped into P + type can be considered. Further, a hetero semiconductor region 23 made of polycrystalline Si is formed on the first main surface side of the N-type SiC region 1b. SiC and polycrystalline Si have different band gaps, different electron affinities, and N-type. A heterojunction is formed at the interface between SiC region 1 b and hetero semiconductor region 23. A gate electrode 25 is formed through a gate insulating film 24 adjacent to the junction between the N − type SiC region 1 b and the hetero semiconductor region 23. The hetero semiconductor region 23 is connected to the source electrode 27. The gate electrode 25 is insulated and separated from the source electrode 27 by the interlayer insulating film 26. The back electrode 3 functions as a drain electrode which is a main terminal. Further, the isolation region 4a reaches the P + type poly Si substrate region 2 at the bottom thereof, and therefore has the same potential as the P + type poly Si substrate region 2.

  Next, the operation will be described. A switch mechanism including a reverse blocking diode for blocking reverse current is formed in the N − type SiC region 1b which is the element region, and the main current is turned on / off by the switch mechanism. In the present embodiment, the heterojunction formed between the P + type poly-Si substrate region 2 and the N− type SiC region 1b functions as a diode that blocks reverse current. The experimental results obtained through diligent efforts indicate that it is better to increase the barrier height of the P + type hetero interface in order to obtain diode characteristics with high breakdown voltage and low leakage current. Further, when such a heterojunction is used, minority carriers are not injected from the heterointerface when a forward current flows. By adopting the configuration of the present embodiment, a reverse blocking diode having a high breakdown voltage and a low leakage current can be formed in series with the switch mechanism, and the isolation region 4a also functions as a reverse blocking diode. In addition, by forming two reverse blocking switch mechanisms with built-in reverse blocking diodes so that the polarities are reversed, a bidirectional switch mechanism that can easily turn on / off current in both directions is provided. Can be formed. Such a bidirectional switch mechanism is an essential element circuit for applications such as a matrix converter, and when the L load such as a motor is driven according to the present invention, since minority carrier injection does not occur in the forward direction, reverse recovery characteristics are obtained. Are better. Therefore, it is advantageous for reducing the size and cost of a power electronics system represented by a matrix converter. Further, as a specific operation of the present embodiment, since the isolation region 4a and the N− type SiC regions 1a and 1b also form a heterojunction, electrical insulation between the element region 4a and the dicing side surface 15 is performed. Can be taken. Further, when the heterojunction that exhibits the reverse blocking function is forward-biased, the reverse recovery charge at the time of reverse recovery of the element when driving the L load or the like due to the monopolar operation in which minority carrier injection does not occur. As a result, the switching loss can be greatly reduced.

  In addition, this invention is not limited to the above embodiment, You may combine either of the above embodiment.

  In the above-described embodiment, the switch mechanism using the lateral power MOSFET and the heterojunction is formed, but another switch mechanism may be formed. For example, a JFET, MESFET, or bipolar transistor may be used. When a semiconductor substrate made of GaN is used, a channel structure using a two-dimensional electron gas cloud may be used. In the above-described embodiments, the N-type SiC regions 1a, 1b, and 1c are used as the semiconductor substrate. However, GaN or diamond, which is a wide band gap material excellent in power device applications, may be used as the semiconductor substrate. Absent. In the above-described embodiment, the insulating films 5 and 6 are used as the supporting substrate. However, an insulating substrate or a semi-insulating substrate may be used as the supporting substrate.

1 is a cross-sectional structure diagram of an element portion according to a first embodiment of the present invention. It is another element cross-section figure of the 1st Embodiment of this invention. It is element part sectional drawing of the 2nd Embodiment of this invention. It is element part sectional drawing of the 3rd Embodiment of this invention. It is element part sectional drawing of the 4th Embodiment of this invention. It is an equivalent circuit diagram explaining the 4th Embodiment of this invention. It is another element part cross-section figure of the 4th Embodiment of this invention. It is element part sectional drawing of the 5th Embodiment of this invention. It is element part sectional drawing of the 6th Embodiment of this invention.

Explanation of symbols

1a, 1b, 1c... N-type SiC region
2 ... P + type poly-Si substrate region
3 ... Back electrode
4a, 4b ... separation region
5 ... Insulating film
6 ... Insulating film
7a, 7b ... Gate insulating film
8a, 8b ... gate electrodes
9a, 9b ... P-type base region 10a, 10b ... P + type base contact region 11a, 11b ... N + type source region 12, 12a, 12b ... Source electrode 13a, 13b ... N + type drain contact region 14a, 14b ... Drain electrode
DESCRIPTION OF SYMBOLS 15 ... Dicing side surface 16a, 16b ... N-type hetero semiconductor region 17a, 17b ... P + type hetero semiconductor region 18a, 18b ... Gate insulating film 19a, 19b ... Gate electrode 20a, 20b ... Interlayer insulating film
23 ... Heterogeneous semiconductor region
24. Gate insulating film
25 ... Gate electrode
26. Interlayer insulating film
27 ... Source electrode

Claims (11)

In a semiconductor device having a plurality of element regions formed in a semiconductor substrate and having an isolation region that electrically insulates between the element regions,
A semiconductor device, wherein the semiconductor substrate and the isolation region are formed of conductive materials having different band gaps, and a heterojunction having a monopolar characteristic is formed at an interface between the semiconductor substrate and the isolation region. The semiconductor substrate is made of silicon carbide, GaN or diamond semiconductor device according to claim 1, wherein the isolation region, wherein the silicofluoride Motoma others are formed of polycrystalline silicon. The semiconductor substrate is formed on the first main surface side of the supporting substrate, the isolation region according to claim 1 or 2, characterized in that it reached the supporting substrate from the first main surface side of the element region Semiconductor device. The support substrate is polycrystalline silicofluoride hydride Rannahli The semiconductor device according to claim 3, characterized in that to form a heterojunction between the supporting substrate and the element region. 4. The semiconductor device according to claim 3 , wherein the support substrate is made of an insulating film, an insulating substrate, or a semi-insulating substrate. 2. A switch mechanism for switching on / off of a main current on a first main surface side of an element region of a first conductivity type, wherein the isolation region is a high-concentration second conductivity type. 6. The semiconductor device according to any one of 5 to 5 . A switch mechanism for switching on / off of a main current on the first main surface side of the element region of the first conductivity type, wherein the separation region and the support substrate are of a high concentration second conductivity type; The semiconductor device according to claim 3 or 4 . The switch mechanism has a source region of a high concentration first conductivity type, the source region is connected so as to be electrically at the same potential as the source electrode and the isolation region, and a drain electrode is connected to the first main surface The semiconductor device according to claim 7 , wherein the semiconductor device is formed on a side. The heterojunction between the support substrate and the element region and the heterojunction between the isolation region and the element region are diodes that block a reverse current of a main current that is turned on / off by the switch mechanism. The semiconductor device according to claim 7 . The switch mechanism includes: a hetero semiconductor region heterojunctioned on the element region; a gate electrode disposed via a gate insulating film adjacent to a junction between the element region and the hetero semiconductor region; The semiconductor device according to claim 7 , further comprising a source electrode in contact with the terror semiconductor region. In a method of manufacturing a semiconductor device, wherein a semiconductor substrate is formed on a first main surface side of a support substrate, a plurality of element regions are formed in the semiconductor substrate, and an isolation region that electrically insulates the element regions is provided.
A groove reaching the support substrate from the first main surface side of the semiconductor substrate is provided, and the isolation region is formed by embedding a conductive material having a band gap different from the material of the semiconductor substrate in the groove, A method of manufacturing a semiconductor device, comprising forming a heterojunction having monopolar characteristics at an interface between the semiconductor substrate and the isolation region.

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