JP7030665B2 - Semiconductor device - Google Patents

Description

Embodiments of the present invention relate to semiconductor devices.

Silicon carbide (SiC) is expected as a material for next-generation semiconductor devices. Silicon carbide has excellent physical properties such as a bandgap of about 3 times, a breaking electric field strength of about 10 times, and a thermal conductivity of about 3 times that of silicon. By utilizing this characteristic, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) capable of high withstand voltage, low loss, and high temperature operation can be realized.

The vertical MOSFET using silicon carbide has a pn junction diode as a parasitic built-in diode. For example, MOSFETs are used as switching elements connected to inductive loads. In this case, even when the MOSFET is off, it is possible to pass a reflux current by using a pn junction diode.

However, when a reflux current is passed using a pn junction diode, stacking defects may grow in the silicon carbide layer due to the recombination energy of the carrier, and the on-resistance of the MOSFET may increase. Increasing the on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET.

Further, as a structure for reducing the on-resistance of a MOSFET using silicon carbide, there is a trench gate type MOSFET in which a gate electrode is provided in a trench. In the trench gate type MOSFET, the on-resistance is reduced by increasing the channel density per unit area.

However, in the trench gate type MOSFET, a structurally high electric field is applied particularly to the gate insulating layer at the bottom of the trench. Therefore, the dielectric breakdown resistance of the gate insulating layer may decrease. A decrease in gate dielectric breakdown resistance leads to a decrease in MOSFET reliability.

Japanese Unexamined Patent Publication No. 2017-11261

An object to be solved by the present invention is to provide a semiconductor device capable of improving reliability.

The semiconductor device of the embodiment has a silicon carbide layer having a first surface and a second surface facing the first surface, and a first portion provided in the silicon carbide layer and extending in the first direction. A trench, a second trench provided in the silicon carbide layer and extending in the first direction, a first gate electrode provided in the first trench, and the second. A second gate electrode provided in the trench, a first gate insulating layer provided between the first gate electrode and the silicon carbide layer, and the second gate electrode and the silicon carbide. A second gate insulating layer provided between the layers, a first conductive type first silicon carbide region provided in the silicon carbide layer, and the silicon carbide layer provided above. A plurality of pieces located between the first silicon carbide region and the first surface, located between the first trench and the second trench, and arranged apart from each other in the first direction. The second silicon carbide region of the second conductive type and the third of the first conductive type provided in the silicon carbide layer and located between the second silicon carbide region and the first surface. Silicon Carbide Region, located in the Silicon Carbide Layer, located between the two Second Silicon Carbide Regions, and between the first trench and the first Silicon Carbide Region. The second conductive type fourth silicon carbide region in contact with the second silicon carbide region and the second silicon carbide region provided in the silicon carbide layer and located between the two second silicon carbide regions. A second conductive type fifth silicon carbide region located between the trench 2 and the first silicon carbide region and in contact with the second silicon carbide region, and the first surface of the silicon carbide layer. A first electrode provided on the side of the above, which is in contact with the third silicon carbide region and is in contact with the first silicon carbide region between the two second silicon carbide regions, and the first electrode of the silicon carbide layer. Includes a MOSFET comprising a second electrode provided on the side of the second surface.

The schematic sectional view of the semiconductor device of 1st Embodiment. The schematic plan view of the semiconductor device of 1st Embodiment. The schematic sectional view of the semiconductor device of 1st Embodiment. The schematic sectional view of the semiconductor device of 1st Embodiment. The schematic sectional view of the semiconductor device of 1st Embodiment. The schematic sectional view of the semiconductor device of 1st Embodiment. The schematic plan view of the semiconductor device of the modification of 1st Embodiment. The schematic sectional view of the semiconductor device of the modification of 1st Embodiment. The schematic sectional view of the semiconductor device of 2nd Embodiment. The schematic plan view of the semiconductor device of 2nd Embodiment. The schematic sectional view of the semiconductor device of 3rd Embodiment. The schematic sectional view of the semiconductor device of 3rd Embodiment. The schematic sectional view of the semiconductor device of 3rd Embodiment. The schematic sectional view of the semiconductor device of 4th Embodiment. The schematic sectional view of the semiconductor device of 4th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members and the like are designated by the same reference numerals, and the description of the members and the like once described will be omitted as appropriate.

Further, when the notations of n ⁺ , n, n ⁻ and p ⁺ , p, p ⁻ are used in the following description, these notations represent the relative high and low of the impurity concentration in each conductive type. That is, n ⁺ indicates that the concentration of n-type impurities is relatively higher than that of n, and n ⁻ indicates that the concentration of n-type impurities is relatively lower than that of n. Further, p ⁺ indicates that the concentration of p-type impurities is relatively higher than that of p, and p ⁻ indicates that the concentration of p-type impurities is relatively lower than that of p. In some cases, n ⁺ type and n ^- type are simply referred to as n-type, p ⁺ type and p ^- type are simply referred to as p-type.

The impurity concentration can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry). Further, the relative high and low of the impurity concentration can be determined from, for example, the high and low of the carrier concentration obtained by SCM (Scanning Capacitance Microscopy). Further, the distance such as the depth of the impurity region can be obtained by, for example, SIMS. Also. Distances such as the width and depth of the impurity region can be obtained from, for example, an SCM image.

The shape of the trench, the thickness of the insulating layer, and the like can be measured, for example, on an image of TEM (Transmission Electron Microscope).

(First Embodiment)
The semiconductor device of the first embodiment is provided in a silicon carbide layer having a first surface and a second surface facing the first surface, and extends in the first direction. In the first trench, the second trench provided in the silicon carbide layer and extending in the first direction, the first gate electrode provided in the first trench, and the second trench. A second gate electrode provided in the above, a first gate insulating layer provided between the first gate electrode and the silicon carbide layer, and a second gate electrode provided between the second gate electrode and the silicon carbide layer. A second gate insulating layer, a first conductive type first silicon carbide region provided in the silicon carbide layer, and a first silicon carbide region and a first silicon carbide region provided in the silicon carbide layer. A plurality of second conductive type second silicon carbide regions located between the surfaces, between the first trench and the second trench, and spaced apart from each other in the first direction. Two first conductive type silicon carbide regions provided in the silicon carbide layer and located between the second silicon carbide region and the first surface, and two silicon carbide layers. A second conductive type fourth silicon carbide region located between the second silicon carbide regions, between the first trench and the first silicon carbide region, and in contact with the second silicon carbide region. , Located in the silicon carbide layer, located between the two second silicon carbide regions, between the second trench and the first silicon carbide region, and in contact with the second silicon carbide region. A first silicon carbide region of the second conductive type, provided on the side of the first surface of the silicon carbide layer, in contact with the third silicon carbide region, and between the two second silicon carbide regions. It includes a first electrode in contact with the silicon carbide region and a second electrode provided on the side of the second surface of the silicon carbide layer.

Hereinafter, the case where the first conductive type is n type and the second conductive type is p type will be described as an example.

FIG. 1 is a schematic cross-sectional view of the semiconductor device of the first embodiment. FIG. 1 is a cross section of AA'in FIG. FIG. 1 is a cross-sectional view of a transistor region described later.

FIG. 2 is a schematic plan view of the semiconductor device of the first embodiment. FIG. 2 is a plan view of the first surface of FIG. 1 (P1 in FIG. 1).

FIG. 3 is a schematic cross-sectional view of the semiconductor device of the first embodiment. FIG. 3 is a BB'cross section of FIG. FIG. 3 is a cross-sectional view of a diode region described later.

FIG. 4 is a schematic cross-sectional view of the semiconductor device of the first embodiment. FIG. 4 is a CC'cross section of FIG.

FIG. 5 is a schematic cross-sectional view of the semiconductor device of the first embodiment. FIG. 5 is a DD'cross section of FIG.

FIG. 6 is a schematic cross-sectional view of the semiconductor device of the first embodiment. FIG. 6 is a cross section of EE'in FIG. FIG. 6 is a cross-sectional view taken along the first trench 22a described later.

The semiconductor device of the first embodiment is a trench gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 is an n-channel MOSFET having electrons as carriers. The MOSFET 100 of the semiconductor device of the first embodiment includes an SBD (Schottky Barrier Diode) as a built-in diode.

As shown in FIG. 2, in the MOSFET 100, the transistor region and the diode region are alternately arranged in the first direction. A MOSFET structure is formed in the transistor region. An SBD structure is arranged in the diode region.

The MOSFET 100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a first gate electrode 16a, a second gate electrode 16b, and a first gate insulating layer 18a. A second gate insulating layer 18b, an interlayer insulating layer 20, a first trench 22a, and a second trench 22b are provided.

In the silicon carbide layer 10, n ⁺ type drain region 24, n type drift region 26 (first silicon carbide region), p-type body region 28 (second silicon carbide region), n ⁺ type Source region 30 (third silicon carbide region), p-type first connection region 32a (fourth silicon carbide region), p-type second connection region 32b (fifth silicon carbide region), p. The first electric field relaxation region 34a (sixth silicon carbide region) of the mold, the second electric power relaxation region 34b (seventh silicon carbide region) of the p type, and the contact region 38 (tenth silicon carbide) of the p ⁺ type. Area) is provided.

The silicon carbide layer 10 is a single crystal SiC. The silicon carbide layer 10 is, for example, 4H-SiC.

The silicon carbide layer 10 includes a first surface (“P1” in FIG. 1) and a second surface (“P2” in FIG. 1) facing the first surface. Hereinafter, the first surface P1 is also referred to as a front surface, and the second surface P2 is also referred to as a back surface. Hereinafter, the “depth” means a depth with respect to the first surface P1.

In FIGS. 1, 2, 3, 4, 5, and 6, the first direction and the second direction are parallel to the first surface P1 and the second surface P2. The third direction is perpendicular to the first surface P1 and the second surface P2. The second direction is perpendicular to the first direction.

The first surface P1 is, for example, a surface inclined at 0 degrees or more and 8 degrees or less with respect to the (0001) surface. That is, it is a surface whose normal is inclined by 0 degrees or more and 8 degrees or less with respect to the c-axis in the [0001] direction. In other words, the off angle with respect to the (0001) plane is 0 degrees or more and 8 degrees or less. Further, the second surface P2 is, for example, a surface inclined by 0 degrees or more and 8 degrees or less with respect to the (000-1) surface.

The (0001) plane is called a silicon plane. The (000-1) surface is called a carbon surface. The inclination direction of the first surface P1 and the second surface P2 is, for example, the [11-20] direction. The [11-20] direction is the a-axis direction. In FIG. 1, for example, the second direction shown in the figure is the a-axis direction.

The first trench 22a and the second trench 22b are provided in the silicon carbide layer 10. The first trench 22a and the second trench 22b extend in the first direction as shown in FIG. A plurality of trenches including the first trench 22a and the second trench 22b are repeatedly arranged in the second direction. The repeat pitch in the second direction of the trench is, for example, 2 μm or more and 6 μm or less. The depth of the first trench 22a and the second trench 22b is, for example, 1 μm or more and 2 μm or less.

The first gate electrode 16a is located in the first trench 22a. The first gate electrode 16a is provided between the source electrode 12 and the drain electrode 14. The first gate electrode 16a extends in the first direction.

The second gate electrode 16b is located in the second trench 22b. The second gate electrode 16b is provided between the source electrode 12 and the drain electrode 14. The second gate electrode 16b extends in the first direction.

The first gate electrode 16a and the second gate electrode 16b are conductive layers. The first gate electrode 16a and the second gate electrode 16b are, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

The first gate insulating layer 18a is provided between the first gate electrode 16a and the silicon carbide layer 10. The first gate insulating layer 18a is provided between at least each region of the source region 30, the body region 28, and the drift region 26, and the first gate electrode 16a.

The second gate insulating layer 18b is provided between the second gate electrode 16b and the silicon carbide layer 10. The second gate insulating layer 18b is provided at least between each region of the source region 30, the body region 28, and the drift region 26, and the second gate electrode 16b.

The first gate insulating layer 18a and the second gate insulating layer 18b include, for example, silicon oxide, silicon nitride, or aluminum oxide. The first gate insulating layer 18a and the second gate insulating layer 18b are, for example, a laminated film of a film containing any of the above materials. The first gate insulating layer 18a and the second gate insulating layer 18b preferably contain silicon oxide containing nitrogen.

The interlayer insulating layer 20 is provided on the first gate electrode 16a and the second gate electrode 16b. The interlayer insulating layer 20 contains, for example, silicon oxide.

The n ⁺ type drain region 24 is provided on the back surface side of the silicon carbide layer 10. The drain region 24 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 24 is, for example, 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less.

The n-type drift region 26 is provided on the drain region 24. The drift region 26 is provided between the drain region 24 and the surface of the silicon carbide layer 10.

The drift region 26 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drift region 26 is, for example, 4 × 10 ¹⁴ cm ^-3 or more and 1 × 10 ¹⁷ cm ^-3 or less.

The p-shaped body region 28 is provided between the drift region 26 and the surface of the silicon carbide layer 10. The body region 28 is provided between the first trench 22a and the second trench 22b. As shown in FIG. 2, a plurality of body regions 28 are arranged apart from each other in the first direction.

The body region 28 functions as a channel region of the MOSFET 100. For example, when the MOSFET 100 is turned on, a channel through which electrons flow is formed in a region of the body region 28 in contact with the first gate insulating layer 18a and a region of the body region 28 in contact with the second gate insulating layer 18b. The region of the body region 28 in contact with the first gate insulating layer 18a and the region of the body region 28 in contact with the second gate insulating layer 18b are channel forming regions.

The body region 28 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the body region 28 is, for example, 5 × 10 ¹⁶ cm ^-3 or more and 5 × 10 ¹⁸ cm ^-3 or less.

The depth of the body region 28 is, for example, 0.2 μm or more and 1.0 μm or less.

The n ⁺ type source region 30 is provided between the body region 28 and the surface of the silicon carbide layer 10. The source region 30 is in contact with the source electrode 12. The source region 30 is in contact with the first gate insulating layer 18a or the second gate insulating layer 18b.

A first trench 22a is sandwiched between the two source regions 30. A second trench 22b is sandwiched between the two source regions 30.

The source region 30 contains, for example, phosphorus (P) as an n-type impurity. The concentration of n-type impurities in the source region 30 is higher than the concentration of n-type impurities in the drift region 26. The concentration of n-type impurities in the source region 30 is, for example, 5 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less.

The depth of the source region 30 is shallower than the depth of the body region 28, for example, 0.1 μm or more and 0.3 μm or less. The distance in the depth direction (third direction) between the drift region 26 and the source region 30 is, for example, 0.1 μm or more and 0.9 μm or less.

The p ⁺ type contact region 38 is provided between the body region 28 and the surface of the silicon carbide layer 10. The contact region 38 is in contact with the source electrode 12. The contact region 38 is sandwiched between, for example, two source regions 30.

The contact region 38 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the contact region 38 is higher than the p-type impurity concentration in the body region 28.

The concentration of p-type impurities in the contact region 38 is, for example, 5 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less.

The p-type first electric field relaxation region 34a is provided between the first trench 22a and the back surface of the silicon carbide layer 10. The first electric field relaxation region 34a is located between the first trench 22a and the drift region 26. The first electric field relaxation region 34a is in contact with the bottom of the first trench 22a.

As shown in FIG. 6, the first electric field relaxation region 34a extends in the first direction along the bottom of the first trench 22a. The first electric field relaxation region 34a is in contact with the first connection region 32a.

The p-type second electric field relaxation region 34b is provided between the second trench 22b and the back surface of the silicon carbide layer 10. The second electric field relaxation region 34b is located between the second trench 22b and the drift region 26. The second electric field relaxation region 34b is in contact with the bottom of the second trench 22b.

As shown in FIG. 6, the second electric field relaxation region 34b extends in the first direction along the bottom of the second trench 22b. The second electric field relaxation region 34b is in contact with the second connection region 32b.

The first electric field relaxation region 34a and the second electric field relaxation region 34b contain, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the first electric field relaxation region 34a and the second electric field relaxation region 34b is higher than, for example, the p-type impurity concentration in the body region 28. The p-type impurity concentration in the first electric field relaxation region 34a and the second electric field relaxation region 34b is, for example, 5 × 10 ¹⁷ cm ^-3 or more and 1 × 10 ¹⁹ cm ^-3 or less.

The thickness of the first electric field relaxation region 34a and the second electric field relaxation region 34b in the direction from the front surface to the back surface (third direction) is, for example, 0.1 μm or more and 0.3 μm or less.

The first electric field relaxation region 34a and the second electric field relaxation region 34b have a function of relaxing the electric field applied to the first gate insulating layer 18a and the second gate insulating layer 18b. In particular, it has a function of relaxing the electric field applied to the first gate insulating layer 18a at the bottom of the first trench 22a and the second gate insulating layer 18b at the bottom of the second trench 22b. The first electric field relaxation region 34a and the second electric field relaxation region 34b are fixed to the source potential via the first connection region 32a and the second connection region 32b.

The p-shaped first connection region 32a is located between the two body regions 28. The first connection region 32a is located between the first trench 22a and the drift region 26. The first connection region 32a touches the side surface of the first trench 22a. The first connection region 32a is in contact with the first electric field relaxation region 34a.

The depth of the first connection region 32a is deeper than the depth of the body region 28. The distance between the first connection region 32a and the back surface of the silicon carbide layer 10 is smaller than the distance between the body region 28 and the back surface of the silicon carbide layer 10.

The p-shaped second connection region 32b is located between the two body regions 28. The second connection region 32b is located between the second trench 22b and the drift region 26. The second connection region 32b touches the side surface of the second trench 22b. The second connection region 32b is in contact with the second electric field relaxation region 34b.

The depth of the second connection region 32b is deeper than the depth of the body region 28. The distance between the second connection region 32b and the back surface of the silicon carbide layer 10 is smaller than the distance between the body region 28 and the back surface of the silicon carbide layer 10.

A drift region 26 is sandwiched between the first connection region 32a and the second connection region 32b.

The first connection region 32a and the second connection region 32b contain, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the first connection region 32a and the second connection region 32b is higher than, for example, the p-type impurity concentration in the body region 28. The p-type impurity concentration in the first connection region 32a and the second connection region 32b is, for example, 5 × 10 ¹⁷ cm ^-3 or more and 1 × 10 ¹⁹ cm ^-3 or less.

The first connection region 32a and the second connection region 32b have a function of electrically connecting the first electric field relaxation region 34a and the second electric field relaxation region 34b to the source electrode 12. The first connection region 32a and the second connection region 32b fix the first electric field relaxation region 34a and the second electric field relaxation region 34b to the source potential.

By fixing the first electric field relaxation region 34a and the second electric field relaxation region 34b to the source potential, the electric charges from the first electric field relaxation region 34a and the second electric field relaxation region 34b are drawn out to the source electrode 12. Is promoted, and dielectric breakdown of the first gate insulating layer 18a and the second gate insulating layer 18b is suppressed.

The source electrode 12 is provided on the surface side of the silicon carbide layer 10. The source electrode 12 is provided on the surface of the silicon carbide layer 10. The source electrode 12 is in contact with, for example, the source region 30, the drift region 26, and the contact region 38.

The source electrode 12 contains metal. The metal forming the source electrode 12 is, for example, a laminated structure of titanium (Ti) and aluminum (Al). The source electrode 12 may include, for example, a metal silicide for reducing the contact resistance in a portion in contact with the source region 30 or the contact region 38. The metal silicide is, for example, nickel silicide.

The connection between the source electrode 12 and the source region 30 and the contact region 38 is, for example, an ohmic connection. The connection between the source electrode 12 and the drift region 26 between the two body regions 28 is a Schottky connection.

The drain electrode 14 is provided on the back surface side of the silicon carbide layer 10. The drain electrode 14 is provided on the back surface of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 24.

The drain electrode 14 is, for example, a metal or a metal semiconductor compound. The drain electrode 14 contains, for example, a material selected from the group consisting of nickel silicide (NiSi), titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

The width of the transistor region in the first direction is, for example, 1 times or more and 3 times or less the width of the diode region in the first direction. The width of the transistor region in the first direction is, for example, 1.5 times or more and 2.5 times or less the width of the diode region in the first direction. The width of the transistor region in the first direction is the width of the body region 28 in the first direction (w1 in FIG. 4). The width of the diode region in the first direction is the distance between the two body regions 28, that is, the width of the drift region 26 sandwiched between the two body regions 28 in the first direction (w2 in FIG. 4). ..

Next, an example of the method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 1 to 6.

First, a silicon carbide layer 10 having an n ⁺ type drain region 24 and an n type drift region 26 is prepared. The drift region 26 is, for example, an epitaxial layer formed on the drain region 24.

Next, the p-type body region 28, the n ⁺ -type source region 30, and the p ⁺ -type contact region 38 are formed in the silicon carbide layer 10 by an ion implantation method.

Next, the first trench 22a and the second trench 22b are formed on the silicon carbide layer 10 by using a known process technique.

Next, by the ion implantation method, the p-type first electric field relaxation region 34a, the p-type second electric field relaxation region 34b, the p-type first connection region 32a, and the p-type second connection region are used. Form 32b. The p-type first connection region 32a and the p-type second connection region 32b are formed, for example, by using oblique ion implantation.

Then, the silicon carbide layer 10 is heat-treated to activate the impurities introduced by the ion implantation method.

Next, in the first trench 22a and the second trench 22b by a known method, the first gate insulating layer 18a, the second gate insulating layer 18b, the first gate electrode 16a, and the second gate electrode 16a, and the second gate insulating layer 18a. The gate electrode 16b is formed.

Next, the interlayer insulating layer 20 is formed on the first gate electrode 16a and the second gate electrode 16b by using a known process technique.

Next, the source electrode 12 is formed on the surface of the silicon carbide layer 10 by using a known process technique. When forming the source electrode 12, the metal silicide region may be selectively formed on the source region 30 and the contact region 38.

Next, the drain electrode 14 is formed on the back surface of the silicon carbide layer 10 by using a known process technique. The MOSFET 100 shown in FIGS. 1 to 6 is manufactured by the above manufacturing method.

Hereinafter, the operation and effect of the semiconductor device of the first embodiment will be described.

The vertical MOSFET using silicon carbide has a pn junction diode as a parasitic built-in diode. In the MOSFET 100, the pn junction between the body region 28 and the drift region 26 is a parasitic built-in diode.

For example, MOSFETs are used as switching elements connected to inductive loads. In this case, even when the MOSFET is off, it is possible to pass a reflux current by using a pn junction diode.

However, when a reflux current is passed using a pn junction diode, stacking defects may grow in the silicon carbide layer due to carrier recombination energy generated by bipolar operation, and the on-resistance of the MOSFET may increase. Increasing the on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET.

The MOSFET 100 of the first embodiment includes, in the diode region, an SBD in which the source electrode 12 is shotkey connected to the drift region 26 as a built-in diode. The source electrode 12 is the anode of the SBD, and the drift region 26 is the cathode of the SBD.

The SBD operates in a unipolar manner. Therefore, even if a reflux current flows, stacking defects do not grow in the silicon carbide layer 10 due to the recombination energy of the carriers. Therefore, the reliability of the MOSFET 100 is improved.

The SBD has a higher leakage current at the time of reverse bias and a lower withstand voltage than the pn junction diode. Therefore, in the MOSFET having a built-in SBD, the power consumption may increase and the surge current withstand may decrease.

In the MOSFET 100 of the first embodiment, the depletion layer extends from the first connection region 32a and the second connection region 32b to the drift region 26 when the SBD in the diode region is reverse biased. Then, the interface between the source electrode 12 and the drift region 26 is covered with a depletion layer. Therefore, the leakage current is suppressed and the withstand voltage is improved. Therefore, it is possible to suppress an increase in power consumption and a decrease in reliability due to a decrease in surge current withstand.

The MOSFET 100 of the first embodiment is provided with a first connection region 32a and a second connection region 32b to form a so-called JBS (Junction Barrier Schottky) structure in which an SBD and a pn junction are combined.

In the trench gate type MOSFET, the on-resistance is reduced by increasing the channel density per unit area. However, in the trench gate type MOSFET, a structurally high electric field is applied particularly to the gate insulating layer at the bottom of the trench. Therefore, the dielectric breakdown resistance of the gate insulating layer may decrease. A decrease in the dielectric breakdown resistance of the gate insulating layer leads to a decrease in the reliability of the MOSFET.

The MOSFET 100 of the first embodiment is provided with a first electric field relaxation region 34a and a second electric field relaxation region 34b at the bottom of the first trench 22a and the second trench 22b. By providing the first electric field relaxation region 34a and the second electric field relaxation region 34b, the electric field strength applied to the first gate insulating layer 18a and the second gate insulating layer 18b is relaxed, and the gate insulating layer is insulated. Destruction resistance is improved.

However, if the first electric field relaxation region 34a and the second electric field relaxation region 34b are in an electrically floating state, the frequency response during switching of the MOSFET 100 deteriorates, and holes are generated when the MOSFET is turned off. Dielectric breakdown of the gate insulating layer may occur due to the fact that the electric field relaxation region 34a of 1 and the second electric field relaxation region 34b cannot be removed.

The MOSFET 100 of the first embodiment is provided with a first connection region 32a and a second connection region 32b connected to the first electric field relaxation region 34a and the second electric field relaxation region 34b. Therefore, the first electric field relaxation region 34a and the second electric field relaxation region 34b are electrically connected to the source electrode 12 via the first connection region 32a and the second connection region 32b.

Therefore, during switching of the MOSFET 100, holes are drawn from the first electric field relaxation region 34a and the second electric field relaxation region 34b to the source electrode 12 through the first connection region 32a and the second connection region 32b. Is possible. Therefore, dielectric breakdown of the gate insulating layer is suppressed, and the reliability of the MOSFET 100 is improved.

FIG. 7 is a schematic plan view of the semiconductor device of the modified example of the first embodiment. FIG. 8 is a schematic cross-sectional view of the semiconductor device of the modified example of the first embodiment. FIG. 8 is a FF'cross section of FIG.

The MOSFET 101 of the modified example has a p-type first connection region 32a (fourth silicon carbide region) having a width in the first direction (FIG. 7, w3 in FIG. 8) and a p-type second connection. The width of the region 32b (fifth silicon carbide region) in the first direction (w3 in FIGS. 7 and 8) is n-type sandwiched between two p-type body regions 28 (second silicon carbide region). It differs from the MOSFET 100 of the first embodiment in that it is wider than the width of the drift region 26 (first silicon carbide region) in the first direction (w2 in FIG. 7).

According to the MOSFET 101 of the modified example, the width w3 in the first direction of the first connection region 32a and the width w3 in the first direction of the second connection region 32b are wide, so that the holes are first generated. The efficiency of drawing from the electric field relaxation region 34a and the second electric field relaxation region 34b to the source electrode 12 is improved. Therefore, as compared with the MOSFET 100 of the first embodiment, the decrease in gate dielectric breakdown withstand voltage is further suppressed.

The width of the transistor region in the first direction is preferably 1 time or more and 3 times or less, and preferably 1.5 times or more and 2.5 times or less the width of the diode region in the first direction. .. By satisfying the above range, the balance between the on-current and the reflux current can be more properly maintained.

As described above, according to the first embodiment and the modified example, an increase in on-resistance, a decrease in avalanche withstand voltage, and a decrease in gate dielectric breakdown withstand voltage are suppressed, and a MOSFET with improved reliability can be realized.

(Second embodiment)
The semiconductor device of the second embodiment is provided in the silicon carbide layer, is located between the fourth silicon carbide region and the first surface, and is a second conductive type impurity rather than the fourth silicon carbide region. The second conductive type having a high concentration of the eighth silicon carbide region, which is provided in the silicon carbide layer, is located between the fifth silicon carbide region and the first surface, and is located from the fifth silicon carbide region. Also differs from the first embodiment in that it further includes a second conductive type ninth silicon carbide region having a high concentration of second conductive type impurities. Hereinafter, the description of the contents overlapping with the first embodiment will be omitted.

FIG. 9 is a schematic cross-sectional view of the semiconductor device of the second embodiment. FIG. 10 is a schematic plan view of the semiconductor device of the second embodiment. FIG. 9 is a GG'cross section of FIG. FIG. 9 is a cross-sectional view of the diode region.

In the MOSFET 200 of the second embodiment, the p ⁺ type first high concentration region 36a (eighth silicon carbide region) and the p ⁺ type second high concentration region 36b (second high concentration region 36b) are contained in the silicon carbide layer 10. 9 silicon carbide regions).

The p ⁺ type first high concentration region 36a is located between the first connection region 32a and the surface of the silicon carbide layer 10. The first high concentration region 36a is in contact with the source electrode 12. The p-type impurity concentration in the first high concentration region 36a is higher than the p-type impurity concentration in the first connection region 32a.

The p ⁺ -shaped second high concentration region 36b is located between the second connection region 32b and the surface of the silicon carbide layer 10. The second high concentration region 36b is in contact with the source electrode 12. The p-type impurity concentration in the second high concentration region 36b is higher than the p-type impurity concentration in the second connection region 32b.

The first high-concentration region 36a and the second high-concentration region 36b contain, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the first high concentration region 36a and the second high concentration region 36b is, for example, 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less.

The first high concentration region 36a has a function of reducing the resistance between the source electrode 12 and the first connection region 32a. By reducing the resistance between the source electrode 12 and the first connection region 32a, the resistance between the source electrode 12 and the first electric field relaxation region 34a is also reduced.

Similarly, the second high concentration region 36b has the function of reducing the resistance between the source electrode 12 and the second connection region 32b. By reducing the resistance between the source electrode 12 and the second connection region 32b, the resistance between the source electrode 12 and the second electric field relaxation region 34b is also reduced.

By reducing the resistance between the source electrode 12 and the first high-concentration region 36a and the second high-concentration region 36b, holes are removed from the first electric field relaxation region 34a and the second electric field relaxation region 34b. , The efficiency of pulling out to the source electrode 12 is improved. Therefore, as compared with the MOSFET 100 of the first embodiment, the decrease in gate dielectric breakdown withstand voltage is further suppressed.

As described above, according to the second embodiment, as in the first embodiment, an increase in on-resistance and a decrease in the avalanche withstand are suppressed, and a MOSFET with improved reliability can be realized. Further, as compared with the first embodiment, it is possible to realize a MOSFET in which a decrease in gate dielectric breakdown withstand voltage is further suppressed and reliability is further improved.

(Third embodiment)
The semiconductor device of the third embodiment is different from the first embodiment in that the transistor region does not include the sixth silicon carbide region and the seventh silicon carbide region. Hereinafter, the description of the contents overlapping with the first embodiment will be omitted.

FIG. 11 is a schematic cross-sectional view of the semiconductor device of the third embodiment. FIG. 12 is a schematic cross-sectional view of the semiconductor device of the third embodiment. FIG. 13 is a schematic cross-sectional view of the semiconductor device of the third embodiment.

FIG. 11 is a diagram corresponding to FIG. 1 of the first embodiment. FIG. 11 is a cross-sectional view of the transistor region.

FIG. 12 is a diagram corresponding to FIG. 3 of the first embodiment. FIG. 12 is a cross-sectional view of the diode region.

FIG. 13 is a diagram corresponding to FIG. 6 of the first embodiment. FIG. 13 is a cross-sectional view taken along the first trench 22a.

As shown in FIGS. 11 and 13, the MOSFET 300 of the third embodiment has a p-type first electric field relaxation region 34a and a p-type second electric field in the silicon carbide layer 10 of the transistor region. It does not have a relaxation region 34b.

In the transistor region, the bottom of the first trench 22a touches the drift region 26. In the transistor region, the bottom of the second trench 22b is in contact with the drift region 26.

As shown in FIGS. 12 and 13, a first electric field relaxation region 34a is provided between the first trench 22a and the drift region 26 in the silicon carbide layer 10 in the diode region. Similarly, a second electric field relaxation region 34b is provided between the second trench 22b and the drift region 26 in the silicon carbide layer 10 in the diode region.

In the MOSFET 300 of the third embodiment, the depletion layer extends from the first electric field relaxation region 34a and the second electric field relaxation region 34b of the diode region to the drift region 26 when the MOSFET 300 is off. The depletion layer covers the interface between the first trench 22a and the drift region 26 and the interface between the second trench 22b and the drift region 26. Therefore, the electric field applied to the first gate insulating layer 18a and the second gate insulating layer 18b is relaxed. Therefore, dielectric breakdown of the gate insulating layer is suppressed, and the reliability of the MOSFET 100 is improved.

From the viewpoint of sufficiently covering the interface between the first trench 22a and the drift region 26 and the interface between the second trench 22b and the drift region 26 with a depletion layer, the first of the first electric field relaxation regions 34a. And the width of the second electric field relaxation region 34b in the first direction are wider than the width of the n-type drift region 26 sandwiched between the two p-type body regions 28 in the first direction. Is preferable.

As described above, according to the third embodiment, as in the first embodiment, an increase in on-resistance, a decrease in avalanche withstand voltage, and a decrease in gate dielectric breakdown withstand voltage are suppressed, and a MOSFET with improved reliability can be realized.

(Fourth Embodiment)
The semiconductor device of the fourth embodiment is different from the third embodiment in that the diode region also does not include the sixth silicon carbide region and the seventh silicon carbide region. Hereinafter, the description of the contents overlapping with the third embodiment will be omitted.

FIG. 14 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment. FIG. 15 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment.

FIG. 14 is a diagram corresponding to FIG. 1 of the first embodiment. FIG. 14 is a cross-sectional view of the transistor region.

FIG. 15 is a diagram corresponding to FIG. 3 of the first embodiment. FIG. 15 is a cross-sectional view of the diode region.

As shown in FIG. 14, the MOSFET 400 of the fourth embodiment has a p-type first electric field relaxation region 34a and a p-type second electric field relaxation region 34b in the silicon carbide layer 10 of the transistor region. Not equipped. Further, as shown in FIG. 15, the silicon carbide layer 10 in the diode region does not include the p-type first electric field relaxation region 34a and the p-type second electric field relaxation region 34b.

The MOSFET 400 of the fourth embodiment includes the bottom of the first trench 22a and the bottom of the first trench 22a by providing the first connection region 32a and the second connection region 32b during the switching operation from the off operation to the on operation of the MOSFET 400. The efficiency of pulling out the carrier from the bottom of the second trench 22b is improved. Therefore, the resistance of the drift region 26 when shifting from the off operation to the on operation is quickly reduced, and the MOSFET 400 with the reduced on resistance can be realized.

As described above, according to the fourth embodiment, as in the first embodiment, an increase in on-resistance and a decrease in the avalanche withstand are suppressed, and a MOSFET with improved reliability can be realized. In addition, a MOSFET with reduced on-resistance can be realized.

As described above, in the first to fourth embodiments, the case of 4H-SiC as the crystal structure of silicon carbide has been described as an example, but the present invention can be applied to silicon carbide having other crystal structures such as 6H-SiC and 3C-SiC. It is also possible to apply. It is also possible to apply a surface other than the (0001) surface to the surface of the silicon carbide layer 10.

In the first to fourth embodiments, the case where the first conductive type is n type and the second conductive type is p type has been described as an example, but the first conductive type is p type and the second conductive type is n type. It is also possible to do.

In the first to fourth embodiments, aluminum (Al) is exemplified as the p-type impurity, but boron (B) can also be used. Further, although nitrogen (N) and phosphorus (P) are exemplified as n-type impurities, arsenic (As), antimony (Sb) and the like can also be applied.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. For example, the components of one embodiment may be replaced or modified with the components of another embodiment. These embodiments and variations thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

10 Silicon carbide layer 12 Source electrode (first electrode)
14 Drain electrode (second electrode)
16a First gate electrode 16b Second gate electrode 18a First gate insulating layer 18b Second gate insulating layer 22a First trench 22b Second trench 26 Drift region (first silicon carbide region)
28 Body region (second silicon carbide region)
30 Source region (third silicon carbide region)
32a 1st connection region (4th silicon carbide region)
32b Second connection region (fifth silicon carbide region)
34a 1st electric field relaxation region (6th silicon carbide region)
34b 2nd electric field relaxation region (7th silicon carbide region)
36a 1st high concentration region (8th silicon carbide region)
36b 2nd high concentration region (9th silicon carbide region)
38 Contact region (10th silicon carbide region)
100 MOSFET (semiconductor device)
101 MOSFET (semiconductor device)
200 MOSFET (semiconductor device)
300 MOSFET (semiconductor device)
400 MOSFET (semiconductor device)
P1 first surface P2 second surface

Claims (9)

A silicon carbide layer having a first surface and a second surface facing the first surface,
A first trench provided in the silicon carbide layer and extending in the first direction,
A second trench provided in the silicon carbide layer and extending in the first direction,
The first gate electrode provided in the first trench and
The second gate electrode provided in the second trench and
A first gate insulating layer provided between the first gate electrode and the silicon carbide layer,
A second gate insulating layer provided between the second gate electrode and the silicon carbide layer,
The first conductive type first silicon carbide region provided in the silicon carbide layer and
It is provided in the silicon carbide layer, is located between the first silicon carbide region and the first surface, is located between the first trench and the second trench, and is the first. A plurality of second conductive type second silicon carbide regions arranged apart from each other in the direction of 1.
A first conductive type third silicon carbide region provided in the silicon carbide layer and located between the second silicon carbide region and the first surface.
Provided in the silicon carbide layer, located between two said second silicon carbide regions, located between the first trench and the first silicon carbide region, said second carbonized. A second conductive type fourth silicon carbide region in contact with the silicon region,
It is provided in the silicon carbide layer, is located between the two second silicon carbide regions, is located between the second trench and the first silicon carbide region, and is the second carbide. A second conductive type fifth silicon carbide region in contact with the silicon region,
A first silicon carbide layer provided on the side of the first surface and in contact with the third silicon carbide region and in contact with the first silicon carbide region between the two second silicon carbide regions. With electrodes
A second electrode provided on the side of the second surface of the silicon carbide layer, and
A semiconductor device including a MOSFET. A silicon carbide layer having a first surface and a second surface facing the first surface,
A first trench provided in the silicon carbide layer and extending in the first direction,
A second trench provided in the silicon carbide layer and extending in the first direction,
The first gate electrode provided in the first trench and
The second gate electrode provided in the second trench and
A first gate insulating layer provided between the first gate electrode and the silicon carbide layer,
A second gate insulating layer provided between the second gate electrode and the silicon carbide layer,
The first conductive type first silicon carbide region provided in the silicon carbide layer and
It is provided in the silicon carbide layer, is located between the first silicon carbide region and the first surface, is located between the first trench and the second trench, and is the first. A plurality of second conductive type second silicon carbide regions arranged apart from each other in the direction of 1.
A first conductive type third silicon carbide region provided in the silicon carbide layer and located between the second silicon carbide region and the first surface.
Provided in the silicon carbide layer, located between two said second silicon carbide regions, located between the first trench and the first silicon carbide region, said second carbonized. A second conductive type fourth silicon carbide region in contact with the silicon region,
It is provided in the silicon carbide layer, is located between the two second silicon carbide regions, is located between the second trench and the first silicon carbide region, and is the second carbide. A second conductive type fifth silicon carbide region in contact with the silicon region,
A first silicon carbide layer provided on the side of the first surface and in contact with the third silicon carbide region and in contact with the first silicon carbide region between the two second silicon carbide regions. With electrodes
A second electrode provided on the side of the second surface of the silicon carbide layer, and
Equipped with
The distance between the fourth silicon carbide region and the second surface and the distance between the fifth silicon carbide region and the second surface are the second silicon carbide region and the above. A semiconductor device that is smaller than the distance to the second surface. A silicon carbide layer having a first surface and a second surface facing the first surface,
A first trench provided in the silicon carbide layer and extending in the first direction,
A second trench provided in the silicon carbide layer and extending in the first direction,
The first gate electrode provided in the first trench and
The second gate electrode provided in the second trench and
A first gate insulating layer provided between the first gate electrode and the silicon carbide layer,
A second gate insulating layer provided between the second gate electrode and the silicon carbide layer,
The first conductive type first silicon carbide region provided in the silicon carbide layer and
It is provided in the silicon carbide layer, is located between the first silicon carbide region and the first surface, is located between the first trench and the second trench, and is the first. A plurality of second conductive type second silicon carbide regions arranged apart from each other in the direction of 1.
A first conductive type third silicon carbide region provided in the silicon carbide layer and located between the second silicon carbide region and the first surface.
Provided in the silicon carbide layer, located between two said second silicon carbide regions, located between the first trench and the first silicon carbide region, said second carbonized. A second conductive type fourth silicon carbide region in contact with the silicon region,
It is provided in the silicon carbide layer, is located between the two second silicon carbide regions, is located between the second trench and the first silicon carbide region, and is the second carbide. A second conductive type fifth silicon carbide region in contact with the silicon region,
A first silicon carbide layer provided on the side of the first surface and in contact with the third silicon carbide region and in contact with the first silicon carbide region between the two second silicon carbide regions. With electrodes
A second electrode provided on the side of the second surface of the silicon carbide layer, and
Equipped with
It is provided in the silicon carbide layer, is located between the first trench and the second surface, is located between the first trench and the first silicon carbide region, and is the first. A second conductive type sixth silicon carbide region that is in contact with the silicon carbide region of 4 and extends in the first direction.
Provided in the silicon carbide layer, located between the second trench and the second surface, located between the second trench and the first silicon carbide region, said first. A second conductive type seventh silicon carbide region that is in contact with the silicon carbide region of 5 and extends in the first direction.
A semiconductor device further equipped with. A silicon carbide layer having a first surface and a second surface facing the first surface,
A first trench provided in the silicon carbide layer and extending in the first direction,
A second trench provided in the silicon carbide layer and extending in the first direction,
The first gate electrode provided in the first trench and
The second gate electrode provided in the second trench and
A first gate insulating layer provided between the first gate electrode and the silicon carbide layer,
A second gate insulating layer provided between the second gate electrode and the silicon carbide layer,
The first conductive type first silicon carbide region provided in the silicon carbide layer and
It is provided in the silicon carbide layer, is located between the first silicon carbide region and the first surface, is located between the first trench and the second trench, and is the first. A plurality of second conductive type second silicon carbide regions arranged apart from each other in the direction of 1.
A first conductive type third silicon carbide region provided in the silicon carbide layer and located between the second silicon carbide region and the first surface.
Provided in the silicon carbide layer, located between two said second silicon carbide regions, located between the first trench and the first silicon carbide region, said second carbonized. A second conductive type fourth silicon carbide region in contact with the silicon region,
It is provided in the silicon carbide layer, is located between the two second silicon carbide regions, is located between the second trench and the first silicon carbide region, and is the second carbide. A second conductive type fifth silicon carbide region in contact with the silicon region,
A first silicon carbide layer provided on the side of the first surface and in contact with the third silicon carbide region and in contact with the first silicon carbide region between the two second silicon carbide regions. With electrodes
A second electrode provided on the side of the second surface of the silicon carbide layer, and
Equipped with
Second conductivity provided in the silicon carbide layer, located between the fourth silicon carbide region and the first surface, and has a higher concentration of second conductive type impurities than the fourth silicon carbide region. The eighth silicon carbide region of the mold and
Second conductivity provided in the silicon carbide layer, located between the fifth silicon carbide region and the first surface, and has a higher concentration of second conductive type impurities than the fifth silicon carbide region. The ninth silicon carbide region of the mold and
A semiconductor device further equipped with. Second conductivity provided in the silicon carbide layer, located between the second silicon carbide region and the first surface, and has a higher concentration of second conductive type impurities than the second silicon carbide region. The semiconductor device according to any one of claims 1 to 4, further comprising a tenth silicon carbide region of the mold. A silicon carbide layer having a first surface and a second surface facing the first surface,
A first trench provided in the silicon carbide layer and extending in the first direction,
A second trench provided in the silicon carbide layer and extending in the first direction,
The first gate electrode provided in the first trench and
The second gate electrode provided in the second trench and
A first gate insulating layer provided between the first gate electrode and the silicon carbide layer,
A second gate insulating layer provided between the second gate electrode and the silicon carbide layer,
The first conductive type first silicon carbide region provided in the silicon carbide layer and
It is provided in the silicon carbide layer, is located between the first silicon carbide region and the first surface, is located between the first trench and the second trench, and is the first. A plurality of second conductive type second silicon carbide regions arranged apart from each other in the direction of 1.
A first conductive type third silicon carbide region provided in the silicon carbide layer and located between the second silicon carbide region and the first surface.
Provided in the silicon carbide layer, located between two said second silicon carbide regions, located between the first trench and the first silicon carbide region, said second carbonized. A second conductive type fourth silicon carbide region in contact with the silicon region,
It is provided in the silicon carbide layer, is located between the two second silicon carbide regions, is located between the second trench and the first silicon carbide region, and is the second carbide. A second conductive type fifth silicon carbide region in contact with the silicon region,
A first silicon carbide layer provided on the side of the first surface and in contact with the third silicon carbide region and in contact with the first silicon carbide region between the two second silicon carbide regions. With electrodes
A second electrode provided on the side of the second surface of the silicon carbide layer, and
Equipped with
The second conductive impurity concentration in the fourth silicon carbide region and the second conductive impurity concentration in the fifth silicon carbide region are higher than the second conductive impurity concentration in the second silicon carbide region. , Semiconductor equipment. A silicon carbide layer having a first surface and a second surface facing the first surface,
A first trench provided in the silicon carbide layer and extending in the first direction,
A second trench provided in the silicon carbide layer and extending in the first direction,
The first gate electrode provided in the first trench and
The second gate electrode provided in the second trench and
A first gate insulating layer provided between the first gate electrode and the silicon carbide layer,
A second gate insulating layer provided between the second gate electrode and the silicon carbide layer,
The first conductive type first silicon carbide region provided in the silicon carbide layer and
It is provided in the silicon carbide layer, is located between the first silicon carbide region and the first surface, is located between the first trench and the second trench, and is the first. A plurality of second conductive type second silicon carbide regions arranged apart from each other in the direction of 1.
A first conductive type third silicon carbide region provided in the silicon carbide layer and located between the second silicon carbide region and the first surface.
Provided in the silicon carbide layer, located between two said second silicon carbide regions, located between the first trench and the first silicon carbide region, said second carbonized. A second conductive type fourth silicon carbide region in contact with the silicon region,
It is provided in the silicon carbide layer, is located between the two second silicon carbide regions, is located between the second trench and the first silicon carbide region, and is the second carbide. A second conductive type fifth silicon carbide region in contact with the silicon region,
A first silicon carbide layer provided on the side of the first surface and in contact with the third silicon carbide region and in contact with the first silicon carbide region between the two second silicon carbide regions. With electrodes
A second electrode provided on the side of the second surface of the silicon carbide layer, and
Equipped with
The first width of the fourth silicon carbide region in the first direction and the width of the fifth silicon carbide region in the first direction are sandwiched between two second silicon carbide regions. A semiconductor device that is wider than the width of the silicon carbide region in the first direction. The semiconductor device according to any one of claims 1 to 7, wherein the connection between the first electrode and the first silicon carbide region is a Schottky connection. The semiconductor device according to any one of claims 1 to 8, wherein the first gate insulating layer and the second gate insulating layer contain silicon oxide containing nitrogen.

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