JP4101229B2 - Semiconductor integrated circuit and control method - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit and a control method, and more particularly, to a power supply control technique for a semiconductor integrated circuit in which power supply is separated.

  In recent years, semiconductor integrated circuits have been required to have low power consumption, and the operation area of the semiconductor integrated circuit is constantly supplied with a power supply voltage (a circuit in which the power supply is always on) and the supply of power supply voltage is cut off. In other words, there are increasing opportunities for development by separating the power supply into separate circuits (circuits where the power supply may be turned off, that is, circuits where the power supply is turned on / off). As a method of performing such power source separation, a method of providing a power source separation circuit and a guard ring block for preventing a current between power source separated circuits (see, for example, Patent Document 1), or between power source separated circuits. There is a method of providing a conversion circuit capable of fixing the potential (for example, see Patent Document 2).

JP 2001-308187 A JP 2003-218682 A

  However, when the power supply is separated inside the semiconductor integrated circuit, when the power supply is turned off in the circuit where the power supply is turned on / off, the output from this circuit becomes high impedance (Hi-Z). Therefore, when the connection destination circuit (the circuit that receives the output from the circuit in which the power is turned off) is a circuit in which the power is on, a through current flows in the connection destination circuit. Also, in the reverse connection relationship, a through current is generated when the connection destination (input source) of a circuit whose power is turned off uses a transfer gate.

  The present invention has been made in view of such circumstances, and prevents a through current from flowing when a power source is turned off in a part of the circuit in a semiconductor integrated circuit that performs power source separation. With the goal.

A semiconductor integrated circuit according to the present invention includes a first circuit to which power supply voltage is constantly supplied, a second circuit in which supply of power supply voltage may be interrupted, and a logic circuit having at least two input terminals. . The output terminal of the second circuit is connected to the first input terminal of the logic circuit, and the output control signal is supplied to the second input terminal. When controlling the supply of the power supply voltage to the second circuit , the output of the logic circuit is fixed to a predetermined potential based on the output control signal, and output after the supply of the power supply voltage to the second circuit is started. The logic circuit outputs the output of the second circuit based on the control signal, and after the output of the logic circuit is fixed to a predetermined potential based on the output control signal, the supply of the power supply voltage to the second circuit is cut off. .

  According to the above configuration, the output of the circuit receiving the output from the second circuit is supplied via the logic circuit only during a predetermined period during which the power supply voltage is supplied to the second circuit. In addition, the predetermined potential is supplied by the logic circuit except for the predetermined period including the period in which the supply of the power supply voltage to the second circuit is interrupted. Therefore, it is possible to prevent the input from being in a floating state in the circuit that receives the output from the second circuit.

According to the present invention, a power-separated semiconductor integrated circuit having a first circuit to which power supply voltage is constantly supplied and a second circuit in which supply of power supply voltage may be interrupted is based on an output control signal. The output of the logic circuit is fixed at a predetermined potential, and after the supply of the power supply voltage to the second circuit is started, the output of the second circuit is output as the output of the logic circuit, and based on the output control signal Then, after the output of the logic circuit is fixed to a predetermined potential, the supply of the power supply voltage to the second circuit is cut off. Thereby, the supply of the power supply voltage to the second circuit is cut off, and even if the output becomes high impedance, the predetermined potential is supplied by the logic circuit to the circuit on the side receiving the output from the second circuit, The input can be prevented from being in a floating state. Therefore, it is possible to prevent a through current from flowing when the supply of the power supply voltage to the second circuit is interrupted, and to reduce wasteful power consumption.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram showing a configuration example of a semiconductor integrated circuit LSI1 according to the first embodiment of the present invention. The semiconductor integrated circuit LSI1 has circuit modules CMA, CMB, CMC, and CMD. The semiconductor integrated circuit LSI1 is connected to first to fourth power supply circuits (power supply devices) PSL, PSA, PSB, and PSC.

  The circuit module (A Module) CMA has an internal circuit module (A1 Module) ICA constituting a processing circuit and the like. The circuit module CMA is connected to the second power supply circuit PSA, and the power supply voltage SA2 is supplied from the second power supply circuit PSA.

  Similarly, the circuit module (B Module) CMB has an internal circuit module (B1 Module) ICB constituting a processing circuit and the like. The circuit module CMB is connected to the third power supply circuit PSB, and the power supply voltage SB2 is supplied from the third power supply circuit PSB.

Similarly, the circuit module (C Module) CMC has an internal circuit module (C1 Module) ICC constituting a processing circuit and the like. The circuit module CMC is connected to the fourth power supply circuit PSC, and the power supply voltage SC2 is supplied from the fourth power supply circuit PSC.
Note that so-called IP macros can be used for the internal circuit modules ICA, ICB, and ICC in the circuit modules CMA, CMB, and CMC by defining their input / output.

  The circuit module (D Module) CMD is a control circuit that comprehensively controls the second to fourth power supply circuits PSA, PSB, and PSC and a logic circuit (AND gate in the first embodiment) to be described later. The circuit module CMD receives the control signal SD from the outside, the control signals SA1, SB1, and SC1 for controlling the second to fourth power supply circuits PSA, PSB, and PSC, and the output control signal for controlling the logic circuit. SA3, SB3, and SC3 are output. The control signal SD is a signal for enabling control from the outside of the semiconductor integrated circuit LSI1, and based on the control signal SD, the circuit module CMD generates or generates the control signals SA1, SB1, SC1, and the like. Control.

  Other circuits (including the circuit module CMD) in the semiconductor integrated circuit LSI excluding the circuit modules CMA, CMB, and CMC are connected to the first power supply circuit PSL, and the power supply voltage S0 is supplied from the first power supply circuit PSL. Is done.

  The first power supply circuit PSL always supplies the power supply voltage S0 once the power is turned on until the entire semiconductor integrated circuit LSI1 is turned off. On the other hand, the second to fourth power supply circuits PSA, PSB, and PSC are independently controlled by the control signals SA1, SB1, and SC1 supplied from the circuit module CMD, and the power is turned on / off as necessary. The power supply voltages SA2, SB2, and SC2 are supplied and cut off.

  That is, in the semiconductor integrated circuit LSI1, the circuit modules CMA, CMB, and CMC are circuits (circuits in which the power is turned on / off) that may be cut off from the supply of the power supply voltage. Other circuits (including the circuit module CMD) are circuits to which a power supply voltage is constantly supplied (a circuit in which the power supply is always on).

  Here, in the semiconductor integrated circuit LSI1 according to the first embodiment, each signal output from the circuit modules CMA, CMB, and CMC whose power is turned on / off is provided with an AND gate as a receiving destination (output destination). Provide. Signals output from the circuit modules CMA, CMB, CMC are input to one input of the AND gate, output control signals SA3, SB3, SC3 are input to the other input, and outputs are output from the circuit modules CMA, CMB, CMC. Supply to the receiver of the output signal.

  In other words, an AND gate is provided between the output ends of the circuit modules CMA, CMB, and CMC whose power is turned on / off and the input ends of the circuits that receive signals output from the output ends. The output terminals of the circuit modules CMA, CMB, and CMC are connected to one input terminal of the AND gate, and the signal lines related to the output control signals SA3, SB3, and SC3 are connected to the other input terminal. Further, an input terminal of a circuit that receives output signals from the circuit modules CMA, CMB, and CMC is connected to an output terminal of the AND gate.

  For example, as shown in FIG. 1, for the output signals SA4 and SA5 from the internal circuit module ICA in the circuit module CMA whose power is turned on / off, the output signal SA4 and the output control signal are received at the destination of the output signal SA4. An AND gate D11 is provided that receives SA3 and supplies the output to the receiver of the output signal SA4. Further, an output signal SA5 and an output control signal SA3 are input to the receiver of the output signal SA5, and an AND gate B11 is provided for supplying the output to the internal circuit module ICB in the circuit module CMB that is the receiver of the output signal SA5. It is done.

  Similarly, for the output signals SB4, SB5, and SB6 from the internal circuit module ICB in the circuit module CMB, the output signal SB4 and the output control signal SB3 are input to the destination of the output signal SB4, and the output is output from the output signal SB4. An AND gate D12 is provided to supply to the receiver. Further, an output gate SB5 and an output control signal SB3 are input to the receiver of the output signal SB5, and an AND gate C11 is provided to supply the output to the internal circuit module ICC in the circuit module CMC that is the receiver of the output signal SB5. The output signal SB6 and the output control signal SB3 are input to the receiver of the output signal SB6, and the AND gate A11 is provided to supply the output to the internal circuit module ICA in the circuit module CMA that is the receiver of the output signal SB6. It is done.

  Similarly, for the output signals SC4 and SC5 from the internal circuit module ICC in the circuit module CMC, the output signal SC4 and the output control signal SC3 are input to the destination of the output signal SC4, and the output is received by the output signal SC4. An AND gate D13 to be supplied first is provided. Further, an output gate SC12 and an output control signal SC3 are input to the receiver of the output signal SC5, and an AND gate B12 is provided to supply the output to the internal circuit module ICB in the circuit module CMB that is the receiver of the output signal SC5. It is done.

  In the semiconductor integrated circuit LSI1 according to the first embodiment, each signal (however, input from the circuit module CMD) is input to the circuit modules CMA, CMB, and CMC that are turned on / off from a circuit that is always turned on. With respect to the output control signal, the buffer circuit is provided and connected to the input terminals of the internal circuit modules ICA, ICB, and ICC to which each signal is input. That is, each signal input to the circuit modules CMA, CMB, and CMC is supplied to the input terminals of the internal circuit modules ICA, ICB, and ICC via the buffer circuit.

  In the buffer circuit, when a transfer gate is used as a connection destination (input source) of each signal input to the circuit modules CMA, CMB, and CMC, power to the circuit modules CMA, CMB, and CMC is turned off. This is to prevent a through current from flowing. Therefore, when the transfer gate is not used as the connection destination (input source), the buffer circuit may not be provided.

  For example, as shown in FIG. 1, the input signal SA6 is supplied to the internal circuit module ICA in the circuit module CMA whose power is turned on / off via the buffer circuit A12. The input signal SB7 is supplied to the internal circuit module ICB in the circuit module CMB whose power is turned on / off via the buffer circuit B13. Similarly, the input signal SC6 is supplied to the internal circuit module ICC in the circuit module CMC whose power is turned on / off via the buffer circuit C12.

Next, the operation will be described.
FIG. 2A is a timing chart showing an example of a power supply control sequence of the semiconductor integrated circuit LSI1 according to the first embodiment. In FIG. 2A, power is turned on in the order of first power circuit PSL → second power circuit PSA → third power circuit PSB → fourth power circuit PSC, and fourth power circuit PSC → second power circuit. 3 shows a case where the power supply circuit PSB 3 is disconnected (power supply is cut off) in the order of the second power supply circuit PSA → the first power supply circuit PSL.

  First, when the first power supply circuit PSL is in an off state, that is, when the power supply voltage S0 is not supplied to the semiconductor integrated circuit LSI1, the control signals SA1, SB1, SC1 output from the circuit module CMD, and output control Signals SA3, SB3, and SC3 are undefined.

  When the first power supply circuit PSL is turned on, the power supply voltage S0 is supplied to other circuits (including the circuit module CMD) of the semiconductor integrated circuit LSI1 excluding the circuit modules CMA, CMB, and CMC. As a result, low level (“L”) control signals SA1, SB1, and SC1 and output control signals SA3, SB3, and SC3 are output from the circuit module CMD. Therefore, the power supply voltages SA2, SB2, and SC2 from the second to fourth power supply circuits PSA, PSB, and PSC are not supplied.

  At this time, the potentials of the signals SA4, SA5, SB5, SB6, SC4, and SC5 output from the circuit modules CMA, CMB, and CMC correspond to a high impedance state. Among these output signals, the output signals that are received by the circuit whose power is on are SA4, SB4, and SC4, but the AND gates D11, D12, and D13 to which the output signals SA4, SB4, and SC4 are input. The output control signals SA3, SB3, and SC3 are input at “L”. Therefore, the AND gates D11, D12, and D13 supply an “L” signal to the circuit that receives the output signals SA4, SB4, and SC4, preventing the input from being in a floating state and allowing a through current to flow. Can be prevented.

  Thereafter, when the second power supply circuit PSA is turned on, the circuit module CMD sets the control signal SA1 corresponding to the second power supply circuit PSA to a high level (“H”). When the control signal SA1 becomes “H”, the second power supply circuit PSA is turned on, and the power supply voltage SA2 is supplied from the second power supply circuit PSA to the circuit module CMA. As a result, the potentials of the output signals SA4 and SA5 from the circuit module CMA become potentials of a certain logic level (“H” or “L”).

  At this time, the potential of the output signal SB6 from the circuit module CMB is in a high impedance state, but the output control signal SB3 is inputted at "L" to the AND gate A11 to which it is inputted. Therefore, the output of the AND gate A11 is “L”, and the through current due to the output signal SB6 being in the high impedance state does not flow in the circuit module CMA that is the destination of the output signal SB6.

  After a predetermined period has elapsed since the control signal SA1 was set to “H”, the circuit module CMD sets the output control signal SA3 related to the circuit module CMA to “H”. As a result, the output signals SA4 and SA5 from the circuit module CMA are supplied to the receiving circuit via the AND gates D11 and B11. Note that a predetermined period from when the control signal SA1 is set to “H” to when the output control signal SA3 is set to “H” is referred to a predetermined rise time of the second power supply circuit PSA, and the second power supply The time may be the same as or longer than the time when the output of the power supply voltage SA2 from the circuit PSA is started.

  As described above, when the second power supply circuit PSA is turned on and the supply of the power supply voltage SA2 to the circuit module CMA is started, the second power supply circuit PSA is controlled by the control signal SA1 to supply power to the circuit module CMA. After the voltage SA2 is supplied, the output signals SA4 and SA5 from the circuit module CMA are output as the outputs of the AND gates D11 and B11 by the output control signal SA3. As a result, regardless of the state of the output signals SA4 and SA5 from the circuit module CMA, it is possible to prevent the input of the circuit serving as the reception destination from being in a floating state and prevent a through current from flowing. .

  Subsequently, when the third power supply circuit PSB is turned on, the control signal SB1 corresponding to the third power supply circuit PSB is first set to “H” as in the case of turning on the second power supply circuit PSA. The third power supply circuit PSB is turned on, and the power supply voltage SB2 is supplied from the third power supply circuit PSB to the circuit module CMB. After the power supply voltage SB2 is supplied to the circuit module CMB, the output control signal SB3 is set to “H” so that the output signals SB4, SB5, and SB6 from the circuit module CMB are output as the outputs of the AND gates D12, C11, and A11. To.

  Similarly, when the fourth power supply circuit PSC is turned on, the fourth power supply circuit PSC is controlled by the control signal SC1 corresponding to the fourth power supply circuit PSC, and the power supply voltage SC2 is supplied to the circuit module CMC. Thereafter, the output control signal SC3 is controlled so that the output signals SC4 and SC5 from the circuit module CMC are output as the outputs of the AND gates D13 and B12.

  Conversely, when the fourth power supply circuit PSC is turned off, the circuit module CMD sets the output control signal SC3 to “L” and the AND gates to which the output signals SC4 and SC5 from the circuit module CMC are input. The outputs of D13 and B12 are fixed to “L”. Thereafter, the circuit module CMD sets the control signal SC1 to “L”, turns off the fourth power supply circuit PSC, and cuts off the supply of the power supply voltage SC2 from the fourth power supply circuit PSC to the circuit module CMC.

  As described above, when the supply of the power supply voltage SC2 to the circuit module CMC is interrupted, the outputs of the AND gates D13 and B12 are fixed to the potential “L” by the output control signal SC3, and then the fourth signal is output by the control signal SC1. The power supply circuit PSC is controlled to cut off the supply of the power supply voltage SC2 to the circuit module CMC. Thereby, it is possible to prevent the input of the circuit that receives the output signals SA4 and SA5 from the circuit module CMA from being in a floating state, thereby preventing the through current from flowing.

  Similarly, when the supply of the power supply voltage SB2 to the circuit module CMB is interrupted, the output potential of the AND gates D12, C11, A11 is fixed by the output control signal SB3, and then the third power supply circuit PSB is controlled by the control signal SB1. To supply the power supply voltage SB2 to the circuit module CMB. The same applies when the supply of the power supply voltage SA2 to the circuit module CMA is cut off.

  The power-on sequence and the power-off sequence (shut-off sequence) are not limited to those shown in FIG. 2A. For example, the power-on sequence and the power-off sequence shown in FIGS. Any combination of the above is possible. Further, it is not necessary to shut off the power in the reverse order of the power-on sequence. Further, it is not necessary to turn on or off the power in another power circuit after completion of power on or off in a certain power circuit, and a control operation related to power on or off is performed as shown in FIGS. 2G to 2J. There may be overlapping parts in time.

  2B to 2J are timing charts showing other examples of the power supply control sequence of the semiconductor integrated circuit LSI1 according to the first embodiment. Although the power-on sequence and the power-off sequence are different, one set includes SA1, SA2, and SA3, one set includes SB1, SB2, and SB3, and the other set includes SC1, SC2, and SC3. Since the control signal and the output control signal may be controlled in the above-described control order, detailed description will be omitted, and only the power-on order and the power-off order shown in the drawings will be shown below.

In FIG. 2B, the power is turned on in the order of the first power supply circuit PSL → the third power supply circuit PSB → the fourth power supply circuit PSC → the second power supply circuit PSA, and the second power supply circuit PSA → the fourth power supply. FIG. 6 is a diagram showing a case of cutting in the order of circuit PSC → third power supply circuit PSB → first power supply circuit PSL.
In FIG. 2C, power is turned on in the order of the first power supply circuit PSL → the fourth power supply circuit PSC → the second power supply circuit PSA → the third power supply circuit PSB, and the third power supply circuit PSB → the second power supply. It is the figure which showed the case where it cut | disconnects in order of circuit PSA-> 4th power supply circuit PSC-> 1st power supply circuit PSL.

In FIG. 2D, power is turned on in the order of the first power supply circuit PSL → second power supply circuit PSA → fourth power supply circuit PSC → third power supply circuit PSB, and the third power supply circuit PSB → fourth power supply. FIG. 6 is a diagram showing a case of cutting in the order of circuit PSC → second power supply circuit PSA → first power supply circuit PSL.
In FIG. 2E, the power is turned on in the order of the first power supply circuit PSL → the third power supply circuit PSB → the second power supply circuit PSA → the fourth power supply circuit PSC, and the fourth power supply circuit PSC → the second power supply. FIG. 6 is a diagram showing a case of cutting in the order of circuit PSA → third power supply circuit PSB → first power supply circuit PSL;

In FIG. 2F, power is turned on in the order of the first power supply circuit PSL → the fourth power supply circuit PSC → the third power supply circuit PSB → the second power supply circuit PSA, and the second power supply circuit PSA → the third power supply. It is the figure which showed the case where it cut | disconnects in order of circuit PSB-> 4th power supply circuit PSC-> 1st power supply circuit PSL.
In FIG. 2G, power is turned on in the order of the first power supply circuit PSL → second power supply circuit PSA and fourth power supply circuit PSC → third power supply circuit PSB, and the third power supply circuit PSB → second power supply. It is the figure which showed the case where it cut | disconnects in order of the circuit PSA and 4th power supply circuit PSC-> 1st power supply circuit PSL.

In FIG. 2H, the power is turned on in the order of the first power supply circuit PSL → the second power supply circuit PSA and the third power supply circuit PSB → the fourth power supply circuit PSC, and the fourth power supply circuit PSC → the second power supply. It is a diagram showing a case where the circuit PSA and the third power supply circuit PSB are disconnected in the order of the first power supply circuit PSL.
FIG. 2I shows that the power is turned on in the order of the first power supply circuit PSL → the third power supply circuit PSB and the fourth power supply circuit PSC → the second power supply circuit PSA, and the second power supply circuit PSA → the third power supply. It is the figure which showed the case where it cut | disconnects in order of the circuit PSB and 4th power supply circuit PSC-> 1st power supply circuit PSL.
In FIG. 2J, the power is turned on in the order of the first power supply circuit PSL → second to fourth power supply circuits PSA, PSB, PSC, and the second to fourth power supply circuits PSA, PSB, PSC → first power supply. It is the figure which showed the case where it cut | disconnects in order of the circuit PSL.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
FIG. 3 is a diagram showing a configuration example of the semiconductor integrated circuit LSI2 according to the second embodiment of the present invention. In FIG. 3, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted. In FIG. 3, OR gates A21, B21, B22, C21, D21, D22, and D23 correspond to the AND gates A11, B11, B12, C11, D11, D12, and D13 shown in FIG.

  The semiconductor integrated circuit LSI2 according to the second embodiment is an AND gate to which output signals from the circuit modules CMA, CMB, CMC that are turned on / off in the semiconductor integrated circuit LSI1 according to the first embodiment are input. Is changed to an OR gate.

  That is, in the semiconductor integrated circuit LSI2 according to the second embodiment, the output ends of the circuit modules CMA, CMB, CMC whose power is turned on / off are connected to one input end of the OR gate, and the output control signals SA3, SB3 , SC3 is connected to the other input terminal of the OR gate. The input terminal of the circuit that receives the output signals from the circuit modules CMA, CMB, and CMC is connected to the output terminal of the OR gate.

4A to 4C are timing charts respectively showing an example of a power supply control sequence of the semiconductor integrated circuit LSI2 according to the second embodiment.
Since the power supply control sequence of the semiconductor integrated circuit LSI2 according to the second embodiment uses an OR gate instead of the AND gate as described above, the output control signals SA3, SB3, and SC3 are inverted. Since only the difference is the same as the power supply control sequence of the semiconductor integrated circuit LSI1 according to the first embodiment, a detailed description thereof will be omitted. Only the power-on sequence and the power-off sequence shown in each figure are shown below.

In FIG. 4A, power is turned on in the order of the first power circuit PSL → second power circuit PSA → third power circuit PSB → fourth power circuit PSC, and the fourth power circuit PSC → third power source. FIG. 5 is a diagram showing a case of cutting in the order of circuit PSB → second power supply circuit PSA → first power supply circuit PSL.
In FIG. 4B, power is turned on in the order of the first power supply circuit PSL → the third power supply circuit PSB → the fourth power supply circuit PSC → the second power supply circuit PSA, and the second power supply circuit PSA → the fourth power supply. FIG. 6 is a diagram showing a case of cutting in the order of circuit PSC → third power supply circuit PSB → first power supply circuit PSL.
In FIG. 4C, power is turned on in the order of the first power supply circuit PSL → the fourth power supply circuit PSC → the second power supply circuit PSA → the third power supply circuit PSB, and the third power supply circuit PSB → the second power supply. It is the figure which showed the case where it cut | disconnects in order of circuit PSA-> 4th power supply circuit PSC-> 1st power supply circuit PSL.

  If the output from the circuit modules CMA, CMB, and CMC becomes high impedance even when the AND gate is changed to the OR gate in this way, the output control signals SA3, SB3, and SC3 are set to “H” to set the OR gate. The output is fixed at the potential “H” and supplied to the receiver of the output from the circuit modules CMA, CMB, and CMC. Thereby, it is possible to prevent the input of the circuit that receives the output from the circuit modules CMA, CMB, and CMC from being in a floating state, thereby preventing a through current from flowing.

(Third embodiment)
Next, a third embodiment of the present invention will be described.
The semiconductor integrated circuit according to the third embodiment described below uses AND gates and OR gates together as logic gates to which output signals from circuit modules CMA, CMB, and CMC that are turned on / off are input. Yes, an AND gate or an OR gate is appropriately used according to the destination of each output signal from the circuit modules CMA, CMB, CMC.

  Specifically, an AND gate is used when the circuit receiving the output signals from the circuit modules CMA, CMB, and CMC is active high, and an OR gate is used when the circuit is active low.

  FIG. 5 is a diagram showing a configuration example of the semiconductor integrated circuit LSI3 according to the third embodiment of the present invention. In FIG. 5, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  In FIG. 5, the output signal SA7 and the output control signal SA3 ′ are input to the receiver of the output signal SA7 from the internal circuit module ICA in the circuit module CMA that is turned on / off, and the output is the output signal SA7. An OR gate D31 is provided to supply to the receiver. Further, the output signal SA8 and the output control signal SA3 ′ are input to the receiver of the output signal SA8 from the internal circuit module ICA, and the output is sent to the internal circuit module ICB in the circuit module CMB that is the receiver of the output signal SA8. An OR gate B31 is provided.

  In FIG. 5, the OR gate is used only for the output signal from the internal circuit module ICA in the circuit module CMA, but this is an example. As for output signals from the internal circuit modules ICB and ICC in the circuit modules CMB and CMC, an OR gate can be used by providing an output control signal for controlling the OR gate as necessary.

6A to 6C are timing charts respectively showing an example of a power supply control sequence of the semiconductor integrated circuit LSI3 according to the third embodiment.
The power supply control sequence of the semiconductor integrated circuit LSI3 according to the third embodiment is different from the power supply control sequences in the above-described embodiments in that the four control elements SA3 ′ are controlled as one set in addition to SA1, SA2, and SA3. Therefore, the power supply control sequence of the semiconductor integrated circuit LSI3 according to the third embodiment is the same as the power supply control sequence in each embodiment and is clear from the above description, and thus detailed description thereof is omitted and illustrated in each drawing. Only the power-on sequence and the power-off sequence are shown below.

In FIG. 6A, power is turned on in the order of the first power supply circuit PSL → second power supply circuit PSA → third power supply circuit PSB → fourth power supply circuit PSC, and the fourth power supply circuit PSC → third power supply. FIG. 5 is a diagram showing a case of cutting in the order of circuit PSB → second power supply circuit PSA → first power supply circuit PSL.
In FIG. 6B, power is turned on in the order of the first power supply circuit PSL → the third power supply circuit PSB → the fourth power supply circuit PSC → the second power supply circuit PSA, and the second power supply circuit PSA → the fourth power supply. FIG. 6 is a diagram showing a case of cutting in the order of circuit PSC → third power supply circuit PSB → first power supply circuit PSL.
FIG. 6C shows the first power supply circuit PSL → the fourth power supply circuit PSC → the second power supply circuit PSA → the third power supply circuit PSB, and the third power supply circuit PSB → the second power supply. It is the figure which showed the case where it cut | disconnects in order of circuit PSA-> 4th power supply circuit PSC-> 1st power supply circuit PSL.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described.
FIG. 7 is a diagram showing a configuration example of the semiconductor integrated circuit LSI4 according to the fourth embodiment of the present invention. In FIG. 7, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  The semiconductor integrated circuit LSI4 according to the fourth embodiment includes a nonvolatile memory NV that holds control signals SA1, SB1, and SC1 and output control signals SA3, SB3, SC3, and SD3 output from the circuit module CMD. That is, in the semiconductor integrated circuit LSI4, the control signals SA1, SB1, and SC1 and the output control signals SA3, SB3, SC3, and SD3 output from the circuit module CMD are transmitted to the respective logic gates (see FIG. 7) through the nonvolatile memory NV. In the example shown, it is supplied to an AND gate).

  As described above, the control signals SA1, SB1, SC1 and the output control signals SA3, SB3, SC3, SD3 output from the circuit module CMD are supplied to each logic gate via the nonvolatile memory NV. Also, the supply of the power supply voltage S0 can be cut off for the circuit module CMD.

  Further, as the supply of the power supply voltage S0 to the circuit module CMD can be cut off, the signals SA6, SB7, and SC6 are passed through AND gates A41, B41, and C41 to which the output control signal SD3 is supplied. To the circuit modules CMA, CMB, and CMC.

  FIG. 8 is a timing chart showing an example of a power supply control sequence of the semiconductor integrated circuit LSI4 according to the fourth embodiment. The power control sequence shown in FIG. 8 is basically the same as the power control sequence of the semiconductor integrated circuit LSI1 according to the first embodiment shown in FIG. 2A. However, in the semiconductor integrated circuit LSI4 according to the fourth embodiment, the control signals SA1, SB1, SC1 and the output control signals SA3, SB3, SC3, SD3 are supplied to the respective logic gates via the nonvolatile memory NV. Even if the supply of the power supply voltage S0 to the CMD is cut off, the state of these signals is maintained.

  As described above, according to each embodiment, as for the output signal from the circuit module whose power is turned on / off, the output signal from the circuit module whose power is turned on / off is input to one input, and the other A logic gate is provided that inputs an output control signal to the input of the power supply and supplies the output to a destination of the output signal from the circuit module whose power is turned on / off. When starting and shutting off the supply of power to a circuit module whose power is turned on / off, after the power supply voltage is supplied to the circuit module whose power is turned on / off, the output signal is logically gated. And the supply of the power supply voltage to the circuit module whose power is turned on / off after the output of the logic gate is fixed to a predetermined potential is cut off.

  As a result, regardless of the output of the circuit module that is turned on / off, the input of the circuit that receives the signal output from the circuit module that is turned on / off is in the floating state. It is possible to prevent the through current from flowing. In other words, even if the output of the circuit module to which the power is turned on / off becomes high impedance, the through current flows in the circuit that receives the signal output from the circuit module to which the power is turned on / off. This can prevent the wasteful power consumption.

Further, not only a signal from a circuit module whose power is turned on / off to a circuit module whose power is always on, but also a signal passed between circuit modules whose power is turned on / off, It can be prevented from flowing, and wasteful power consumption can be reduced.
In addition, each control signal and each output control signal are comprehensively controlled by the circuit module CMD that is a control circuit, so that each control circuit is provided in correspondence with each circuit module that is turned on / off. The area can be reduced.
In the fourth embodiment, by providing the non-volatile memory NV, the supply of the power supply voltage to the circuit module CMD can be cut off, and the power consumption can be reduced.

In the first to fourth embodiments described above, four power supply circuits PSA, PSB, PSC, and PSL are connected to the semiconductor integrated circuits LSI1 to LSI4. However, the present invention is not limited to this and the power supply is not limited thereto. The number of circuits is arbitrary, and the number of power supply circuits connected to the semiconductor integrated circuit may be more than four or less than four. Even if there is only one power supply circuit, it may be configured to switch whether or not to supply the power supply voltage to the circuit modules CMA, CMB, and CMC.
In addition, the circuit modules CMA, CMB, and CMC, which are circuits that are turned on / off, and the power supply circuits PSA, PSB, and PSC for supplying the power supply voltage to the circuit modules have a one-to-one correspondence. A plurality of circuit modules may be connected to one power supply circuit.
Further, the number of circuit modules to be turned on / off is also arbitrary.

  In the first to fourth embodiments described above, a two-input AND gate and a two-input OR gate are used as logic gates for inputting an output signal from a circuit module that is turned on / off. However, the present invention is not limited to this, and an arbitrary logic gate having at least two input terminals can be used, and an output control signal may be appropriately set according to the logic gate.

The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Various aspects of the present invention will be described below as supplementary notes.

(Appendix 1) a first circuit to which a power supply voltage is constantly supplied;
A second circuit in which supply of the power supply voltage may be interrupted;
An output terminal of the second circuit is connected to the first input terminal, and a logic circuit having at least two input terminals to which an output control signal is supplied to the second input terminal,
When the supply of the power supply voltage to the second circuit is started, after the power supply voltage is supplied to the second circuit, the logic circuit outputs the output of the second circuit by the output control signal. Like
When the supply of power supply voltage to the second circuit is cut off, the output of the logic circuit is fixed at a predetermined potential by the output control signal, and then the supply of power supply voltage to the second circuit is cut off. A semiconductor integrated circuit.
(Supplementary note 2) The semiconductor integrated circuit according to Supplementary note 1, wherein the logic circuit is a two-input AND circuit.
(Supplementary note 3) The semiconductor integrated circuit according to Supplementary note 1, wherein the logic circuit is a two-input OR circuit.
(Supplementary note 4) The semiconductor integrated circuit according to any one of supplementary notes 1 to 3, wherein a buffer circuit is inserted into a signal line of a signal input to the second circuit.
(Supplementary note 5) The semiconductor integrated circuit according to any one of supplementary notes 1 to 4, further comprising a control circuit that controls the power supply circuit that supplies the power supply voltage and outputs the output control signal.
(Supplementary note 6) The semiconductor integrated circuit according to Supplementary note 5, further comprising a nonvolatile memory for holding an output control signal output from the control circuit.
(Supplementary Note 7) A first circuit to which power supply voltage is constantly supplied and a second circuit in which supply of power supply voltage may be interrupted are provided, and an output terminal of the second circuit is a first input terminal And a power supply-separated semiconductor integrated circuit control method comprising a logic circuit having at least two input terminals to which an output control signal is supplied to a second input terminal,
When the supply of the power supply voltage to the second circuit is started, the power supply circuit that supplies the power supply voltage is controlled to supply the power supply voltage to the second circuit, and then the output of the logic circuit A control method of a semiconductor integrated circuit, wherein the output control signal is controlled so that an output of a second circuit is output.
(Supplementary Note 8) A first circuit to which power supply voltage is constantly supplied and a second circuit in which supply of power supply voltage may be interrupted are provided, and an output terminal of the second circuit is a first input terminal And a power supply-separated semiconductor integrated circuit control method comprising a logic circuit having at least two input terminals to which an output control signal is supplied to a second input terminal,
When the supply of the power supply voltage to the second circuit is cut off, the output of the logic circuit is fixed to a predetermined potential by the output control signal, and then the power supply circuit that supplies the power supply voltage is controlled to control the second circuit. A method for controlling a semiconductor integrated circuit, wherein supply of power supply voltage to the circuit is cut off.

1 is a diagram illustrating a configuration example of a semiconductor integrated circuit according to a first embodiment of the present invention. It is a timing chart which shows an example of the power supply control sequence in 1st Embodiment. It is a timing chart which shows the other example of the power supply control sequence in 1st Embodiment. It is a timing chart which shows the other example of the power supply control sequence in 1st Embodiment. It is a timing chart which shows the other example of the power supply control sequence in 1st Embodiment. It is a timing chart which shows the other example of the power supply control sequence in 1st Embodiment. It is a timing chart which shows the other example of the power supply control sequence in 1st Embodiment. It is a timing chart which shows the other example of the power supply control sequence in 1st Embodiment. It is a timing chart which shows the other example of the power supply control sequence in 1st Embodiment. It is a timing chart which shows the other example of the power supply control sequence in 1st Embodiment. It is a timing chart which shows the other example of the power supply control sequence in 1st Embodiment. It is a figure which shows the structural example of the semiconductor integrated circuit by the 2nd Embodiment of this invention. It is a timing chart which shows an example of the power supply control sequence in 2nd Embodiment. It is a timing chart which shows the other example of the power supply control sequence in 2nd Embodiment. It is a timing chart which shows the other example of the power supply control sequence in 2nd Embodiment. It is a figure which shows the structural example of the semiconductor integrated circuit by the 3rd Embodiment of this invention. It is a timing chart which shows an example of the power supply control sequence in 3rd Embodiment. It is a timing chart which shows the other example of the power supply control sequence in 3rd Embodiment. It is a timing chart which shows the other example of the power supply control sequence in 3rd Embodiment. It is a figure which shows the structural example of the semiconductor integrated circuit by the 4th Embodiment of this invention. It is a timing chart which shows an example of the power supply control sequence in 4th Embodiment.

Explanation of symbols

CMA, CMB, CMC, CMD Circuit module ICA, ICB, ICC Internal circuit module PSL, PSA, PSB, PSC Power supply circuit A11, B11, B12, C11, D11 to D13 Logic gates SA1, SB1, SC1 Control signals SA3, SB3, SC3 output control signal

Claims (7)

A first circuit to which a power supply voltage is constantly supplied;
A second circuit in which supply of the power supply voltage may be interrupted;
An output terminal of the second circuit is connected to the first input terminal, and a logic circuit having at least two input terminals to which an output control signal is supplied to the second input terminal,
When the supply of the power supply voltage to the second circuit is started , the output of the logic circuit is fixed at a predetermined potential based on the output control signal, and the power supply voltage is supplied to the second circuit. The logic circuit outputs the output of the second circuit by the output control signal,
When cutting off the supply of power supply voltage to the second circuit, after fixing the output of the logic circuit to a predetermined potential based on the output control signal, supply of power supply voltage to the second circuit is performed. A semiconductor integrated circuit characterized by being cut off.   2. The semiconductor integrated circuit according to claim 1, wherein a buffer circuit is inserted into a signal line of a signal input to the second circuit.   3. The semiconductor integrated circuit according to claim 1, further comprising a control circuit that controls the power supply circuit that supplies the power supply voltage and outputs the output control signal. A first circuit to which power supply voltage is always supplied and a second circuit in which supply of power supply voltage may be interrupted, and an output terminal of the second circuit is connected to a first input terminal, And a method of controlling a power-separated semiconductor integrated circuit comprising a logic circuit having at least two input terminals to which an output control signal is supplied to a second input terminal,
When the supply of the power supply voltage to the second circuit is started , the output of the logic circuit is fixed to a predetermined potential based on the output control signal, and the power supply voltage is supplied to the second circuit. The output of the second circuit is output as the output of the logic circuit ,
When the supply of power supply voltage to the second circuit is cut off, the supply of power supply voltage to the second circuit is cut off after fixing the output of the logic circuit to a predetermined potential based on the output control signal A method of controlling a semiconductor integrated circuit. 4. The semiconductor integrated circuit according to claim 3, further comprising a non-volatile memory that holds an output control signal output from the control circuit. 6. The semiconductor integrated circuit according to claim 5, wherein supply of power supply voltage to the control circuit can be cut off. 7. The through current flowing in the semiconductor integrated circuit is prevented by fixing the output of the logic circuit to a predetermined potential based on the output control signal. A semiconductor integrated circuit according to 1.

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