JP2008177755A - Level shift circuit and semiconductor device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shift circuit inhibiting the unstable state of the level of an output signal. <P>SOLUTION: In a first transistor M1, a first terminal is grounded, and a logical signal S1 is input to a gate. In a second transistor M2, the first terminal is grounded, and the inversion signal *S1 of the logical signal S1 is input to the gate. In a first inverter 12, an input terminal is connected to a second terminal for the first transistor, an output terminal is connected to the second terminal for the second transistor M2, and the first inverter 12 receives a second power-supply voltage AVDD and is operated. In a second inverter 14, the input terminal is connected to the second terminal for the second transistor M2, the output terminal is connected to the second terminal for the first transistor M1 and the second inverter 14 receives the second power-supply voltage AVDD and is operated. In a reset transistor M5, a fixed voltage is applied to the first terminal, the first terminal is connected to the second terminal for the first transistor M1 and a reset signal is input to the gate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a level shift circuit that is provided between circuit blocks that operate with different power supply voltages and converts a signal level.

  In an electronic circuit including a plurality of circuit blocks, a different power supply voltage may be supplied for each circuit block in order to reduce power consumption. For example, when an analog circuit and a digital circuit exist, a power supply voltage of about 3V is supplied to the analog circuit, and a power supply voltage of about 1.5V is supplied to the digital circuit.

In the case of outputting a logic signal that takes two values, high and low, from the digital circuit to the analog circuit, even if 1.5 V that is the high level of the digital circuit is output, the analog circuit does not recognize the high level. Therefore, a level shift circuit for converting a signal level (voltage level) is provided between the two circuit blocks.
JP 2004-38513 A JP 2004-234619 A

  The level shift circuit has a problem that the level of the output signal becomes unstable when the level of the input logic signal is indefinite. Further, even when the power supply voltage supplied to the level shift circuit itself is insufficient, the level of the output signal becomes unstable.

  The present invention has been made in view of these problems, and a comprehensive object thereof is to provide a level shift circuit that suppresses an indefinite level of an output signal.

  According to one aspect of the present invention, a logic signal output from a first circuit block that operates at a first power supply voltage is received, level-converted, and output to a second circuit block that operates at a second power supply voltage higher than the first power supply voltage. The present invention relates to a level shift circuit. The level shift circuit includes a first transistor having a first terminal grounded and the logic signal input to a gate; a second transistor having a first terminal grounded and an inverted signal of the logic signal input to the gate; A first inverter having an input terminal connected to the second terminal of the first transistor, an output terminal connected to the second terminal of the second transistor and receiving a second power supply voltage; and an input terminal of the second transistor The second terminal is connected to the second terminal, the output terminal is connected to the second terminal of the first transistor, the second inverter operates by receiving the second power supply voltage, the fixed voltage is applied to the first terminal, and the second terminal is connected to the second terminal. And a reset transistor connected to a second terminal of any one of the first and second transistors and having a reset signal input to a gate. The level shift circuit outputs a signal corresponding to the signal at the second terminal of either the first or second transistor to the second circuit block.

  According to this aspect, the level of the output signal of the level shift circuit can be fixed by controlling the logic level of the reset signal when the logic signal is indefinite or the first and second power supply voltages are insufficient. it can.

  The fixed voltage applied to the first terminal of the reset transistor may be the second power supply voltage.

  The signal may be a low level during a period in which the level of the output signal of the level shift circuit is to be fixed. The reset signal may be a signal that becomes a low level in a state where the first power supply voltage is insufficient.

  The reset signal may be a signal corresponding to the second power supply voltage. The reset signal may be a signal that rises with delay with respect to the second power supply voltage.

  In a level shift circuit according to an aspect, in place of the first inverter, a third transistor in which a first terminal is connected to a terminal to which a second power supply voltage is applied and a second terminal is connected to a second terminal of the first transistor. May be provided. Instead of the second inverter, the level shift circuit includes a fourth transistor having a second terminal connected to a terminal to which the second power supply voltage is applied and a second terminal connected to the second terminal of the second transistor. Also good. The second terminal of the first transistor may be connected to the gate of the third transistor, and the second terminal of the second transistor may be connected to the gate of the fourth transistor.

  The level shift circuit may be integrated on one semiconductor substrate together with the first and second circuit blocks. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

  Another embodiment of the present invention is a semiconductor device. This semiconductor device receives a digital circuit that operates at a first power supply voltage, an analog circuit that operates at a second power supply voltage that is higher than the first power supply voltage, and a logic signal output from the digital circuit, performs level conversion, and an analog circuit And a level shift circuit that outputs to the output. The analog circuit includes a power supply circuit that operates based on a logic signal output from the level shift circuit and generates a first power supply voltage. The level shift circuit includes a first transistor having a first terminal grounded and a logic signal input to a gate; a second transistor having a first terminal grounded and an inverted signal of the logic signal input to a gate; and an input terminal Is connected to the second terminal of the first transistor, the output terminal is connected to the second terminal of the second transistor, receives the second power supply voltage and operates, and the input terminal is the second terminal of the second transistor. Connected to the second terminal of the first transistor, the output terminal is connected to the second inverter that operates in response to the second power supply voltage, and the first terminal is connected to the input terminal of either the first or second inverter. A reset transistor in which a fixed voltage is applied to the second terminal and a reset signal is input to the gate, and a signal corresponding to the output signal of either the first or second inverter is analyzed. And outputs it to the grayed circuit.

  According to this aspect, in a state where the second power supply voltage for the analog circuit is insufficient, the power supply circuit cannot generate the first power supply voltage. At this time, the digital circuit does not operate normally and the logic signal becomes indefinite. In such a case, it is possible to prevent the output signal of the level shift circuit from becoming unstable by appropriately setting the logic level of the reset signal.

  It should be noted that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other between devices, systems, etc. are also effective as an aspect of the present invention.

  According to the present invention, it is possible to suppress the level of the output signal of the level shift circuit from becoming unstable.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state where the member A and the member B are connected” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. It includes the case of being indirectly connected through another member that does not affect the connection state.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical connection. The case where it is indirectly connected through another member that does not affect the state is also included.

  FIG. 1 is a circuit diagram showing a configuration of a level shift circuit 10 according to an embodiment of the present invention. The level shift circuit 10 receives the logic signal S1 output from the first circuit block CB1 that operates at the first power supply voltage DVDD, performs level conversion, and operates at the second power supply voltage AVDD that is higher than the first power supply voltage DVDD. Output to the circuit block CB2.

  The level shift circuit 10 includes a first transistor M1, a second transistor M2, a first inverter 12, a second inverter 14, a first output inverter 16, a second output inverter 18, an input inverter 22, and a reset transistor M5.

The input inverter 22 operates in response to the first power supply voltage DVDD and inverts the logic signal S1 input to the input terminal 102.
The first transistor M1 is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the first terminal (source) is grounded. The logic signal S1 is input to the gate of the first transistor M1.
The second transistor M2 is an N-channel MOSFET, the first terminal (source) is grounded, and the logic signal * S1 inverted by the input inverter 22 is input to the gate.

The first inverter 12 and the second inverter 14 operate by receiving the second power supply voltage AVDD. The input terminal of the first inverter 12 is connected to the second terminal (drain) of the first transistor M1, and its output terminal is connected to the second terminal (drain) of the second transistor M2.
The input terminal of the second inverter 14 is connected to the second terminal (drain) of the second transistor M2, and its output terminal is connected to the second terminal (drain) of the first transistor M1.

  The size of the transistors constituting the first inverter 12 and the second inverter 14 (W / L, W represents the gate width, L represents the gate length) should be smaller than the transistor sizes of the first transistor M1 and the second transistor M2. Is desirable.

  The reset transistor M5 is a P-channel MOSFET, and the first terminal (source) is connected to the input terminal of either the first inverter 12 or the second inverter 14. In the present embodiment, the second terminal (drain) of the reset transistor M5 is connected to the input terminal of the first inverter 12. A fixed voltage is applied to the first terminal (source) of the reset transistor M5. In the present embodiment, the fixed voltage is the second power supply voltage AVDD. A reset signal RST is input to the gate of the reset transistor M5.

  The reset signal RST is a signal that takes a logical value for turning on the reset transistor M5 in a period in which the logical level of the output signal S2 for the second circuit block CB2 is to be fixed. In the circuit of FIG. 1, the reset signal RST is at a low level during a period in which the logic level of the output signal S2 is to be fixed. For example, in a state where the first power supply voltage DVDD is insufficient, the level is low.

The level shift circuit 10 outputs a signal corresponding to the output signal of either the first inverter 12 or the second inverter 14 to the second circuit block CB2. The level shift circuit 10 in FIG. 1 outputs a signal corresponding to the output signal of the first inverter 12.
The first output inverter 16 and the second output inverter 18 are cascade-connected and operate in response to the second power supply voltage AVDD. The first output inverter 16 inverts the output signal of the first inverter 12, and the second output inverter 18 inverts the output signal of the first output inverter 16. The output signal of the second output inverter 18 is output from the output terminal 104 to the second circuit block CB2 as the output of the level shift circuit 10.

The operation of the level shift circuit 10 configured as described above will be described.
When the first power supply voltage DVDD and the second power supply voltage AVDD have normal values, the reset signal RST is set to a high level (that is, AVDD). At this time, the reset transistor M5 is turned off. The logic signal S1 output from the first circuit block CB1 takes either a low level (0V) or a high level (DVDD).

When the logic signal S1 is at a low level, the first transistor M1 is turned off and the second transistor M2 is turned on. When the second transistor M2 is turned on, the input level of the second inverter 14 becomes low level, and its output level becomes high level. The first inverter 12 and the second inverter 14 hold the first node N1 at a low level (0V) and the second node N2 at a high level (AVDD).
When the first node N1 is at a low level (0 V), the output signal S2 of the level shift circuit 10 is at a low level.

Conversely, when the logic signal S1 is at a high level, the first transistor M1 is turned on and the second transistor M2 is turned off. When the first transistor M1 is turned on, the input level of the first inverter 12 becomes low level, and its output level becomes high level. The first inverter 12 and the second inverter 14 hold the first node N1 at a high level and the second node N2 at a low level.
When the first node N1 is at the high level (AVDD), the output signal S2 of the level shift circuit 10 is at the high level.

  Next, an operation when the logic signal S1 input to the level shift circuit 10 becomes indefinite will be described. Such a situation may occur when only the second power supply voltage AVDD is stably supplied and the first power supply voltage DVDD is insufficient.

  At this time, the reset signal RST is set to a low level. As a result, the reset transistor M5 is turned on, and the second node N2 is fixed to the high level (AVDD). The first node N1 at this time is fixed at a low level by the first inverter 12 and the second inverter 14. Therefore, the output signal S2 of the level shift circuit 10 is fixed at a low level.

  Thus, according to the level shift circuit 10 according to the present embodiment, it is possible to prevent the logic level of the output signal S2 from becoming indefinite when the logic signal S1 is indefinite. As a result, it is possible to prevent the operation of the second circuit block CB2 from becoming unstable.

FIG. 2 is a block diagram showing a configuration of a semiconductor device 200 using the level shift circuit 10 of FIG. The semiconductor device 200 includes a level shifter 100, a digital circuit 20, and an analog circuit 30. In the block diagram of FIG. 2, the analog circuit 30 corresponds to the second circuit block CB <b> 2 of FIG. 1 and the first circuit block CB <b> 1 of the digital circuit 20.
The level shift circuit 10 level-shifts some control signals Sc output from the digital circuit 20 and outputs them to the analog circuit 30. That is, the level shifter 100 of FIG. 2 includes a plurality of level shift circuits 10 that use the control signal Sc as the input signal S1.

The level shift circuit 10, the digital circuit 20, and the analog circuit 30 are integrated on a single semiconductor substrate.
The digital circuit 20 operates with the first power supply voltage DVDD. The analog circuit 30 operates at a second power supply voltage AVDD that is higher than the first power supply voltage DVDD. The analog circuit 30 includes a power supply circuit 32 that generates a first power supply voltage DVDD to be supplied to the digital circuit 20 and another analog circuit 34. The digital circuit 20 generates a control signal Sc for controlling the analog circuit 30. The level shift circuit 10 receives the control signal Sc output from the digital circuit 20, performs level conversion, and outputs it to the analog circuit 30. The analog circuit 30 operates based on the control signal Sc2 output from the level shifter 100.

  The terminal 204 is a terminal for supplying the first power supply voltage DVDD when the power supply circuit 32 is stopped. A reset signal RST is supplied to the reset terminal 206. In FIG. 2, the reset signal RST is a signal obtained by delaying the rise of the second power supply voltage AVDD by the capacitor C1.

  The circuit operation of FIG. 2 will be described. When the semiconductor device 200 is activated, when the second power supply voltage AVDD rises, it is supplied to the power supply circuit 32, the analog circuit 34, and the level shifter 100. Since a delay occurs until the power supply circuit 32 generates the first power supply voltage DVDD, the first power supply voltage DVDD becomes insufficient immediately after startup. As a result, the control signal Sc1 output from the digital circuit 20 becomes indefinite.

  On the other hand, when the second power supply voltage AVDD rises, the reset signal RST rises from the low level (0 V) to the high level (AVDD) according to the time constant determined by the capacitor C1. That is, immediately after startup, in a state where the reset signal RST is near the low level, the reset transistor M5 in FIG. 1 is turned on, and the logic level of the control signal Sc2 to the analog circuit 30 is fixed.

  Thereafter, when a sufficient first power supply voltage DVDD is generated by the power supply circuit 32, the digital circuit 20 operates normally and the logic level of the control signal Sc1 is determined. At this time, since the reset signal RST is at a high level (AVDD), the control signal Sc2 takes a level determined according to the control signal Sc1.

  As described above, by using the level shift circuit 10 of FIG. 1, it is possible to prevent the level of the control signal from becoming unstable in the semiconductor device 200 in which circuit blocks operating with different power supply voltages are mounted.

  Further, by generating the reset signal RST by delaying the second power supply voltage AVDD, the reset transistor M5 can be turned on only during the period corresponding to the delay time, and the logic level of the control signal Sc2 can be fixed. . When the delay is performed using the capacitor C1, the time constant is defined by the capacitance value of the capacitor C1, and therefore, the time for which the reset transistor M5 is turned on can be suitably controlled.

  The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. .

  FIG. 3 is a circuit diagram showing a configuration of a level shift circuit according to a modification. In the level shift circuit 10a of FIG. 3, the first inverter 12 and the second inverter 14 of FIG. 1 are replaced with a third transistor M3 and a fourth transistor M4 which are P-channel MOSFETs.

  The source of the third transistor M3 is connected to the power supply terminal 106 to which the second power supply voltage AVDD is supplied. The drain of the third transistor M3 is connected to the drain of the first transistor M1. The source of the fourth transistor M4 is supplied with the second power supply voltage AVDD, and the drain thereof is connected to the drain of the second transistor M2. The gate of the third transistor M3 is connected to the drain of the fourth transistor M4, and the gate of the fourth transistor M4 is connected to the drain of the third transistor M3.

  Also in the level shift circuit 10a of FIG. 3, the third transistor M3 and the fourth transistor M4 hold the potentials of the first node N1 and the second node N2. Also in the level shift circuit 10a of FIG. 3, as in the level shift circuit 10 of FIG. 1, the logic level of the output signal S2 can be fixed by turning on the reset transistor M5.

  In the level shift circuit of FIGS. 1 and 3, the number of the first output inverter 16 and the second output inverter 18 is arbitrary, and the second output inverter 18 may not be provided.

  In an embodiment, the drain of the reset transistor M5 may be connected to the first node N1. Further, the reset transistor M5 may be provided between the ground terminal and the second node N2 (or the first node N1). In this case, the reset transistor M5 may be composed of an N channel MOSFET.

  In addition, the replacement of the N-channel MOSFET and the P-channel MOSFET in the circuit of FIG. 1, the replacement of the MOSFET and the bipolar transistor, or the inversion of the power supply terminal and the ground terminal also belongs to the scope of the present invention.

It is a circuit diagram which shows the structure of the level shift circuit which concerns on embodiment of this invention. FIG. 2 is a block diagram showing a configuration of a semiconductor device using the level shift circuit of FIG. 1. It is a circuit diagram which shows the structure of the level shift circuit which concerns on a modification.

Explanation of symbols

  10 level shift circuit, 12 first inverter, 14 second inverter, M1 first transistor, M2 second transistor, M3 third transistor, M4 fourth transistor, M5 reset transistor, CB1 first circuit block, CB2 second circuit block , 20 digital circuit, 30 analog circuit, 32 power supply circuit, 34 analog circuit, 102 input terminal, 104 output terminal, 200 semiconductor device.

Claims (7)

A level shift circuit that receives a logic signal output from a first circuit block that operates at a first power supply voltage, converts the level, and outputs the logical signal to a second circuit block that operates at a second power supply voltage higher than the first power supply voltage. And
A first transistor having a first terminal grounded and a gate receiving the logic signal;
A second transistor having a first terminal grounded and an inverted signal of the logic signal input to the gate;
A first inverter having an input terminal connected to the second terminal of the first transistor, an output terminal connected to the second terminal of the second transistor, and operating in response to the second power supply voltage;
A second inverter having an input terminal connected to the second terminal of the second transistor, an output terminal connected to the second terminal of the first transistor, and operating in response to the second power supply voltage;
A reset transistor in which a fixed voltage is applied to the first terminal, a second terminal is connected to the second terminal of the first or second transistor, and a reset signal is input to the gate;
A level shift circuit that outputs a signal corresponding to the signal at the second terminal of either the first or second transistor to the second circuit block.   The level shift circuit according to claim 1, wherein the fixed voltage applied to the first terminal of the reset transistor is the second power supply voltage.   3. The level shift circuit according to claim 2, wherein the reset signal is a signal that becomes a low level when the first power supply voltage is insufficient.   3. The level shift circuit according to claim 2, wherein the reset signal is a signal that rises with a delay with respect to the second power supply voltage. In place of the first inverter, a third transistor having a first terminal connected to a terminal to which the second power supply voltage is applied and a second terminal connected to a second terminal of the first transistor,
Instead of the second inverter, a fourth transistor having a second terminal connected to a terminal to which the second power supply voltage is applied and a second terminal connected to a second terminal of the second transistor,
Prepared,
5. The device according to claim 1, wherein a second terminal of the first transistor is connected to a gate of the third transistor, and a second terminal of the second transistor is connected to a gate of the fourth transistor. The level shift circuit described in 1.   5. The level shift circuit according to claim 1, wherein the level shift circuit is integrated on a single semiconductor substrate together with the first and second circuit blocks. A digital circuit operating at a first power supply voltage;
An analog circuit operating at a second power supply voltage higher than the first power supply voltage;
A level shift circuit that receives a logic signal output from the digital circuit, converts the level and outputs the logic signal to the analog circuit;
With
The analog circuit includes a power supply circuit that operates based on the logic signal output from the level shift circuit and generates the first power supply voltage,
The level shift circuit includes:
A first transistor having a first terminal grounded and a gate receiving the logic signal;
A second transistor having a first terminal grounded and an inverted signal of the logic signal input to the gate;
A first inverter having an input terminal connected to a second terminal of the first transistor, an output terminal connected to a second terminal of the second transistor, and operating in response to the second power supply voltage;
A second inverter having an input terminal connected to the second terminal of the second transistor, an output terminal connected to the second terminal of the first transistor, and receiving the second power supply voltage;
A reset transistor in which a fixed voltage is applied to the first terminal, a second terminal is connected to an input terminal of the first or second inverter, and a reset signal is input to the gate;
And a signal corresponding to the signal at the second terminal of either the first transistor or the second transistor is output to the analog circuit.

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