JP3915024B2 - Clock synchronization circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock synchronization circuit, and more particularly to a clock synchronization circuit that selects one of a plurality of reference clocks and generates a clock synchronized therewith.
[0002]
[Prior art]
FIG. 6 shows a conventional clock synchronization circuit, which includes a selector 1, a flip-flop 10, an EX-OR type phase comparator 2, a low-pass filter 3, a voltage controlled oscillator (VCO) 4, and a half-minute. And a peripheral 5.
[0003]
Here, the selector 1 receives a selection signal (SEL) from the outside, selects any one of a plurality of reference clocks REF 1 and REF 2 to be input, and supplies the selected clock to the flip-flop 10.
[0004]
The flip-flop 10 receives the reference clock selected by the selector 1 and the inverted output at the input end, and divides the frequency by 1/2, and generates a pulse P1 having a duty ratio of 50% that matches the phase of the selected reference clock. The data is output to one input terminal of the EX-OR type phase comparator 2.
[0005]
Further, a PLL is formed by the EX-OR type phase comparator 2, the low-pass filter 3, the voltage controlled oscillator (VCO) 4, and the 1/2 frequency divider 5, and is synchronized with the selected reference clock. An output clock CLK is generated.
[0006]
The 1/2 divider 5 divides the output clock CLK by 1/2 to generate a pulse P2 having a duty ratio of 50%, and outputs the pulse P2 to the other input terminal of the EX-OR type phase comparator 2.
[0007]
The EX-OR type phase comparator 2 receives the output P1 of the flip-flop 10 and the output P2 of the 1/2 frequency divider 5 and outputs an exclusive OR (EX-OR) thereof.
[0008]
The voltage controlled oscillator (VCO) 4 receives the output of the EX-OR type phase comparator 2 as a control signal through the low-pass filter 3, and generates an output clock CLK synchronized with the selected reference clock.
[0009]
The voltage controlled oscillator (VCO) 4 has a control characteristic in which the frequency decreases with an increase in the output duty of the EX-OR type phase comparator 2, and this PLL is an EX-OR type phase comparator 2. The output P2 of the 1/2 frequency divider 5 that is input to the signal converges to a phase relationship of −90 ° with respect to the output P1 of the flip-flop 10.
[0010]
[Problems to be solved by the invention]
However, in the conventional clock synchronization circuit described above, when the phase difference between the plurality of reference clocks is small, the phase of the output of the flip-flop 10 changes nearly 180 ° when the selector 1 switches to another reference clock. There are problems that it takes time to pull in the PLL and that frequency fluctuations until the establishment of synchronization are large.
[0011]
Hereinafter, the operation at the time of reference clock switching in the conventional clock synchronization circuit will be described.
[0012]
FIG. 7 is a timing chart showing an operation example when the reference clock is switched. When the selector 1 receives the selection signal (SEL) (FIG. 7C) from the outside, the reference clock REF1 (FIG. 7A) is received at time t1. ) To the reference clock REF2 (FIG. 7B).
[0013]
Here, the phase difference between the reference clock REF1 and the reference clock REF2 is, for example, 10 °.
[0014]
First, in a state where the selector 1 selects the reference clock REF1, the output P1 (FIG. 7E) of the flip-flop 10 is a ½ frequency-divided pulse with a duty ratio of 50% that matches the phase of the reference clock REF1. Yes, this pulse P <b> 1 is input to one end of the EX-OR type phase comparator 2.
[0015]
This PLL converges to a state where the phase difference between the two signals input to the EX-OR type phase comparator 2 is 90 °. That is, the output P2 (FIG. 7 (f)) of the 1/2 frequency divider 5 input to the other end of the EX-OR type phase comparator 2 is the output P1 of the flip-flop 10 (FIG. 7 (e)). The phase difference converges to -90 °.
[0016]
At time t1, when switching occurs between the phase difference of 10 ° between the reference clock REF1 and the reference clock REF2, two adjacent reference clocks of the reference clock REF1 and the reference clock REF2 are input to the flip-flop 10 ( In FIG. 7D, the output P1 of the flip-flop 10 changes in a short time from “L” level to “H” level to “L” level as shown in FIG.
[0017]
When the next reference clock REF2 is received, it changes to the “H” level in synchronization with the reference clock REF2. At this time, the phase difference between the output P1 (FIG. 7 (e)) of the flip-flop 10 input to the EX-OR type phase comparator 2 and the output P2 (FIG. 7 (f)) of the 1/2 frequency divider 5 is -280 °.
[0018]
Therefore, a large phase change of 190 ° is required from the phase difference of −280 ° to the PLL convergence state of −90 °, and the phase difference between the reference clock REF1 and the reference clock REF2 is 10 °. Nevertheless, an extremely large phase change (190 °) occurs, it takes time to pull in the PLL, and the frequency fluctuation until the synchronization is established also increases.
[0019]
SUMMARY OF THE INVENTION An object of the present invention is to provide a clock synchronization circuit that selects one of a plurality of reference clocks and generates a clock that is synchronized with the reference clock, and minimizes phase fluctuations when switching the reference clock without using a complicated circuit. An object of the present invention is to provide a clock synchronization circuit that can be used.
[0020]
[Means for Solving the Problems]
The clock synchronization circuit of the present invention selects one of the plurality of reference clocks in response to a selection signal from the outside in a clock synchronization circuit that selects one of a plurality of reference clocks and generates an output clock synchronized with the selected one. A selector, pulse generation means for receiving a reference clock selected by the selector and generating a ½ frequency-divided pulse with a duty ratio of 50%, ½ frequency-divided output of the output clock, and output of the pulse generation means And a means for generating the output clock by controlling a voltage controlled oscillator based on the phase difference between the first reference clock and the second reference clock when the selector selects another reference clock. The phase of the output pulse is changed by the phase difference from the previous reference clock.
[0021]
Specifically, in a clock synchronization circuit that selects one of a plurality of reference clocks and generates an output clock synchronized with the PLL by a PLL, a selector that selects one of the plurality of reference clocks in response to a selection signal from the outside A pulse generating means for receiving a reference clock selected by the selector and generating a ½ frequency-divided pulse with a duty ratio of 50%; and a pulse with a duty ratio of 50% by dividing the output clock by ½. A 1/2 divider to generate, an EX-OR type phase comparator that receives the output of the pulse generator and the output of the 1/2 divider, and outputs an exclusive OR, and this EX-OR A voltage-controlled oscillator that generates an output clock by controlling an oscillation frequency in accordance with an output of the type phase comparator, and the pulse generating means includes a selector that receives another reference clock. When selecting click, only the phase difference between the different reference clock and the previous reference clock changes the phase of the output pulse.
[0022]
Further, the pulse generating means may be constituted by a flip-flop that operates by receiving the output of the selector at one input terminal and receiving the output of the 1/2 frequency divider at the other input terminal.
[0023]
In the above configuration, the voltage-controlled oscillator has a control characteristic in which the oscillation frequency decreases with an increase in output duty of the EX-OR type phase comparator.
[0024]
Further, when the voltage controlled oscillator has a control characteristic in which the oscillation frequency increases with an increase in output duty of the EX-OR type phase comparator, the 1/2 frequency divider and the flip-flop An inverting circuit for inverting the signal polarity is provided between the other input terminal. Alternatively, the inverting circuit may be provided between the ½ frequency divider and the EX-OR type phase comparator.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described with reference to the drawings.
[0026]
FIG. 1 is a block diagram showing an embodiment of the present invention. A selector 1 for selecting one of a plurality of reference clocks REF1 and REF2 according to a selection signal (SEL), a flip-flop 6, and an EX- An OR type phase comparator 2, a low-pass filter 3, a voltage controlled oscillator (VCO) 4, and a ½ frequency divider 5 are included.
[0027]
Here, a PLL is formed by the EX-OR type phase comparator 2, the low pass filter 3, the voltage controlled oscillator (VCO) 4, and the 1/2 frequency divider 5, and is synchronized with the selected reference clock. The generated output clock CLK is generated.
[0028]
The 1/2 divider 5 divides the output clock CLK by 1/2 to generate a pulse P2 having a duty ratio of 50%, and outputs the pulse P2 to one input terminal of the EX-OR type phase comparator 2.
[0029]
The EX-OR type phase comparator 2 receives the output P1 of the flip-flop 6 and the output P2 of the 1/2 frequency divider 5 and outputs an exclusive OR (EX-OR) thereof.
[0030]
The voltage controlled oscillator (VCO) 4 receives the output of the EX-OR type phase comparator 2 as a control signal through the low-pass filter 3, and generates an output clock CLK synchronized with the selected reference clock.
[0031]
The voltage controlled oscillator (VCO) 4 has a control characteristic in which the oscillation frequency decreases with an increase in the output duty of the EX-OR type phase comparator 2, and this PLL is an EX-OR type phase comparator. The output P2 of the 1/2 frequency divider 5 input to 2 converges to a phase relationship of −90 ° with respect to the output P1 of the flip-flop 10.
[0032]
The difference from the conventional clock synchronization circuit is that the output of the selector 1 and the output P2 of the 1/2 frequency divider 5 are supplied to the two input terminals of the flip-flop 6, respectively. The output P2 of the 1/2 frequency divider 5 is supplied to the EX-OR type phase comparator 2 respectively.
[0033]
Here, let us consider a condition for minimizing the phase change of the two signals input to the EX-OR type phase comparator 2 when the reference clock is switched. This is to minimize the phase change of the output pulse P1 of the flip-flop 6 when the reference clock is switched.
[0034]
For example, as shown in FIG. 3, the reference clock REF1 (FIG. 3A) is switched to the reference clock REF2 (FIG. 3B).
[0035]
The output of the flip-flop 6 before switching is a pulse with a duty ratio of 50%, which is divided by 1/2 and changes according to the reference clock REF1, as indicated by the solid line in FIG. In addition, the broken line part has shown the case where switching has not occurred.
[0036]
When the reference clock is switched from REF1 to REF2, in order to minimize the phase change of the output of the flip-flop 6, the output waveform of the flip-flop 6 is divided by a half of the reference clock REF2 (FIG. 3 (h) It is clear that
[0037]
Further, when the phase difference between the reference clocks REF1 and REF2 is changed variously, the reference clock in which the output waveform of the flip-flop 6 after switching is closest to the output waveform of the flip-flop 6 before switching (FIG. 3 (g)). Considering the ½ frequency waveform of REF2, the region division as shown in FIG.
[0038]
That is, there is a rising edge of the ½ frequency-divided waveform of the reference clock REF2 in a region ± 90 ° (region A) with respect to the rising of the waveform of FIG. 3G, and the falling of the waveform of FIG. In contrast, the falling edge of the ½ frequency-divided waveform of the reference clock REF2 only needs to be in the ± 90 ° region (region B).
[0039]
In this way, if the output waveform of the flip-flop 6 after switching is made to be a 1/2 frequency-divided waveform of the reference clock REF2 (FIG. 3 (h)), the phase change can be minimized.
[0040]
By the way, before switching of the reference clock, the output of the flip-flop 6 (FIG. 3G) input to the EX-OR type phase comparator 2 and the output of the 1/2 frequency divider 5 (FIG. 3J) Have converged to a state having a phase difference of 90 ° from each other, and even if the reference clock is switched, it takes time for the response of the PLL, so the phase of the output of the 1/2 divider 5 is immediately It does not change. Regions A and B shown in FIG. 3 (i) correspond to the “H” level and “L” level of the output waveform of the ½ frequency divider 5 (FIG. 3 (j)), respectively.
[0041]
Therefore, the output of the selector 1 is input to one input terminal of the flip-flop 6, the output of the ½ divider (FIG. 3 (j)) is input to the other input terminal, and the selected reference clock is used. By sampling the output of the 1/2 divider 5 and performing a 1/2 dividing operation, the output waveform of the flip-flop 6 after switching is changed to the 1/2 divided waveform of the reference clock REF2 (FIG. 3 (h)). Can be.
[0042]
FIG. 2 is a timing chart showing the operation of the clock synchronization circuit of the present invention.
Here, the phase difference between the reference clock REF1 (FIG. 2 (a)) and the reference clock REF2 (FIG. 2 (b)) is 10 °, and the selector 1 receives a selection signal (SEL) from the outside (FIG. 2 (c)). In response, the reference clock REF1 is switched to REF2 at time t1.
[0043]
When the reference clock REF1 (FIG. 2 (a)) is selected, an output clock that is in phase with the reference clock REF1 is output from the VCO 4, and this output clock is divided by 1/2 by the 1/2 divider 5. Then, it is input to one end of the EX-OR type phase comparator 2 as an output pulse P2 having a duty ratio of 50% (FIG. 2 (f)).
[0044]
Further, the output P1 (FIG. 2 (e)) of the flip-flop 6 is input to the other end of the EX-OR type phase comparator 2. The output P1 of the flip-flop 6 is a 1/2 frequency-divided pulse with a duty ratio of 50% that is in phase with the reference clock REF1, and is a 1/2 frequency divider that is input to one end of the EX-OR type phase comparator 2. The PLL converges in a state having a phase difference of 90 ° with respect to the output P2 of 5.
[0045]
Here, the reference clock (FIG. 2 (d)) selected by the selector 1 is input to one input terminal of the flip-flop 6, and the output P2 (FIG. 2 (f)) of the 1/2 frequency divider 5 is flip-flopped. Is input to the other input terminal of the group 6, and the output P2 of the 1/2 frequency divider 5 is sampled by the selected reference clock to operate the flip-flop 6, and 1/2 at the rising edge of the selected reference clock. Based on the level of the output P2 of the frequency divider 5, a ½ frequency-divided output P1 (FIG. 2 (e)) with a duty ratio of 50% that changes to the “H” level or the “L” level is generated.
[0046]
Now, when switching from the reference clock REF1 to REF2 at time t1, the output P2 (FIG. 2 (f)) of the 1/2 frequency divider 5 at one input end of the flip-flop 6 does not change abruptly, but the other The reference clock at the input terminal changes from REF1 to REF2.
[0047]
That is, the output of the flip-flop 6 changes from the “L” level to the “H” level by the rising edge of the reference clock REF1 immediately before the time point t1, and then the reference clock REF2 is input within the phase range of 90 ° from the time point t1. Even so, the output of the flip-flop 6 maintains the “H” level.
[0048]
Then, it changes from the “H” level to the “L” level at the next reference clock REF2, and thereafter, the output level of the flip-flop 6 changes in accordance with the reference clock REF2, and the duty ratio 50 matches the phase of the reference clock REF2. % 1 / 2-divided output pulse P1 (FIG. 2 (e)) is generated.
[0049]
As a result, when the reference clock REF1 is switched to REF2, the output of the flip-flop 6 is a ½ frequency-divided output with a duty ratio of 50% that matches the phase of the reference clock REF2.
[0050]
Accordingly, the phase difference between the two signals input to the EX-OR type phase comparator 2 is 100 °, and the phase change can be minimized to 10 °. Therefore, an extremely large phase change (190 °) as in the prior art. The PLL pull-in time can be shortened with a simple circuit configuration, and the frequency fluctuation until the synchronization is established can be suppressed.
[0051]
FIG. 4 is a diagram showing another embodiment.
[0052]
In the clock synchronization circuit shown in FIG. 1, the voltage controlled oscillator (VCO) 4 has a control characteristic in which the frequency decreases with an increase in the output duty of the EX-OR type phase comparator 2. did.
[0053]
However, in the case of a control characteristic opposite to this, that is, the voltage controlled oscillator (VCO) 7 has a control characteristic in which the oscillation frequency increases with an increase in the output duty of the EX-OR type phase comparator 2. In this case, for example, as shown in FIG. 4, if an inverting circuit 8 for inverting the signal polarity is inserted between the 1/2 frequency divider 5 and the input terminal of the flip-flop 6, the one shown in FIG. It can be operated similarly.
[0054]
Alternatively, even if the inverting circuit 8 is provided between the ½ frequency divider 5 and the EX-OR type phase comparator 2, the same operation can be performed.
[0055]
In the above description, the number of reference clocks selected by the selector 1 is two, REF1 and REF2. However, the number is not limited, and n reference clocks REF1, REF2,. .., REFn can be provided with a selector 9 for selecting one of them, and a clock synchronized with the selected reference clock can be generated.
[0056]
【The invention's effect】
As described above, according to the present invention, in a clock synchronization circuit that selects one of a plurality of reference clocks and generates a clock synchronized with the PLL by using a PLL, the reference clock can be switched without using a complicated circuit. The phase change between the two signals input to the phase comparator can be suppressed to the phase difference between the reference clocks, the PLL pull-in time can be shortened, and the frequency fluctuation until the synchronization is established can also be suppressed.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of the present invention.
FIG. 2 is a timing chart showing the operation of the clock synchronization circuit of the present invention.
FIG. 3 is a diagram for explaining a phase change at the time of clock switching;
FIG. 4 is a diagram showing another embodiment of the present invention.
FIG. 5 is a diagram showing another embodiment of the present invention.
FIG. 6 is a diagram showing a conventional clock synchronization circuit.
FIG. 7 is a timing chart showing the operation of a conventional clock synchronization circuit.
[Explanation of symbols]
1, 9 Selector 2 EX-OR type phase comparator 3 Low pass filter 4, 7 Voltage controlled oscillator (VCO)
5 1/2 divider 6, 10 flip-flop 8 inversion circuit

Claims (6)

In a clock synchronization circuit that selects one of a plurality of reference clocks and generates an output clock synchronized with the selected clock, a selector that receives a selection signal from the outside and selects one of the plurality of reference clocks is selected by the selector. A voltage generator based on a phase difference between a half-divided output of the output clock and an output of the pulse generating means, receiving a reference clock and generating a ½ frequency-divided pulse with a duty ratio of 50% And a means for generating the output clock by controlling a type oscillator, and the pulse generating means, when the selector selects another reference clock, a phase difference between the other reference clock and the previous reference clock. A clock synchronization circuit characterized by changing the phase of the output pulse only. In a clock synchronization circuit that selects one of a plurality of reference clocks and generates an output clock synchronized with the PLL by a PLL, a selector that receives a selection signal from the outside and selects one of the plurality of reference clocks, and this selector Pulse generation means for receiving the selected reference clock and generating a ½ frequency divided pulse with a duty ratio of 50%, and ½ for generating a pulse with a duty ratio of 50% by dividing the output clock by ½. A frequency divider, an EX-OR type phase comparator that receives the output of the pulse generation means and the output of the 1/2 frequency divider and outputs an exclusive OR, and the EX-OR type phase comparator A voltage-controlled oscillator that generates an output clock by controlling an oscillation frequency according to an output, and the pulse generation unit selects another reference clock by the selector And time, the clock synchronization circuit, characterized in that varying the different reference clock and the phase difference by the output pulse phase with the previous reference clock. 3. The flip-flop that operates by receiving the output of the selector at one input terminal and the output of the 1/2 frequency divider at the other input terminal. Clock synchronization circuit. 3. The clock synchronization circuit according to claim 2, wherein the voltage-controlled oscillator has a control characteristic in which the oscillation frequency decreases with an increase in output duty of the EX-OR type phase comparator. The voltage controlled oscillator has a control characteristic in which the oscillation frequency increases in response to an increase in output duty of the EX-OR type phase comparator, and the other input terminal of the ½ divider and the flip-flop 4. The clock synchronization circuit according to claim 3, wherein an inverting circuit for inverting the signal polarity is provided between the first and second terminals. The voltage controlled oscillator has a control characteristic in which the oscillation frequency increases with an increase in output duty of the EX-OR type phase comparator, and the 1/2 frequency divider and the EX-OR type phase comparator 4. The clock synchronization circuit according to claim 3, wherein an inverting circuit for inverting the signal polarity is provided between the first and second terminals.

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