JP2009081557A - Phase lock loop circuit - Google Patents

Abstract

A phase locked loop circuit capable of controlling the frequency of an output clock signal with high accuracy is provided.
A capacitor (104) for holding a control voltage, a phase detector (101) for detecting a phase difference of a feedback signal with respect to a reference clock signal, and the capacitor in accordance with the detected phase difference. Alternatively, the first switch circuit (SW1, SW2) connected to the reference potential and an output clock signal having an oscillation frequency corresponding to the control voltage of the capacitor are generated, and the output clock signal or the signal corresponding to the output clock signal is generated. A voltage-controlled oscillator (105) that outputs the feedback signal to the phase detector, and the capacitance for a certain period from an edge of the reference clock signal or from an edge of the output clock signal or a signal corresponding to the output clock signal And a second switch circuit (SW3) connected to the reference potential or the power supply voltage. That the phase-locked loop circuit is provided.
[Selection] Figure 1

Description

  The present invention relates to a phase-locked loop circuit.

  FIG. 13 is a diagram illustrating a configuration example of a phase lock loop (PLL) circuit. The phase detector 101 inputs the reference clock signal RFCK to the reference input terminal RCK, inputs the output clock signal OCK to the feedback input terminal FB, outputs the control signal of the switch SW1 from the up output terminal UP, and outputs the down output terminal DOWN. Outputs a control signal for the switch SW2. A series connection circuit of the current source 102 and the switch SW1 is connected between the positive power supply voltage and the input terminal IN of the voltage controlled oscillator (VCO) 105. A series connection circuit of the switch SW2 and the current source 103 is connected between the input terminal IN of the VCO 105 and a reference potential (ground potential). The capacitor 104 is connected between the input terminal IN of the VCO 105 and a reference potential. The VCO 105 outputs an output clock signal OCK from the output terminal OUT.

  14A and 14B are timing charts showing an operation example of the PLL circuit of FIG. The switch SW1 is turned on when the up output terminal UP becomes high level, and turned off when the up output terminal UP becomes low level. The switch SW2 is turned on when the down output terminal DOWN becomes high level, and turned off when the down output terminal DOWN becomes low level.

  FIG. 14A shows a case where the output clock signal OCK is advanced by the phase difference φ1 with respect to the reference clock signal RFCK. The phase detector 101 outputs a high-level control signal from the down output terminal DOWN from the rising edge of the output clock signal OCK to the rising edge of the reference clock signal RFCK. When the control signal becomes high level, the switch SW2 is turned on, the capacitor 104 is connected to the reference potential, and the voltage Vcntl of the capacitor 104 decreases by the voltage V1. The VCO 105 controls the oscillation frequency of the output clock signal OCK to be lowered when the voltage Vcntl is lowered. As a result, the phase difference φ1 becomes small, eventually the phase difference φ1 becomes 0, and the output clock signal OCK has the same frequency as the reference clock signal RFCK.

  FIG. 14B shows a case where the output clock signal OCK is delayed by a phase difference φ1 with respect to the reference clock signal RFCK. The phase detector 101 outputs a high-level control signal from the up output terminal UP from the rising edge of the reference clock signal RFCK to the rising edge of the output clock signal OCK. When the control signal becomes high level, the switch SW1 is turned on, the capacitor 104 is connected to the power supply voltage, and the voltage Vcntl of the capacitor 104 increases by the voltage V1. The VCO 105 controls the oscillation frequency of the output clock signal OCK to increase as the voltage Vcntl increases. As a result, the phase difference φ1 becomes small, eventually the phase difference φ1 becomes 0, and the output clock signal OCK has the same frequency as the reference clock signal RFCK.

  FIG. 15 is a graph showing the relationship between the phase difference φ and the voltage fluctuation amount ΔVcntl of the PLL circuit of FIG. The phase difference φ is the phase difference of the output clock signal OCK with respect to the reference clock signal RFCK. The voltage fluctuation amount ΔVcntl is the fluctuation amount of the voltage Vcntl. As shown in FIGS. 14A and 14B, the smaller the phase difference φ, the smaller the pulse widths of the down output terminal DOWN and the up output terminal UP, and the voltage fluctuation amount ΔVcntl when the phase difference φ is small is obtained. I can't control it. This is because when there is a switching point between the switch SW1 and the switch SW2 when the phase difference φ is near 0, the waveform is crushed when the pulse width of the up output terminal UP or the down output terminal DOWN becomes below a certain level, and the phase difference φ This is because the linearity of the voltage fluctuation amount ΔVcntl is lost.

  FIG. 19 is a graph showing a more specific relationship between the phase difference φ and the voltage fluctuation amount ΔVcntl of the PLL circuit of FIG. When the phase difference φ is small between −φ1 and + φ1, the voltage fluctuation amount ΔVcntl becomes zero. Hereinafter, a description will be given with reference to FIGS. 16A to 16C, FIGS. 17A to 17C, and FIG.

  FIGS. 16A to 16C, FIGS. 17A to 17C, and FIG. 18 are timing charts showing an operation example of the PLL circuit of FIG.

  16A to 16C show a case where the phase of the output clock signal OCK is advanced with respect to the reference clock signal RFCK. In FIG. 16A, the output clock signal OCK has a large phase difference φ3 with respect to the reference clock signal RFCK, and the voltage fluctuation amount ΔVcntl becomes the voltage −V3. In FIG. 16B, the output clock signal OCK is advanced by the intermediate phase difference φ2 with respect to the reference clock signal RFCK, and the voltage fluctuation amount ΔVcntl becomes the voltage −V2. In FIG. 16C, the output clock signal OCK is advanced by a small phase difference φ1 with respect to the reference clock signal RFCK, and the voltage fluctuation amount ΔVcntl becomes zero. When the phase difference is −φ3 and −φ2, the pulse waveform of the down output terminal DOWN is not broken, and the linearity of the phase difference φ and the voltage fluctuation amount ΔVcntl is maintained. On the other hand, when the phase difference is −φ1, the pulse waveform of the down output terminal DOWN collapses and the voltage fluctuation amount ΔVcntl becomes zero.

  17A to 17C show a case where the phase of the output clock signal OCK is delayed with respect to the reference clock signal RFCK. In FIG. 17A, the output clock signal OCK is delayed by a large phase difference φ3 with respect to the reference clock signal RFCK, and the voltage fluctuation amount ΔVcntl becomes the voltage V3. In FIG. 17B, the output clock signal OCK is delayed by a medium phase difference φ2 with respect to the reference clock signal RFCK, and the voltage fluctuation amount ΔVcntl becomes the voltage V2. In FIG. 17C, the output clock signal OCK is delayed by a small phase difference φ1 with respect to the reference clock signal RFCK, and the voltage fluctuation amount ΔVcntl becomes zero. When the phase differences are φ3 and φ2, the pulse waveform of the up output terminal UP is not broken, and the linearity of the phase difference φ and the voltage fluctuation amount ΔVcntl is maintained. On the other hand, when the phase difference is φ1, the pulse waveform at the up output terminal UP collapses and the voltage fluctuation amount ΔVcntl becomes zero.

  FIG. 18 shows a case where the output clock signal OCK has no phase difference with respect to the reference clock signal RFCK. When the phase difference φ is 0, the voltage fluctuation amount ΔVcntl becomes 0.

  As described above, when the phase difference φ is small from −φ1 to + φ1, the voltage fluctuation amount ΔVcntl becomes 0, the linearity between the phase difference φ and the voltage fluctuation amount ΔVcntl is lost, and the output clock signal OCK Cannot be matched with the frequency of the reference clock signal RFCK with high accuracy.

  In Patent Document 1 below, a phase comparison unit that detects a phase difference between input signals and outputs a signal corresponding to the phase difference, and a signal output from the phase comparison unit are input and converted to a DC voltage. A low-pass filter that connects to the low-pass filter, generates a signal having a predetermined frequency controlled by the DC voltage, and outputs the signal, and the output signal of the voltage-controlled oscillator is divided. A delay control unit configured to generate a delay amount control signal based on a signal corresponding to a phase difference output from the phase comparison unit; The delay unit delays the output signal for a predetermined time by the control of the delay control unit and is connected to the phase comparison unit in a feedback manner. The delay control unit generates a delay amount control signal based on the phase difference signal input by the delay control unit. Describes a PLL circuit characterized in that the feedback signal is phase-synchronized with a reference signal by delay-connecting the output of the divider by a corresponding time and feedback-connecting to the phase comparator based on the delay amount control signal. ing.

  In Patent Document 2 below, a feedback signal obtained by dividing the output of the voltage controlled oscillator and a reference clock signal are phase-compared by a phase comparator, and the voltage control is performed by a control circuit according to the comparison result. In the PLL circuit for controlling an oscillator, a modulation circuit is provided which takes one of the feedback signal and the reference clock signal as an input signal, modulates the input signal in the time axis direction, and supplies the modulated signal to the phase comparator. A PLL circuit is described.

JP-A-6-276089 Japanese Patent Laid-Open No. 10-163860

  An object of the present invention is to provide a phase locked loop circuit capable of controlling the frequency of an output clock signal with high accuracy.

  The phase-locked loop circuit of the present invention includes a capacitor that holds a control voltage, a phase detector that detects a phase difference of a feedback signal with respect to a reference clock signal, and the capacitor according to the detected phase difference. A first switch circuit connected to a reference potential; and an output clock signal having an oscillation frequency corresponding to the control voltage of the capacitor, and the output clock signal or a signal corresponding to the output clock signal as the feedback signal A voltage-controlled oscillator that outputs to the detector, and connects the capacitor to the reference potential or the power supply voltage for a certain period from the edge of the reference clock signal or for a certain period from the edge of the output clock signal or a signal corresponding to the output clock signal And a second switch circuit.

  Since the boundary point connecting the capacitor to the power supply voltage or the reference potential can be moved away from the zero point of the phase difference, the frequency of the output clock signal can be controlled with high accuracy even when the phase difference is near zero.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of a phase-locked loop (PLL) circuit according to the first embodiment of the present invention. The phase detector 101 inputs the reference clock signal RFCK to the reference input terminal RCK, inputs the feedback signal OCK_2 to the feedback input terminal FB, outputs the control signal of the switch SW1 from the up output terminal UP, and from the down output terminal DOWN. A control signal for the switch SW2 is output. A series connection circuit of the current source 102 and the switch SW1 is connected between the positive power supply voltage and the input terminal IN of the voltage controlled oscillator (VCO) 105. A series connection circuit of the switch SW2 and the current source 103 is connected between the input terminal IN of the VCO 105 and a reference potential (ground potential). The capacitor 104 is connected between the input terminal IN of the VCO 105 and a reference potential. The VCO 105 outputs an output clock signal OCK from the output terminal OUT.

  The delay circuit 111 delays the output clock signal OCK by a delay time t and outputs a feedback signal OCK_2. The feedback signal OCK_2 is input to the feedback input terminal FB of the phase detector 101. The delay circuit 112 delays the reference clock signal RFCK by a delay time t and outputs a signal. A logical product (AND) circuit 113 outputs a logical product signal DOWN_2 of the logical inversion signal of the output signal of the delay circuit 112 and the reference clock signal RFCK. A series connection circuit of the switch SW3 and the current source 114 is connected between the input terminal IN of the VCO 105 and the reference potential. The switch SW3 is turned on or off according to the signal DOWN_2.

  2A and 2B are timing charts showing an operation example of the PLL circuit of FIG. The switch SW1 is turned on when the up output terminal UP becomes high level, and turned off when the up output terminal UP becomes low level. The switch SW2 is turned on when the down output terminal DOWN becomes high level, and turned off when the down output terminal DOWN becomes low level. The switch SW3 is turned on when the signal DOWN_2 becomes high level, and turned off when the signal DOWN_2 becomes low level.

  FIG. 2A shows a case where the output clock signal OCK is advanced by the phase difference φ1 with respect to the reference clock signal RFCK. The delay circuit 111 delays the output clock signal OCK by a delay time t and outputs a feedback signal OCK_2. The phase detector 101 outputs a high-level control signal from the up output terminal UP from the rising edge of the reference clock signal RFCK to the rising edge of the feedback signal OCK_2. The AND circuit 113 outputs a signal DOWN_2 that becomes a high level during the delay time t from the rising edge of the reference clock signal RFCK. While the up output terminal UP is at the high level, the switch SW1 is turned on and the capacitor 104 is connected to the power supply voltage. Further, while the signal DOWN_2 is at a high level, the switch SW3 is turned on and the capacitor 104 is connected to the reference potential. As a result, the voltage Vcntl of the capacitor 104 decreases by the voltage V1 during the period when the signal DOWN_2 is at the high level and the up output terminal UP is at the low level. The VCO 105 controls the oscillation frequency of the output clock signal OCK to be lowered when the voltage Vcntl is lowered. As a result, the phase difference φ1 becomes small, eventually the phase difference φ1 becomes 0, and the output clock signal OCK has the same frequency as the reference clock signal RFCK.

  FIG. 2B shows a case where the output clock signal OCK is delayed by a phase difference φ1 with respect to the reference clock signal RFCK. The delay circuit 111 delays the output clock signal OCK by a delay time t and outputs a feedback signal OCK_2. The phase detector 101 outputs a high-level control signal from the up output terminal UP from the rising edge of the reference clock signal RFCK to the rising edge of the feedback signal OCK_2. The AND circuit 113 outputs a signal DOWN_2 that becomes a high level during the delay time t from the rising edge of the reference clock signal RFCK. While the up output terminal UP is at the high level, the switch SW1 is turned on and the capacitor 104 is connected to the power supply voltage. Further, while the signal DOWN_2 is at a high level, the switch SW3 is turned on and the capacitor 104 is connected to the reference potential. As a result, the voltage Vcntl of the capacitor 104 increases by the voltage V1 during the period when the output terminal UP is at the high level and the signal DOWN_2 is at the low level. The VCO 105 controls the oscillation frequency of the output clock signal OCK to increase as the voltage Vcntl increases. As a result, the phase difference φ1 becomes small, eventually the phase difference φ1 becomes 0, and the output clock signal OCK has the same frequency as the reference clock signal RFCK.

  FIG. 3 is a graph showing the relationship between the phase difference φ and the voltage fluctuation amount ΔVcntl of the PLL circuit of FIG. The phase difference φ is the phase difference of the output clock signal OCK with respect to the reference clock signal RFCK. The voltage fluctuation amount ΔVcntl is the fluctuation amount of the voltage Vcntl. As shown in FIGS. 2A and 2B, as the advance amount of the phase difference φ increases, the pulse width of the up output terminal UP decreases, and the voltage fluctuation amount ΔVcntl in a predetermined section where the phase difference φ is smaller than −φ1. Can not control. That is, since the operation switching time of the switches SW1 and SW2 is away from the zero point of the phase difference φ and is located at a time point smaller than −φ1, the voltage fluctuation amount ΔVcntl can be controlled even with a phase difference having a small absolute value. , Skew and Jitter are improved. According to the present embodiment, when the phase difference φ is larger than −φ1, the linearity between the phase difference φ and the voltage fluctuation amount ΔVcntl can be maintained, so that the frequency of the output clock signal OCK is set to the frequency of the reference clock signal RFCK. Can be matched with high accuracy.

  FIG. 7 is a graph showing a more specific relationship between the phase difference φ and the voltage fluctuation amount ΔVcntl of the PLL circuit of FIG. While the phase difference φ is in the vicinity of −φ2, the voltage fluctuation amount ΔVcntl becomes 0, and when the phase difference φ is larger than −φ2, the linearity between the phase difference φ and the voltage fluctuation amount ΔVcntl can be maintained. Hereinafter, a description will be given with reference to FIGS. 4A to 4C, FIGS. 5A to 5C, and FIG.

  FIGS. 4A to 4C, FIGS. 5A to 5C, and FIG. 6 are timing charts showing an operation example of the PLL circuit of FIG.

  4A to 4C show a case where the phase of the output clock signal OCK is advanced with respect to the reference clock signal RFCK. In FIG. 4A, the output clock signal OCK is advanced by a large phase difference φ3 with respect to the reference clock signal RFCK, and the voltage fluctuation amount ΔVcntl becomes the voltage −V3. In FIG. 4B, the output clock signal OCK is advanced by the intermediate phase difference φ2 with respect to the reference clock signal RFCK, the pulse waveform of the up output terminal UP collapses, and the voltage fluctuation amount ΔVcntl becomes the voltage −V2. In FIG. 4C, the output clock signal OCK is advanced by a small phase difference φ1 with respect to the reference clock signal RFCK, and the voltage fluctuation amount ΔVcntl becomes the voltage −V1. When the phase difference is −φ3 and −φ1, the pulse waveform of the down output terminal DOWN and the pulse waveform of the up output terminal UP are not broken, and the linearity of the phase difference φ and the voltage fluctuation amount ΔVcntl is maintained. On the other hand, when the phase difference is −φ2, the pulse waveform of the up output terminal UP collapses, and the linearity between the phase difference φ and the voltage fluctuation amount ΔVcntl is not maintained.

  5A to 5C show a case where the phase of the output clock signal OCK is delayed with respect to the reference clock signal RFCK. In FIG. 5A, the output clock signal OCK is delayed by a large phase difference φ3 with respect to the reference clock signal RFCK, and the voltage fluctuation amount ΔVcntl becomes the voltage V3. In FIG. 5B, the output clock signal OCK is delayed by a medium phase difference φ2 with respect to the reference clock signal RFCK, and the voltage fluctuation amount ΔVcntl becomes the voltage V2. In FIG. 5C, the output clock signal OCK is delayed by a small phase difference φ1 with respect to the reference clock signal RFCK, and the voltage fluctuation amount ΔVcntl becomes the voltage V1. When the phase differences are φ3, φ2, and φ1, the pulse waveform of the up output terminal UP is not collapsed, and the linearity of the phase difference φ and the voltage fluctuation amount ΔVcntl is maintained.

  FIG. 6 shows a case where the output clock signal OCK has no phase difference with respect to the reference clock signal RFCK. When the phase difference φ is 0, the pulse of the up output terminal UP and the high level period of the signal DOWN_2 are the same, and the voltage fluctuation amount ΔVcntl becomes 0.

  As described above, when the phase difference φ is larger than −φ2, the pulse waveform of the up output terminal UP is not collapsed, and the linearity between the phase difference φ and the voltage fluctuation amount ΔVcntl is maintained. In particular, the linearity between the phase difference φ and the voltage fluctuation amount ΔVcntl is maintained even when the phase difference φ is near zero. As a result, the frequency of the output clock signal OCK can be matched with the frequency of the reference clock signal RFCK with high accuracy.

(Second Embodiment)
FIG. 8 is a diagram illustrating a configuration example of a PLL circuit according to the second embodiment of the present invention. The phase detector 101 inputs the reference clock signal RFCK to the reference input terminal RCK, inputs the feedback signal OCK_2 to the feedback input terminal FB, outputs the control signal of the switch SW1 from the up output terminal UP, and from the down output terminal DOWN. A control signal for the switch SW2 is output. A series connection circuit of the current source 102 and the switch SW1 is connected between the positive power supply voltage and the input terminal IN of the voltage controlled oscillator (VCO) 105. A series connection circuit of the switch SW2 and the current source 103 is connected between the input terminal IN of the VCO 105 and a reference potential (ground potential). The capacitor 104 is connected between the input terminal IN of the VCO 105 and a reference potential. The VCO 105 outputs a clock signal OCK_2 from the output terminal OUT. The clock signal OCK_2 is input to the feedback input terminal FB of the phase detector 101 as a feedback signal. The delay circuit 811 delays the clock signal OCK_2 by a delay time t and outputs an output clock signal OCK.

  The delay circuit 812 delays the clock signal OCK_2 by a delay time t and outputs a signal. A logical product (AND) circuit 813 outputs a logical inversion signal of the output signal of the delay circuit 812 and a logical product signal UP_2 of the clock signal OCK_2. A series connection circuit of the switch SW3 and the current source 814 is connected between the positive power supply voltage and the input terminal IN of the VCO 105. The switch SW3 is turned on or off according to the signal UP_2.

  9A and 9B are timing charts showing an operation example of the PLL circuit of FIG. The switch SW1 is turned on when the up output terminal UP becomes high level, and turned off when the up output terminal UP becomes low level. The switch SW2 is turned on when the down output terminal DOWN becomes high level, and turned off when the down output terminal DOWN becomes low level. The switch SW3 is turned on when the signal UP_2 becomes high level and turned off when the signal UP_2 becomes low level.

  FIG. 9A shows a case where the output clock signal OCK is advanced by a phase difference φ3 with respect to the reference clock signal RFCK. The delay circuit 811 delays the clock signal OCK_2 by a delay time t and outputs an output clock signal OCK. The phase detector 101 outputs a high level control signal from the down output terminal DOWN during the period from the rising edge of the clock signal OCK_2 to the rising edge of the reference clock signal RFCK. The AND circuit 813 outputs a signal UP_2 that becomes a high level during the delay time t from the rising edge of the clock signal OCK_2. While the down output terminal DOWN is at the high level, the switch SW2 is turned on and the capacitor 104 is connected to the reference potential. Further, while the signal UP_2 is at the high level, the switch SW3 is turned on, and the capacitor 104 is connected to the power supply voltage. As a result, the voltage Vcntl of the capacitor 104 decreases in a period in which the down output terminal DOWN is at a high level and the signal UP_2 is at a low level. The VCO 105 controls the oscillation frequency of the clock signal OCK_2 to be lowered when the voltage Vcntl is lowered. As a result, the phase difference φ3 becomes smaller, eventually the phase difference φ3 becomes 0, and the output clock signal OCK has the same frequency as the reference clock signal RFCK.

  FIG. 9B shows a case where the output clock signal OCK is delayed by a phase difference φ3 with respect to the reference clock signal RFCK. The delay circuit 811 delays the clock signal OCK_2 by a delay time t and outputs an output clock signal OCK. The phase detector 101 outputs a high-level control signal from the up output terminal UP from the rising edge of the reference clock signal RFCK to the rising edge of the clock signal OCK_2. The AND circuit 813 outputs a signal UP_2 that becomes a high level during the delay time t from the rising edge of the clock signal OCK_2. While the up output terminal UP is at the high level, the switch SW1 is turned on and the capacitor 104 is connected to the power supply voltage. Further, while the signal UP_2 is at the high level, the switch SW3 is turned on, and the capacitor 104 is connected to the power supply voltage. As a result, the voltage Vcntl of the capacitor 104 rises in both periods when the up output terminal UP is at the high level and the signal UP_2 is at the high level. The VCO 105 controls the oscillation frequency of the clock signal OCK_2 to increase as the voltage Vcntl increases. As a result, the phase difference φ3 becomes smaller, eventually the phase difference φ3 becomes 0, and the output clock signal OCK has the same frequency as the reference clock signal RFCK.

  FIG. 10 is a graph showing the relationship between the phase difference φ and the voltage fluctuation amount ΔVcntl of the PLL circuit of FIG. As shown in FIGS. 9A and 9B, the pulse waveform of the up output terminal UP or the down output terminal DOWN collapses near φ2 where the phase difference φ is smaller than φ3, and the linearity of the phase difference φ and the voltage fluctuation amount ΔVcntl. Collapses. When the phase difference φ is smaller than φ2, the pulse waveform at the down output terminal DOWN does not collapse, and the linearity of the phase difference φ and the voltage fluctuation amount ΔVcntl is maintained. As a result, the voltage fluctuation amount ΔVcntl can be controlled even when the phase difference φ is near 0, and the skew and jitter are improved. According to the present embodiment, when the phase difference φ is smaller than φ2, the linearity between the phase difference φ and the voltage fluctuation amount ΔVcntl can be maintained, so that the frequency of the output clock signal OCK is set to the frequency of the reference clock signal RFCK. Can be matched with high accuracy.

(Third embodiment)
FIG. 11 is a diagram illustrating a configuration example of a PLL circuit according to the third embodiment of the present invention. In this embodiment (FIG. 11), a frequency divider 1101 is added to the first embodiment (FIG. 1). Hereinafter, the points of the present embodiment different from the first embodiment will be described. The frequency divider 1101 is connected between the output terminal OUT of the VCO 105 and the input terminal of the delay circuit 111, divides the output clock signal OCK by n, and outputs it to the delay circuit 111. As a result, the output clock signal OCK is output at a frequency n times higher than the reference clock signal RFCK.

(Fourth embodiment)
FIG. 12 is a diagram showing a configuration example of a PLL circuit according to the fourth embodiment of the present invention. In the present embodiment (FIG. 12), a frequency divider 1201 is added to the second embodiment (FIG. 8). Hereinafter, the points of the present embodiment different from the second embodiment will be described. The frequency divider 1201 is connected between the output terminal OUT of the VCO 105 and the feedback input terminal FB of the phase detector 101, and divides the signal of the output terminal OUT of the VCO 105 by n to output a clock signal OCK_2. The clock signal OCK_2 is input to the feedback input terminal FB of the phase detector 101, the input terminal of the delay circuit 812, and the input terminal of the AND circuit 813. As a result, the output clock signal OCK is output at a frequency n times higher than the reference clock signal RFCK.

  As described above, the PLL circuits of the first to fourth embodiments detect the phase difference between the capacitor 104 that holds the control voltage Vcntl and the feedback signal (signal of the feedback input terminal FB) with respect to the reference clock signal RFCK. According to the detector 101, the first switch circuits SW1 and SW2 that connect the capacitor 104 to a power supply voltage or a reference potential according to the detected phase difference, and the oscillation frequency according to the control voltage Vcntl of the capacitor 104 A voltage-controlled oscillator 105 that generates an output clock signal (a signal at the output terminal OUT) and outputs the output clock signal or a signal corresponding to the output clock signal to the phase detector 101 as the feedback signal; and the reference clock signal A certain period from the edge of RFCK (eg rising edge) (eg Delay time t) or the output clock signal or an edge of the signal corresponding to the output clock signal (for example, rising edge) for a certain period (for example, delay time t) to connect the capacitor 104 to the reference potential or the power supply voltage. 2 switch circuit SW3.

  The first embodiment (FIG. 1) further includes a delay circuit 111 that outputs a signal OCK_2 obtained by delaying the output clock signal OCK to the phase detector 101 as the feedback signal. The first switch circuits SW1 and SW2 connect the capacitor 104 to the power supply voltage when the feedback signal OCK_2 is delayed with respect to the reference clock signal RFCK, and the feedback signal OCK_2 becomes the reference clock signal RFCK. On the other hand, the capacitor 104 is connected to the reference potential when proceeding. The voltage-controlled oscillator 105 increases the oscillation frequency when the control voltage Vcntl of the capacitor 104 increases, and decreases the oscillation frequency when the control voltage Vcntl of the capacitor 104 decreases. The second switch circuit SW3 connects the capacitor 104 to the reference potential for a fixed time (for example, delay time t) from the edge (for example, rising edge) of the reference clock signal RFCK.

  The third embodiment (FIG. 11) further includes a frequency divider 1101 that divides the output clock signal OCK. The phase detector 101 inputs the output signal of the voltage controlled oscillator 105 through the frequency divider 1101 and the delay circuit 111 as the feedback signal.

  In the second embodiment (FIG. 8), the phase detector 101 receives the output clock signal OCK_2 as the feedback signal. The first switch circuits SW1 and SW2 connect the capacitor 104 to the power supply voltage when the feedback signal OCK_2 is delayed with respect to the reference clock signal RFCK, and the feedback signal OCK_2 is connected to the reference clock signal RFCK. On the other hand, the capacitor 104 is connected to the reference potential when proceeding. The voltage-controlled oscillator 105 increases the oscillation frequency when the control voltage Vcntl of the capacitor 104 increases, and decreases the oscillation frequency when the control voltage Vcntl of the capacitor 104 decreases. The second switch circuit SW3 connects the capacitor 104 to the power supply voltage for a predetermined time (for example, delay time t) from the edge (for example, rising edge) of the output clock signal OCK_2.

  The fourth embodiment (FIG. 12) further includes a frequency divider 1201 that divides the output clock signal. The phase detector 101 inputs the output signal of the voltage controlled oscillator 105 through the frequency divider 1201 as the feedback signal. The second switch circuit SW3 connects the capacitor 104 to the power supply voltage for a predetermined time (eg, delay time t) from the edge (eg, rising edge) of the output clock signal divided by the frequency divider 1201.

  According to the first to fourth embodiments, since the boundary point connecting the capacitor 104 to the power supply voltage or the reference potential can be moved away from the zero point of the phase difference φ, the output clock signal can be output even when the phase difference φ is near zero. Can be controlled with high accuracy.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

It is a figure which shows the structural example of the phase lock loop (PLL) circuit by the 1st Embodiment of this invention. 2A and 2B are timing charts showing an operation example of the PLL circuit of FIG. 2 is a graph showing a relationship between a phase difference φ and a voltage fluctuation amount ΔVcntl of the PLL circuit of FIG. 1. 4A to 4C are timing charts when the phase of the output clock signal OCK is advanced with respect to the reference clock signal RFCK. 5A to 5C are timing charts when the phase of the output clock signal OCK is delayed with respect to the reference clock signal RFCK. 6 is a timing chart when the output clock signal OCK has no phase difference with respect to the reference clock signal RFCK. 2 is a graph showing a more specific relationship between a phase difference φ and a voltage fluctuation amount ΔVcntl of the PLL circuit of FIG. 1. It is a figure which shows the structural example of the PLL circuit by the 2nd Embodiment of this invention. 9A and 9B are timing charts showing an operation example of the PLL circuit of FIG. 9 is a graph showing the relationship between the phase difference φ and the voltage fluctuation amount ΔVcntl of the PLL circuit of FIG. 8. It is a figure which shows the structural example of the PLL circuit by the 3rd Embodiment of this invention. It is a figure which shows the structural example of the PLL circuit by the 4th Embodiment of this invention. It is a figure which shows the structural example of a PLL circuit. 14A and 14B are timing charts showing an operation example of the PLL circuit of FIG. 14 is a graph showing the relationship between the phase difference φ and the voltage fluctuation amount ΔVcntl of the PLL circuit of FIG. 13. 16A to 16C are timing charts when the phase of the output clock signal OCK is advanced with respect to the reference clock signal RFCK. 17A to 17C are timing charts when the phase of the output clock signal OCK is delayed with respect to the reference clock signal RFCK. 6 is a timing chart when the output clock signal OCK has no phase difference with respect to the reference clock signal RFCK. 14 is a graph showing a more specific relationship between the phase difference φ and the voltage fluctuation amount ΔVcntl of the PLL circuit of FIG. 13.

Explanation of symbols

101 Phase detectors 102 and 103 Current source 104 Capacity 105 VCO
111, 112 delay circuit 113 AND circuit 114 current source

Claims (5)

A capacity for holding the control voltage;
A phase detector that detects the phase difference of the feedback signal with respect to the reference clock signal;
A first switch circuit for connecting the capacitor to a power supply voltage or a reference potential according to the detected phase difference;
A voltage controlled oscillator that generates an output clock signal having an oscillation frequency corresponding to the control voltage of the capacitor, and outputs the output clock signal or a signal corresponding to the output clock signal to the phase detector as the feedback signal;
A second switch circuit that connects the capacitor to the reference potential or the power supply voltage for a certain period from the edge of the reference clock signal or for a certain period from the edge of the output clock signal or the signal corresponding to the output clock signal. A phase-locked loop circuit. And a delay circuit that outputs a signal obtained by delaying the output clock signal to the phase detector as the feedback signal,
The first switch circuit connects the capacitor to the power supply voltage when the feedback signal is delayed with respect to the reference clock signal, and the capacitor when the feedback signal is advanced with respect to the reference clock signal. To the reference potential,
The voltage-controlled oscillator increases the oscillation frequency when the control voltage of the capacitor increases, and decreases the oscillation frequency when the control voltage of the capacitor decreases.
2. The phase-locked loop circuit according to claim 1, wherein the second switch circuit connects the capacitor to the reference potential for a predetermined time from an edge of the reference clock signal. And a frequency divider for dividing the output clock signal,
3. The phase locked loop circuit according to claim 2, wherein the phase detector inputs an output signal of the voltage controlled oscillator as the feedback signal via the frequency divider and the delay circuit. The phase detector inputs the output clock signal as the feedback signal,
The first switch circuit connects the capacitor to the power supply voltage when the feedback signal is delayed with respect to the reference clock signal, and the capacitor when the feedback signal is advanced with respect to the reference clock signal. To the reference potential,
The voltage-controlled oscillator increases the oscillation frequency when the control voltage of the capacitor increases, and decreases the oscillation frequency when the control voltage of the capacitor decreases.
2. The phase-locked loop circuit according to claim 1, wherein the second switch circuit connects the capacitor to the power supply voltage for a predetermined time from an edge of the output clock signal. And a frequency divider for dividing the output clock signal,
The phase detector inputs the output signal of the voltage controlled oscillator as the feedback signal through the frequency divider,
5. The phase-locked loop circuit according to claim 4, wherein the second switch circuit connects the capacitor to the power supply voltage for a predetermined time from an edge of the output clock signal divided by the frequency divider.

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