JP3967487B2 - IC card - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an IC card, and more particularly to an internal power supply voltage drop detection circuit, a power booster circuit, and a random number generation circuit. For example, a contactless card or a contact-type card that receives electric power and transmits / receives data using radio waves. It is used for IC cards.
[0002]
[Prior art]
FIG. 7A shows an example of the entire configuration of a non-contact type tag identification (Radio Frequency Identification; RFID) system that transmits and receives data using radio waves.
[0003]
This RFID system includes a host composed of a personal computer, a controller, an antenna, and the like, and a non-contact type tag called a transponder or a data carrier.
[0004]
Non-contact tag, as shown in FIG. 7 (b), (c) , incorporated an antenna coil which also serves as the power receiving, the data reception / transmission, a monolithic RFID chip memory and ASIC is one chip This is a simple configuration and will be referred to as a wireless card hereinafter.
[0005]
According to the RFID system as described above, commands and data are transmitted on a radio wave carrier signal as necessary from the host side, and necessary power is generated by the carrier wave signal on the wireless card side, and data writing and Since information is returned to the host side for reading and transmission, no battery is required.
[0006]
Therefore, the host side can use the RFID system for management such as entry / exit of a person by reading the contents stored in the memory of the wireless card in a non-contact manner using radio waves and rewriting the contents of the memory.
[0007]
For example, if you have a wireless card for a commuter pass in a pocket of clothes, you can run it with a wireless card attached to a car, and you will not have to stop to settle at the tollgate on the highway, Applications such as monitoring and managing parking lot entry / exit without intervention can be considered. It can also be used to manage the behavior of livestock and migratory fish.
[0008]
FIG. 8 specifically shows a conventional example of the wireless card in FIG.
[0009]
That is, the antenna coil is, LC circuit for generating an RF signal to detect a radio wave (e.g. ASK signal which is amplitude-modulated by the data signal) input from the outside (L is inductance, C is capacitance) acts as a.
[0010]
The chip includes an internal power supply generating circuit 82 for generating from said antenna coil is rectified and smoothed and constant voltage the RF signal input to the RF signal input terminal 81 an internal power supply of the wireless card (DC voltage), the internal power supply A power-on circuit 83 that detects the rise of the power supply voltage generated by the generation circuit and outputs a power-on signal, and a clock that shapes the RF signal input and divides the frequency as necessary to generate a system clock signal A generation circuit 84, a data demodulation circuit 85 that restores a command signal and a data signal by filtering the RF signal input, a transmission pulse generation circuit 86, a semiconductor memory unit 87, and a control circuit 88 are provided.
[0011]
The control circuit 88 has a CPU (central processing unit) (or control logic circuit), and receives the internal power supply and the system clock signal.
[0012]
The transmission pulse generation circuit 86 is connected to, for example, an NMOS transistor connected between the RF signal input terminal 81 and the ground potential terminal, and transmission data is given to the gate from the transmission data output port of the CPU 88. .
[0013]
The semiconductor memory unit 87 includes a ROM (read only memory) 87a for storing programs and fixed data, a RAM (random access memory) 87b for temporarily storing data, and a nonvolatile memory capable of storing data for a long period of time. And a memory address selection circuit 87d.
[0014]
As the non-volatile memory, for example, an EEPROM (electrically erasable / rewritable memory) or FRAM (ferroelectric memory) is used. In this example, a boosted voltage is used for data rewriting (erasing and writing). The necessary EEPROM 87c is used. Correspondingly, a power boosting circuit 89 for receiving the internal power and generating the boosted voltage is provided.
[0015]
By the way, as described above, when a wireless card is used, energy is supplied to the host (read / write side) that transmits radio waves and data is transmitted and received, and data is transferred to the EEPROM 87c as necessary. Write.
[0016]
At this time, if the wireless card is close to the host, the supplied electric field is strong, and there is no fear that the power source energy will be insufficient in the middle of data writing to the EEPROM 87c, but the wireless card moves away from the host. As a result, the supplied electric field becomes weak, and there is a problem that the power supply energy becomes insufficient during the data writing, and the writing operation must be stopped.
[0017]
As an example of this measure, conventionally, a function for confirming whether or not the power supply voltage of the wireless card is reduced by performing a pseudo write operation without actually storing data in the EEPROM 87c is used as a normal write operation. There is a method for maintaining the stable operation of the wireless card by adding it before.
[0018]
However, such a method has a problem that it takes extra time to write data to the wireless card.
[0019]
As another example of the countermeasure, there is a method of detecting the power supply voltage generated by the internal power supply generation circuit 82 and stopping the data writing operation to the EEPROM 87c when the power supply voltage drops below a certain level.
[0020]
However, such a method has a problem that the response operation for the power supply voltage drop tends to be delayed due to the response delay of the internal power supply generation circuit 82.
[0021]
On the other hand, the boosting characteristic of the power boosting circuit 89 for supplying the pulsed boosted voltage to the EEPROM 87c is important, for example, as shown in FIG. 9, the rising and falling slopes are relatively gentle. is there. This is because if the rise of the pulsed boosted voltage is steep, an impact of energy is applied to the memory cell of the EEPROM 87c, the memory cell is damaged, and the number of times of rewriting of the EEPROM 87c is greatly reduced (for example, 10 ⁵ order). To 10 ⁴ orders).
[0022]
Therefore, conventionally, as shown in the boosting characteristic shown in FIG. 9, the rising and falling slopes of the pulsed boosted voltage are set to be relatively gentle. There was a problem that it took extra time for data processing.
[0023]
Such a problem similarly occurs when the boosting characteristic of the power boosting circuit for supplying the boosting voltage to the EEPROM built in the contact type IC card is as shown in FIG.
[0024]
On the other hand, for example, when generating a random number signal to control the generation timing of identification number data, conventionally, since the random number signal is generated by software processing using the CPU 88, the random number is not always irregular. It is not generated. That is, if the initial values at the start of random number generation are matched, the same random number is generated.
[0025]
In general, a random number signal is known for various uses in an IC card. For example, when a random number signal is generated on a contact type IC card using a CPU to control writing of encryption key data, for example. Also, there are problems as described above.
[0026]
[Problems to be solved by the invention]
As described above, when the wireless card moves away from the host, the electric field supplied is weakened, the power supply energy is insufficient during the data writing, and the conventional measures for preventing the problem that the writing operation has to be stopped are There has been a problem that it takes extra processing time for data writing to the wireless card, or that the response operation for the power supply voltage drop tends to be delayed due to the response delay of the internal power generation circuit.
[0029]
The present invention has been made to solve the above-mentioned problems, and is a non-contact method capable of guaranteeing a stable data writing operation with respect to the built-in EEPROM even when the power source energy is insufficient in the middle of data writing as it is away from the host. An object is to provide a type of IC card.
[0032]
[Means for Solving the Problems]
An IC card according to the present invention is a non-contact type IC card that includes an antenna coil that also receives power and transmits and receives data, and an integrated circuit chip on which a semiconductor memory and a control circuit are formed. An internal power generation circuit that generates an internal power supply voltage from a high-frequency signal input from the antenna coil; a data demodulation circuit that restores a received data signal from the high-frequency signal input from the antenna coil; and a high-frequency signal input from the antenna coil A clock generation circuit for generating a system clock signal based on the above, an electrically erasable / rewritable memory, a power boosting circuit for receiving the internal power supply voltage and generating a boosted voltage for supplying to the memory, An internal power supply that detects when the internal power supply voltage drops below a certain value and outputs a detection flag signal A drop detection circuit, which operates in response to the internal power supply voltage and is controlled so that data can be rewritten to the memory during a period in which the detection flag signal is not received, and when the detection flag signal is received, the memory The internal power supply voltage drop detection circuit is provided in a signal path between the terminal to which the high frequency signal is input and the internal power supply generation circuit. The inserted resistance, a band gap reference power supply that receives the internal power supply voltage to generate a bandgap reference voltage, and a voltage drop generated in the resistor is compared with the bandgap reference voltage. And a voltage comparison circuit for detecting when the voltage drops below the voltage and outputting the detection flag signal .
[0039]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0040]
FIG. 1 is a circuit diagram showing an example of an IC chip of a wireless card according to the first embodiment of the present invention.
[0041]
The wireless card shown in FIG. 1 is used as a non-contact type tag of the RFID system described above with reference to FIG. 7, and compared with the wireless card of the conventional example described above with reference to FIG. The point that the internal power supply voltage drop detection circuit 11 is added, (2) the configuration and boost characteristics of the boost clock generation circuit 13 for supplying a clock signal to the power supply boost circuit 12, and (3) the configuration of the random number signal generation circuit 14 Are different, and the others are almost the same.
[0042]
In other words, the wireless card shown in FIG. 1 is a monolithic RFID chip contact and power reception memory and the ASIC is one chip, input from the antenna coil (outside also serving as a data reception / transmission for example detection of a radio wave of 13.57MHz (Acting as an LC circuit for generating an RF signal).
[0043]
The monolithic RFID chip includes an internal power supply generating circuit 82 for generating from said antenna coil is rectified and smoothed and constant voltage the RF signal input to the RF signal input terminal 81 an internal power supply of the wireless card (DC voltage), the A power-on circuit 83 that detects the rise of the power supply voltage generated by the internal power supply generation circuit and outputs a power-on signal, and shapes the RF signal input, divides it as necessary, and divides the system clock signal (this A clock generation circuit 84 for generating 13.57 MHz in the example, a data demodulation circuit 85 for restoring the command signal and the data signal by filtering the RF signal input, a transmission pulse generation circuit 86, a semiconductor memory unit 87, A random number signal generation circuit 14 and a control circuit 15 are provided.
[0044]
The control circuit 15 has a CPU or a control logic circuit, and receives the internal power supply and the system clock signal.
[0045]
The transmission pulse generation circuit 86 is connected to, for example, an NMOS transistor connected between the RF signal input terminal 81 and the ground potential terminal, and transmission data is transmitted from the transmission data output port of the control circuit 15 to the gate. Given.
[0046]
The semiconductor memory unit 87 includes a ROM (read only memory) 87a storing a program and fixed data, a RAM (random access memory) 87b for temporarily storing data, and a non-volatile memory capable of storing data for a long time ( EEPROM or FRAM) and a memory address selection circuit 87d.
[0047]
In this example, an EEPROM 87c that requires a boosted voltage for data rewriting (erasing and writing) is used as the nonvolatile memory. Correspondingly, a power supply booster circuit 12 is provided for receiving the internal power supply and generating the boosted voltage.
[0048]
Further, the boosting clock generation circuit 13 for supplying a clock signal to the power boosting circuit 12, and the detection of the time when the internal power supply voltage drops below a certain value as the external input level decreases, and outputs a detection flag signal, An internal power supply voltage drop detection circuit (external input level drop detection circuit) 11 for inputting the detection flag to the flag input port of the control circuit 15 is provided.
[0049]
The internal power supply voltage drop detection circuit 11 receives a resistor 111 inserted in a signal path between the RF signal input terminal 81 and the internal power supply generation circuit 82 and a band that receives the internal power supply and generates a bandgap reference voltage. When the gap reference power supply 112 and the internal power supply are operating power supplies, the voltage drop (current detection voltage) generated in the resistor 111 is compared with the bandgap reference voltage, and when the internal power supply voltage drops below the bandgap reference voltage And a voltage comparison circuit 113 that detects and outputs a detection flag signal.
[0050]
The control circuit 15 allows data writing to the EEPROM 87c while the detection flag signal is not input, and if the detection flag signal is input, the wireless card is hosted to such an extent that the power supply energy necessary for data writing to the EEPROM 87c is insufficient. It has a control function to determine that the electric field supplied from the host is weakened away from the host and to stop the data writing operation to the EEPROM 87c.
[0051]
On the other hand, the power boosting circuit 12 is composed of a switch element SW group and a capacitor C group as shown in FIG. 2, for example, and the switch element SW group is switch-controlled by complementary clock signals φ and / φ. Since this configuration and operation are well known, description thereof is omitted, but the boosted voltage is controlled in accordance with the cycle of the clock signal.
[0052]
The boost clock generation circuit 13 is configured, for example, as shown in FIG. 3, and uses an internal power supply voltage as an operation power supply to generate a clock signal based on the system clock signal.
[0053]
That is, the boost clock generation circuit 13 shown in FIG. 3 includes a timing counter 131 that generates a switching timing signal whose logic level is inverted after counting a predetermined number of the system clock signal inputs, and a binary that counts the system clock signal inputs. It consists of a counter 132 and a selector 133.
[0054]
The selector 133 outputs a complementary signal having a first period and a complementary signal having a second period, which are output from two different circuit stages of the binary counter 132, according to the logic level of the switching timing signal of the timing counter 131. Are selected and output as the first clock signals φ1, / φ1 or the second clock signals φ2, / φ2.
[0055]
That is, as shown in FIG. 4, the boost clock generation circuit 13 generates the first clock signals φ1 and / φ1 having the first period at the initial stage when the internal power supply voltage rises, and thereafter the second clock signal Second clock signals φ2 and / φ2 having a period (longer than the first period) are generated.
[0056]
When the clock signals φ1, / φ1 or φ2, / φ2 whose periods are controlled in this way are supplied to the power boosting circuit 12 as the clock signals φ, / φ, the boosted voltage output from the power boosting circuit 12 is as shown in FIG. As shown in FIG. 5, the slope becomes abrupt at the initial stage of rising, and thereafter (including the vicinity where the boosting is almost completed) has a boosting characteristic where the slope becomes gentle.
[0057]
Therefore, when data is written to the EEPROM 87c, since it gradually changes in the vicinity where the boosted voltage becomes high, the impact on the EEPROM 87c can be suppressed, and since the rise of the boosted voltage itself is abrupt, the entire processing time is reduced. It becomes possible to shorten.
[0058]
The means for controlling the cycle of the clock signal output from the booster clock generation circuit 13 is not limited to the above embodiment, and the means for controlling the boosting characteristic of the boosted voltage output from the power supply booster circuit 12 is as described above. It is not limited to examples.
[0059]
On the other hand, the random number signal generation circuit 14 is configured, for example, as shown in FIG. 6 so as to generate a random number signal used for controlling the generation timing of identification number data in hardware.
[0060]
In other words, in FIG. 6, the first clock generation circuit 61 generates a first clock signal CK1 having a first frequency (for example, a frequency in the range of 1 to 10 and several MHz), and the second clock generation circuit 62. Generates a second clock signal CK2 having a second frequency sufficiently lower than the first frequency.
[0061]
In this case, each of the clock generation circuits 61 and 62 can also be used as a clock generation circuit having another purpose used in other parts of the wireless card, or an external clock signal can be input as at least one of the clock signals. By using this, the circuit scale of the chip may be suppressed.
[0062]
For example, when the system clock signal input is used as the first clock signal CK1, the first clock generation circuit 61 is omitted, and the second clock generation circuit 62 divides the system clock signal input to obtain the first clock signal CK1. A frequency dividing circuit (not shown) that generates the second clock signal CK2 may be used.
[0063]
Alternatively, when the system clock signal input is used as the second clock signal CK2, the second clock generation circuit 62 is omitted, and the first clock generation circuit 61 multiplies the system clock signal input to A multiplier circuit that generates one clock signal CK1 may be used.
[0064]
The first clock signal CK1 is input to the data input terminal D of the first stage of a shift register 63 (the number of stages n is determined by the number of random numbers to be generated) composed of a plurality (n) stages of shift circuits. The second clock signal CK2 is input to the shift clock input terminal CK.
[0065]
In this case, the timing at which the first clock signal CK1 is captured by the second clock signal CK2 having a frequency sufficiently lower than that of the first clock signal CK1 and having no frequency correlation (different phase) with the first clock signal. Therefore, a random number signal (uncorrelated data) is generated at each stage output of the shift register 63.
[0066]
If the frequency relationship between the first clock signal CK1 and the second clock signal CK2 is opposite to that described above, the output of each stage of the shift register 63 may be “H” or “L”. And random number signals are not generated.
[0067]
Each stage output of the shift register 63 is input to a data register 64 composed of n latch circuits, and is latched by a latch signal supplied from the control circuit 15 at a predetermined timing. The output (random number signal) of the data register 64 is output to the data bus through the output gate circuit 65 controlled by the output enable signal supplied at a predetermined timing from the control circuit 15 and used.
[0068]
According to the random number signal generation circuit shown in FIG. 6 as described above, the random number signal is irregularly generated to control the generation timing of the identification number data and the number of bits, even though it has a very simple hardware configuration. It is possible to generate encryption key data with a large amount of data.
[0069]
In the above-described embodiment, the case where the radio wave transmitted / received to / from the host is an ASK signal that is amplitude-modulated by the data signal is not limited to this, but is an FSK signal that is frequency-modulated by the data signal. In this case, the present invention can be applied.
[0070]
The application of the internal power supply voltage reduction circuit 11 in the above embodiment is limited to a non-contact type IC card, but the power supply boost circuit 12, the boost clock generation circuit 13, and the random number signal generation circuit 14 are non-contact type. The present invention can be applied not only to an IC card but also to a contact type IC card.
[0071]
【The invention's effect】
As described above, according to the present invention, there is provided a non-contact type IC card capable of guaranteeing a stable data writing operation with respect to the built-in EEPROM even when the power source energy is insufficient in the middle of data writing as the distance from the host side increases. Can be provided.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an example of an IC chip of a wireless card according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of a power supply booster circuit in FIG. 1;
FIG. 3 is a circuit diagram showing an example of a boost clock generation circuit in FIG. 1;
4 is a waveform diagram showing an example of an output signal of the boost clock generation circuit of FIG. 3. FIG.
5 is a waveform diagram showing an example of a boosted voltage when the clock signal of FIG. 4 is supplied to the power booster circuit of FIG.
6 is a circuit diagram showing an example of a random number signal generation circuit in FIG. 1. FIG.
FIG. 7 is a block diagram showing an example of the configuration of a non-contact type tag identification system (RFID system).
8 is a circuit diagram specifically showing a conventional example of an internal circuit of the wireless card in FIG. 7. FIG.
FIG. 9 is a waveform diagram showing the boosting characteristics of the power boosting circuit in FIG.
[Explanation of symbols]
11 ... Internal power supply voltage drop detection circuit,
12: Power booster circuit,
13 ... Boost clock generation circuit,
14 ... Random number signal generation circuit,
15 ... control circuit,
81 ... RF signal input terminal,
82. Internal power generation circuit,
83 ... Power-on circuit,
84: Clock generation circuit,
85: Data demodulation circuit,
86: Transmission pulse generation circuit,
87 ... Semiconductor memory part,
87c: EEPROM.

Claims (1)

In a non-contact type IC card that includes an antenna coil that serves as both power reception and data transmission and an integrated circuit chip on which a semiconductor memory and a control circuit are formed, the integrated circuit chip includes:
An internal power generation circuit that generates an internal power supply voltage from a high-frequency signal input from the antenna coil;
A data demodulating circuit for restoring a received data signal from a high-frequency signal input from the antenna coil;
A clock generation circuit that generates a system clock signal based on a high-frequency signal input from the antenna coil;
Electrically erasable and rewritable memory;
A power supply booster circuit that receives the internal power supply voltage and generates a boosted voltage for supplying to the memory;
An internal power supply voltage drop detection circuit that detects when the internal power supply voltage drops below a certain value and outputs a detection flag signal;
Control is performed so that data can be rewritten to the memory during a period when the internal power supply voltage is received and the detection flag signal is not received. When the detection flag signal is received, data is rewritten to the memory. And a control circuit that controls so as to be impossible ,
The internal power supply voltage drop detection circuit is
A resistor inserted in a signal path between the terminal to which the high-frequency signal is input and the internal power generation circuit;
A bandgap reference power supply that receives the internal power supply voltage and generates a bandgap reference voltage;
A voltage comparison circuit that compares the voltage drop generated in the resistor with the band gap reference voltage, detects when the internal power supply voltage drops below the band gap reference voltage, and outputs the detection flag signal
IC card characterized in that it comprises and.

Images