JP3828376B2 - Storage system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a storage system, for example, a storage system including an electrically rewritable multi-value storage nonvolatile semiconductor memory device (EEPROM).
[0002]
[Prior art]
In recent years, a NAND cell type EEPROM has been proposed as one of electrically rewritable nonvolatile semiconductor devices (EEPROMs).
[0003]
In this EEPROM, for example, a plurality of n-channel FETMOS structure memory cells in which floating gates and control gates are stacked as charge storage layers are connected in series in such a manner that their sources and drains are shared by adjacent ones. Is connected to the bit line as a unit.
[0004]
36A and 36B are diagrams showing one NAND cell portion of the memory cell array, where FIG. 36A is a plan view and FIG. 36B is an equivalent circuit diagram. FIG. 37 is a cross-sectional view, FIG. 37A is a cross-sectional view taken along line AA ′ in FIG. 36A, and FIG. 37B is a cross-sectional view taken along line BB ′ in FIG. It is.
[0005]
The p-type silicon substrate (or p-type well) 11 is provided with an element region surrounded by an element isolation oxide film 12. NAND cells are formed in the element region, and a memory cell array is formed by collecting a plurality of NAND cells.
[0006]
With reference to FIGS. 36 and 37, description will be given focusing on one NAND cell.
[0007]
In the devices shown in FIGS. 36 and 37, eight memory cells M1 to M8 are connected in series to constitute one NAND cell. Each memory cell has a floating gate 14 (14-1, 14-2,..., 14-8) formed on a substrate 11 via a gate insulating film 13. A control gate 16 is formed on the floating gate 14 via a second gate insulating film 15. Each of the n-type diffusion layers 19 serving as the source and drain of the memory cell is shared by adjacent memory cells. Thereby, the eight memory cells are connected in series with each other.
[0008]
On the drain side and the source side of the NAND cell, first select gates 14-9 and 16- formed simultaneously with the floating gates 14-1 to 14-8 and the control gates 16-1 to 16-8 of the memory cell, respectively. 9 and second selection gates 14-10 and 16-10 are provided. An upper portion of the substrate 11 on which elements such as memory cells are formed is covered with a CVD oxide film 17. A bit line 18 is provided on the CVD oxide film 17. The control gates 16 of the NAND cells are formed continuously in the row direction, and are shared by the NAND cells adjacent in the row direction and function as word lines (control gates CG1, CG2,..., CG8). The select gates 14-9, 16-9, and 14-10, 16-10 are formed continuously in the row direction in the same manner as the control gates 16-1 to 16-8, and NAND cells adjacent in the row direction are connected to each other. And function as selection gates SG1 and SG2.
[0009]
FIG. 38 is an equivalent circuit diagram of a memory cell array in which the NAND cells are arranged in a matrix.
[0010]
As shown in FIG. 38, the source line is connected to a reference potential wiring made of aluminum, conductive polysilicon, or the like via a contact. One contact is provided between the source line and the reference potential wiring, for example, for every 64 bit lines. The reference potential wiring is connected to a peripheral circuit (not shown) that controls the potential applied to the source line according to the operation mode, for example.
[0011]
The control gates CG1, CG2,..., The first and second selection gates SG1, SG2 are continuously arranged in the row direction. Usually, a set of memory cells connected to the control gate is called a page (one page), and is sandwiched between a pair of drain side (first selection gate) and source side (second selection gate) selection gates. A set of pages is referred to as a NAND block (1 NAND block) or a block (1 block). One page is composed of, for example, 256 bytes (256 × 8) memory cells. The memory cells for one page are written almost simultaneously. One block is composed of, for example, 2048 bytes (2048 × 8) memory cells. The memory cells for one block are erased almost simultaneously.
[0012]
The operation of the NAND type EEPROM is as follows.
[0013]
Data writing is performed in order from the memory cell far from the bit line.
[0014]
A boosted write voltage Vpp (= about 20 V) is applied to the control gate of the selected memory cell, and an intermediate potential (= 10V) is applied, and 0V ("0" write) or an intermediate potential ("1" write) is applied to the bit line according to the data. At this time, the potential of the bit line is transmitted to the selected memory cell. When the data is “0”, a high voltage is applied between the floating gate of the selected memory cell and the substrate, electrons are tunneled from the substrate to the floating gate, and the threshold voltage is positive. Moving. When the data is “1”, the threshold voltage does not change.
Data erasure is performed almost simultaneously in units of blocks.
[0015]
That is, all the control gates and selection gates included in the block to be erased are set to 0 V, and the boosted boosted potential VppE (about 20 V) is applied to the p-type silicon substrate (or p-type well and n-type substrate). To do. On the other hand, the boosted potential VppE is applied to the control gate and selection gate included in the block that is not erased. Thereby, in the memory cell of the block to be erased, the electrons accumulated in the floating gate are released to the p-type silicon substrate (or well), and the threshold voltage moves in the negative direction.
[0016]
In the data read operation, after precharging the bit line, the bit line is floated, the control gate of the selected memory cell is set to 0 V, the control gates of the other memory cells, the selection gate is set to the power supply voltage Vcc (for example, 3 V), This is done by setting the source line to 0 V and detecting whether a current flows in the selected memory cell on the bit line. That is, if the data written in the memory cell is “0” (threshold value Vth> 0 of the memory cell), the memory cell is turned off, so that the bit line maintains the precharge potential, but “1” (memory cell If the threshold value Vth <0), the memory cell is turned on and the bit line is lowered from the precharge potential by ΔV. By detecting these bit line potentials with a sense amplifier, data in the memory cell is read out.
[0017]
More recently, a multi-value storage cell in which information of three or more values is stored in one cell is known as one method for realizing a large capacity of an EEPROM (for example, Japanese Patent Laid-Open No. 7-93979). JP-A-7-161852).
[0018]
FIG. 39 shows the threshold voltage of the memory cell and the four write states (four-value data “0”, “1” when four values are stored by providing four write states in one memory cell. And “2”, “3”).
[0019]
The state of data “0” is the same as the state after erasure and has, for example, a negative threshold value. The state of data “1” has a threshold value between 0.5V and 0.8V, for example. The state of data “2” has a threshold value between 1.5V and 1.8V, for example. The state of data “3” has a threshold value between 2.5V and 2.8V, for example.
[0020]
Therefore, the read voltage VCG2R is applied to the control gate CG of the memory cell M, the memory cell is “ON” or “OFF”, and the memory cell data is “0” or “1”. “Either“ 2 ”or“ 3 ”” can be detected. Subsequently, the memory cell data is completely detected by applying the read voltages VCG3R and VCG1R. The read voltages VCG1R, VCG2R, and VCG3R are, for example, 0V, 1V, and 2V, respectively.
[0021]
The voltages VCG1V, VCG2V, and VCG3V are called verify voltages. When data is written, these verify voltages are applied to the control gate to detect the state of the memory cell M and check whether the data has been sufficiently written. To do. The verify voltages VCG1V, VCG2V, and VCG3V are, for example, 0.5V, 1.5V, and 2.5V, respectively.
[0022]
[Problems to be solved by the invention]
In the flash memory, the number of rewrites is limited to, for example, 1 million times in a binary memory cell. This limitation on the number of rewrites is caused by, for example, leakage of electrons stored in the floating gate from the floating gate of the memory cell in the written state to the substrate. When the memory cell is in the data “0” state due to the leakage of electrons from the memory cell in the data “1” state in FIG. 39, the write data is destroyed.
[0023]
When multilevel data is stored in the memory cell, the voltage difference between states (for example, the voltage difference between the “3” state and the “2” state in FIG. 39) becomes small. As a result, even if a small amount of electrons leaks to the substrate, the data changes from the “3” state to the “2” state. Further, when the memory cell is multi-valued, the threshold value in the state where the threshold value is the largest (“3” state in FIG. 39) is increased, so that the electric field between the floating gate and the substrate is increased. As a result, the amount of electron leakage from the floating gate increases.
[0024]
From the above situation, as the number of memory cells is increased, the reliability, in particular, the reliability with respect to the number of data rewrites deteriorates, and the limit value of the number of rewrites decreases, for example, 500,000 times. As a result, the durability of the device (the life of the device) is impaired.
[0025]
In a conventional memory card (for example, N.Niijima; IBM J.RES.DEVELOP.VOL.39 NO.5 SEPTEMBER 1995), the number of rewrites is recorded for each block, and the number of rewrites exceeds, for example, 1 million times. Does not use the block. However, even in this method, the more the multi-value storage is performed, the smaller the number of times the memory card is used than in the binary storage.
[0026]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a storage system that includes a multi-value storage memory cell and has high durability especially with respect to rewriting.
[0027]
Another object is to provide a storage system including several new system elements necessary for the storage system to achieve the above object.
[0028]
[Means for Solving the Problems]
In order to achieve the above object, the present inventionIn the storage system according to the first aspect of the present invention, a plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewritable, and the plurality of memory cells are controlled. A control circuit, wherein the control circuit controls a part of the plurality of memory cells as a storage part of the n value, and sets a different part of the memory cells to an m value (m is a natural number of 2 or more, Control as a storage portion of m <n), and further, control information indicating which memory cell is controlled as a storage portion of m value is stored in some different memory cells.It is characterized by that.
[0029]
Also,In the storage system according to the second aspect of the present invention, a plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewritable, and the plurality of memory cells are provided. A control circuit for controlling, wherein the control circuit controls a part of the plurality of memory cells as a storage part of the n value, and sets a different part of the memory cells to an m value (m is a natural number of 2 or more). Yes, it is controlled as a memory part of m <n), further, control information indicating which memory cell is controlled as a memory part of m value is stored in a part of different memory cells, and m value is obtained by rewriting the control information. Change memory cell to storeIt is characterized by that.
In the storage system according to the third aspect of the present invention, a plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewritable, and the plurality of memories A control circuit for controlling the cell, wherein the control circuit controls a part of the plurality of memory cells as a storage part of the n value and sets a different part of the memory cells to an m value (m is 2 or more). It is a natural number and is controlled as a storage portion of m <n), and further, control information indicating which memory cell is controlled as a storage portion of n value is stored in some different memory cells.
In the storage system according to the fourth aspect of the present invention, a plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewritable, and the plurality of memories A control circuit for controlling the cell, wherein the control circuit controls a part of the plurality of memory cells as a storage part of the n value and sets a different part of the memory cells to an m value (m is 2 or more). It is a natural number and is controlled as a storage part of m <n), and further, by storing control information on which memory cell is controlled as a storage part of n value in a part of different memory cells, rewriting the control information The memory cell for storing the n value is changed.
In the memory system according to the fifth aspect of the present invention, a memory cell array composed of a plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewritable. And a control circuit for controlling the plurality of memory cells, wherein the control circuit controls a part of the memory cell array as a storage part for the n value and a different part of the memory cell array for an m value ( m is 2 or more It is a number, and is controlled as a storage portion of m <n), and control information indicating which portion of the memory cell array is controlled as a storage portion of the m value is stored in a further different part of the memory cell array. To do.
In the storage system according to the sixth aspect of the present invention, a memory cell array comprising a plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewritable. And a control circuit for controlling the plurality of memory cells, wherein the control circuit controls a part of the memory cell array as a storage part for the n value and a different part of the memory cell array for an m value ( m is a natural number of 2 or more, and is controlled as a storage portion of m <n), and control information on which portion of the memory cell array is controlled as a storage portion of m value is stored in a different part of the memory cell array. The memory cell array for storing m values is changed by rewriting the control information.
In the memory system according to the seventh aspect of the present invention, a memory cell array comprising a plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewritable. And a control circuit for controlling the plurality of memory cells, wherein the control circuit controls a part of the memory cell array as a storage part for the n value and a different part of the memory cell array for an m value ( m is a natural number equal to or greater than 2, and is controlled as a storage portion of m <n), and control information indicating which portion of the memory cell array is controlled as an n-value storage portion is stored in a further different portion of the memory cell array. It is characterized by that.
In the memory system according to the eighth aspect of the present invention, a memory cell array comprising a plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewritable. And a control circuit for controlling the plurality of memory cells, wherein the control circuit controls a part of the memory cell array as a storage part for the n value and a different part of the memory cell array for an m value ( m is a natural number equal to or greater than 2, and is controlled as a storage portion of m <n), and control information indicating which portion of the memory cell array is controlled as an n-value storage portion is stored in a different part of the memory cell array. The memory cell array for storing n values is changed by rewriting the control information.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described by taking a multi-level NAND flash memory as an example.
[0031]
1 to 3 are diagrams showing the relationship between threshold voltage and multi-value data in each storage mode of the multi-value NAND flash memory according to the first embodiment of the present invention.
[0032]
FIG. 1 shows one example of the relationship between the threshold voltage and the quaternary data in the quaternary operation mode, and FIGS. 2A to 2C show the relationship between the threshold voltage and the quaternary operation mode. Three examples of the relationship between the threshold voltage and the ternary data are shown in FIGS. 3A and 3B. The relationship between the threshold voltage and the binary data in the binary operation mode is shown in FIGS. Each example is shown.
[0033]
1 to 3, “0” is an erased state, and “1”, “2”, and “3” are write states. The internal operations (writing, reading, erasing, etc.) of the multi-level NAND flash memory are described in Japanese Patent Application Laid-Open Nos. 7-93979, 7-161852, 7-295137, and 8-61443. It is said that it is described in Japanese Patent Application No. 8-61445.
[0034]
As described above, in the field of EEPROM, as the number of values increases, the number of rewritable times decreases. For example, a quaternary cell having a quaternary storage state as shown in FIG. 1 has 500,000 times, a ternary cell having a ternary storage state as shown in FIG. In a binary cell taking a value storage state, 1 million times is a rewritable range.
[0035]
According to the present invention, first, the memory cell is used as a quaternary cell having a storage state as shown in FIG. 1 until 500,000 times of rewriting is performed. Until 500,000 times of rewriting is performed after 500,000 times of rewriting, it is used as a ternary cell as shown in FIGS. After 800,000 times of rewriting, it is used as a binary cell as shown in FIG.
[0036]
Further, in order to simplify the operation method of the apparatus, it is used as a quaternary cell until 500,000 times of rewriting, and after 500,000 times of rewriting, it is used as a binary cell. Anyway.
[0037]
Thus, when the limit of the number of times of rewriting as a quaternary cell is exceeded, the number of times of use of the flash memory can be increased by using it as a ternary cell or a binary cell. Therefore, the durability especially for rewriting is improved as compared with the conventional multi-value storage flash memory.
[0038]
The above-mentioned durability is not only improved as the durability of the flash memory alone, that is, the durability of the chip, but also by incorporating this flash memory into various memory devices (for example, memory cards), Durability is also improved.
[0039]
Whether the memory cell is operated as a quaternary value, a ternary value, or a binary value may be controlled by inputting a command to the flash memory from the outside of the chip. That is, as an operation mode in the flash memory, a quaternary write operation mode (or operation method) / read operation mode (or operation method), a ternary write operation mode (or operation method) / read operation mode (or operation) Method) Binary write operation mode (or operation method) / read operation mode (or operation method) are provided, and one of these operation modes (or operation methods) is selected by inputting a command, You may control the operation.
[0040]
Alternatively, whether the memory cell is operated as a 4-value, a 3-value, or a 2-value may be controlled by write data input from a controller that controls the flash memory. That is, without changing the internal operation of the flash memory, the write data input from the outside is controlled to be quaternary, ternary, binary, or sequentially, quaternary, binary. That is, when operating as a quaternary cell, four values “0”, “1”, “2”, “3” are input, and when operating as a ternary cell, “0”, “1”, “ When operating as a binary cell by inputting three values of “2 ″”, the respective input data values may be controlled so as to input two values of ““ 0 ”and“ 1 ””.
[0041]
Further, when the limit of the number of rewrites as a binary cell is exceeded, the cell may not be used.
[0042]
Further, when the limit of the number of rewrites as a binary cell is exceeded, data may not be written or erased in the cell. In this case, since the cell is not rewritten, it can be used as a ROM. When used as a ROM, the degree of deterioration of the cell, particularly the tunnel oxide film, determines the memory retention period. However, even if the number of rewrites reaches the limit, the cell usually has sufficient reliability to withstand as a ROM. This is because the limit on the number of rewrites is set with a certain margin before the tunnel oxide film can no longer be used.
[0043]
Next explained is a storage system according to the second embodiment of the invention.
[0044]
FIG. 4 is a configuration diagram of a flash memory according to the second embodiment.
[0045]
As shown in FIG. 4, the controller 100 controls the operation of k (k is a natural number) multilevel NAND flash memory chips 101-1 to 101-k.
[0046]
FIG. 5 is a configuration diagram of the chip 101 of the multi-level NAND flash memory shown in FIG. The chip 101 shown in FIG. 4 includes a plurality of memory cells, and each of these memory cells has a threshold voltage distribution corresponding to the multilevel storage level, as described in the first embodiment. have. The threshold voltage distribution is the same as that shown in FIGS. 1 to 3, for example. As shown in FIGS. 1 to 3, “0” indicates an erased state, and “1”, “2”, and “3” indicate writing. State.
[0047]
The internal operations (writing, reading, erasing, etc.) of the multi-level NAND flash memory are described in Japanese Patent Application Laid-Open Nos. 7-93979, 7-161852, 7-295137, and 8-61443. It is said that it is described in Japanese Patent Application No. 8-61445.
[0048]
One page, which is a unit for simultaneous writing, is composed of 528 bytes of memory cells, of which, for example, 512 bytes of memory cells correspond to the data area, and the remaining 16 bytes of memory cells correspond to logical addresses and physical addresses. An address conversion table and an error correcting code (ECC) are stored.
[0049]
In FIG. 5, one chip is composed of 512 blocks, and one block, which is a unit for simultaneously erasing, is composed of 16 pages. For example, the first block Block0 is used as a system area. That is, Block 0 may store the number of rewrites of each block, which block is broken, or the block sequence number S. Hereinafter, the portion for storing the number of rewrites is referred to as a rewrite number recording area. Details of the explanation such as the block sequence number S are described in the publicly known example N. Niijima; IBM J. RES. DEVELOP. VOL. 39 NO. 5 SEPTEMBER 1995. In this case, each time writing / erasing is repeated, the first block in which the number of rewrites is stored is rewritten. As described above, since rewriting is frequently performed in the system block, the lifetime of the memory cells in the system area may be shorter than the lifetimes of the memory cells in other data areas.
[0050]
FIG. 6 is a configuration diagram of a storage system according to a modification of the second embodiment.
[0051]
As described above, when the lifetime of the memory cell in the system area becomes shorter than the lifetime of the memory cell in the other data area, the DRAM 102 that stores the system area such as the rewrite count recording area as shown in FIG. You may prepare. When the power is turned on (during operation), data in the system area of the flash memory is read and stored in the DRAM. Thereafter, the system area is rewritten for data writing, erasing, rewriting, etc. At this time, the system area stored in the DRAM may be rewritten. Based on the data in the system area on the DRAM, the data in the system area of the flash memory may be rewritten when the power is turned off or at regular intervals.
[0052]
As described above, the system area in the flash memory can be prevented from being frequently rewritten by rewriting the system area during the operation on the data in the DRAM.
[0053]
If the address conversion table needs to be rewritten when writing, erasing, or rewriting data, the contents of the address conversion table may be stored in the DRAM and rewritten in the DRAM.
[0054]
In this embodiment, description will be made by taking a quaternary flash memory as an example. For example, it is possible to rewrite 500,000 times in a quaternary memory cell as shown in FIG. 1 and 1 million times in a binary memory cell as shown in FIGS.
[0055]
According to this embodiment, first, the memory cell is used in the quaternary mode as a quaternary cell as shown in FIG. The number of rewrites of each block is stored in the rewrite count recording area of the system area on the flash memory when the power is off, and stored in the rewrite count recording area of the DRAM when the power is turned on (during operation).
[0056]
After rewriting 500,000 times, the binary cell is used in the binary mode as shown in FIGS. Switching between the quaternary mode and the binary mode may be performed in units of one page or in units of one block, may be performed in units of a plurality of blocks, or may be performed in units of chips. Level storage means for holding whether each page, each block, or each chip is in binary mode or quaternary mode, stores information on the operation mode in the system area of the flash memory when the power is turned off, When power is turned on (operation), it may be stored in DRAM. When the power is turned on, it is possible to determine the value at which the memory cell is operated by reading the level storage means.
[0057]
As described above, when the limit of the number of times of rewriting as a quaternary cell is exceeded, by using it as a binary cell, the number of times of use of the flash memory can be increased.
[0058]
Whether the memory cell is operated as a quaternary value or a binary value may be controlled by inputting a command from the controller 100 to the flash memory. That is, as an operation mode inside the flash memory, a quaternary write operation mode (or operation method) / read operation mode (or operation method), a binary write operation mode (or operation method) / read operation mode (or operation) Method), and any one of these operation modes (or operation methods) may be selected by inputting a command to control each operation.
[0059]
Alternatively, whether the memory cell is operated as a quaternary value or a binary value may be controlled by write data input from the controller 100 that controls the flash memory. In other words, the write data input from the outside is controlled to four values and two values without changing the internal operation of the flash memory. That is, when operating as a quaternary cell, four values “0”, “1”, “2”, “3” are input, and when operating as a binary cell, “0”, “1” ”. Each input data value may be controlled so as to input two values.
[0060]
Further, the number of memory cells in the data area in one page may or may not be changed between the quaternary mode and the binary mode. In quaternary mode and binary mode, out of 528 bytes of memory cells, for example, 512 bytes of memory cells are data areas, and the remaining 16 bytes of memory cells indicate the correspondence between logical addresses and physical addresses. Alternatively, an error correction code (ECC) may be stored. Alternatively, the address conversion table and ECC area may be optimized in the quaternary mode and the binary mode. For example, the address conversion table and ECC area used 16-byte memory cells in the 4-level mode, whereas 24-byte memory cells may be used in the 2-level mode, or 8-byte memory cells. May be used. In either case, a data area other than the address conversion table or ECC area may be used.
[0061]
In the rewrite count recording area, data is updated every time each block is rewritten. Therefore, by monitoring this rewrite count recording area, it is sufficient to determine the value at which the memory cell operates. That is, the rewrite count recording area in the DRAM is read before rewrite, and when the rewrite count of the block to be written is 500,000 times or less, the block is written as a quaternary cell. If the number of rewrites exceeds 500,000, the contents of the level storage means in the DRAM are changed to be binary cells instead of quaternary cells in this embodiment, and the block is changed to a binary cell. Write. If the number of times exceeds one million times, the block may not be used, or writing or erasing may not be performed.
[0062]
In the second embodiment, for example, the number of rewrites is recorded for each block, and what value is determined for each block is determined. Further, the unit for determining the value of operation is not limited to the block. For example, one rewrite count recording area may be provided for a plurality of blocks, and the value of the operation for each block may be determined. Alternatively, one rewrite count recording area may be provided for each flash memory chip, and the value to be operated in units of chips may be determined. Furthermore, the number of rewrites may be monitored for each page, and what value may be operated for each page may be determined.
[0063]
In the second embodiment, the value memory cell is determined by monitoring the number of rewrites. For example, the value memory cell is operated by monitoring the time after shipment. You may decide.
[0064]
Next explained is a storage system according to the third embodiment of the invention.
[0065]
Hereinafter, several storage systems according to the present invention will be given, and these will be described as the storage system according to the third embodiment.
[0066]
FIG. 7 is a diagram illustrating an operation flow of the first storage system according to the third embodiment.
[0067]
The first storage system includes memory cells that store n values (n is a natural number of 3 or more, for example, 3 or 4 or 8 or 16). As shown in FIG. 7, the memory cell operates as an n-value memory cell up to a predetermined number of rewrites (for example, 500,000 times). Thereafter, the memory system operates as a memory cell having m values (m is a natural number less than n).
[0068]
As described in the second embodiment, the number of rewrites is recorded in the rewrite count storage area of each block or each chip, and by monitoring this rewrite count storage area, the value memory cell is operated. You can decide.
[0069]
FIG. 8 is a diagram illustrating an operation flow of the second storage system according to the third embodiment.
[0070]
The second storage system includes memory cells that store n values (n is a natural number of 3 or more, for example, 3 or 4 or 8 or 16). As shown in FIG. 8, the memory cell operates as an n-value memory cell up to a predetermined number of rewrites. Thereafter, the memory system operates as a binary memory cell.
[0071]
FIG. 9 is a diagram illustrating an operation flow of the third storage system according to the third embodiment.
[0072]
The third storage system includes memory cells that store n values (n is a natural number of 3 or more, for example, 3 or 4 or 8 or 16). Then, as shown in FIG. 9, the memory cell operates as an n-value memory cell until the nth rewrite count, and the memory cell has an (n-1) value until the (n-1) th rewrite count. The memory system operates and the memory cell operates as an i value up to the i-th (i is a natural number of 2 or more) rewrite times.
[0073]
Here, the predetermined number of rewrites set corresponding to the limit value of the number of rewrites as the n-value cell, the (n−1) -value cell, and the i-value cell, respectively, -1) is defined as the number of rewrites and the i-th rewrite number.
[0074]
The fourth storage system includes memory cells that store n values (n is a natural number of 3 or more, for example, 3 or 4 or 8 or 16). In the semiconductor memory device, the memory system has level storage means for storing what value data the memory cell holds.
[0075]
The level storage means may store the stored contents in the first block of the flash memory chip, for example, Block 0 shown in FIG.
[0076]
Alternatively, the level storage means may be read when the power is turned on, and the stored contents may be stored in the DRAM 102 shown in FIG. For example, if it is determined that the number of rewrites has reached 500,000 by reading the rewrite count storage area, what has been operating as a quaternary memory cell changes the contents of the level storage means. What is necessary is just to operate | move as a binary memory cell. Thereafter, writing is performed as a binary cell by reading the level storage means. That is, here, when the power is turned on, the level storage means is read to determine what value the memory cell is operated at any time.
[0077]
The fifth storage system includes memory cells that store n values (n is a natural number of 3 or more, for example, 3 or 4 or 8 or 16), and a predetermined number of memory cells constitute a memory cell block, The semiconductor memory device performs writing or erasing in units of memory cell blocks, and the memory cells in the memory cell block operate as n-value memory cells up to a predetermined number of rewrites. Thereafter, in the memory system, all the memory cells in the memory cell block operate as memory cells having m values (m is a natural number less than n).
[0078]
The fifth storage system has a rewrite count storage area for storing the rewrite count of the memory cell block for each memory cell block. What value memory cell the memory cell block operates with may be determined according to the number of rewrites stored in the rewrite number storage area.
[0079]
Note that the memory cell block here is not limited to a so-called block, which is a set of pages sandwiched between one drain-side selection gate and one source-side selection gate. It shows a memory cell group in which writing or erasing is performed simultaneously. For example, in a NAND type EEPROM, writing is usually performed in units of pages as described above, and erasing is performed in units of blocks. In this case, these pages or blocks are stored in the memory cell block here. Equivalent to.
[0080]
A sixth storage system is a semiconductor storage device including a memory cell that stores an n value (n is a natural number of 3 or more, for example, 3 or 4 or 8 or 16). It operates as an n-value memory cell. Thereafter, in the memory system, all the memory cells in the chip including the memory cell operate as m-value memory cells (m is a natural number less than n).
[0081]
The sixth storage system has a rewrite count storage area for storing the number of rewrites of each chip for each chip. What value memory cell the chip operates with may be determined according to the number of rewrites stored in the rewrite number storage area.
[0082]
FIG. 10 is a diagram illustrating an operation flow of the seventh storage system according to the third embodiment.
[0083]
The seventh storage system includes memory cells that store n values (n is a natural number of 3 or more, for example, 3 or 4 or 8 or 16). As shown in FIG. 10, the memory cell operates as an n-value memory cell up to the nth rewrite cycle, and as a m-value (m is a natural number less than n) memory cell up to the mth rewrite cycle. A storage system that operates and does not use the memory cell thereafter.
[0084]
FIG. 11 is a diagram showing an operation flow of the eighth storage system according to the third embodiment.
[0085]
The eighth storage system includes memory cells that store n values (n is a natural number of 3 or more, for example, 3 or 4 or 8 or 16). Then, as shown in FIG. 11, the memory cell operates as an n-value memory cell until the nth rewrite count, operates as a binary memory cell until the second rewrite count, and thereafter, A storage system that does not use memory cells.
[0086]
FIG. 12 is a diagram illustrating an operation flow of the ninth storage system according to the third embodiment.
[0087]
The ninth storage system includes a memory cell that stores n values (n is a natural number of 3 or more, for example, 3 or 4 or 8 or 16). Then, as shown in FIG. 12, the memory cell operates as an n-value memory cell until the nth rewrite count, and the memory cell operates as an (n-1) value until the (n-1) th rewrite count. Thereafter, the memory cell operates as an i value up to the i-th (i is a natural number of 2 or more) rewrite sequence. After that, after reaching the second rewrite count, the memory system does not use the memory cell.
[0088]
FIG. 13 is a diagram illustrating an operation flow of the tenth storage system according to the third embodiment.
[0089]
The tenth storage system includes memory cells that store n values (n is a natural number of 3 or more, for example, 3 or 4 or 8 or 16). As shown in FIG. 13, the memory cell operates as an n-value memory cell until the nth rewrite count, and as an m-value memory cell (m is a natural number less than n) until the mth rewrite count. A storage system that operates and thereafter does not erase or write data in the memory cell.
[0090]
FIG. 14 is a diagram illustrating an operation flow of the eleventh storage system according to the third embodiment.
[0091]
The eleventh storage system includes memory cells that store n values (n is a natural number of 3 or more, for example, 3 or 4 or 8 or 16). Then, as shown in FIG. 14, the memory cell operates as an n-value memory cell until the nth rewrite count, operates as a binary memory cell until the second rewrite count, and thereafter, A storage system that does not erase or write data in memory cells.
[0092]
FIG. 15 is a diagram illustrating an operation flow of the twelfth storage system according to the third embodiment.
[0093]
The twelfth storage system includes memory cells that store n values (n is a natural number of 3 or more, for example, 3 or 4 or 8 or 16). As shown in FIG. 15, the memory cell operates as an n-value memory cell until the nth rewrite operation, and the memory cell operates as an (n-1) value until the (n-1) th rewrite operation. Thereafter, the memory cell operates as an i value up to the i-th (i is a natural number of 2 or more) rewrite sequence. After that, after reaching the second rewrite count, the memory system does not erase or write data in the memory cell.
[0094]
FIG. 16 is a diagram illustrating an operation flow of the thirteenth storage system according to the third embodiment.
[0095]
The thirteenth storage system includes memory cells that store n values (n is a natural number of 3 or more, for example, 3 or 4 or 8 or 16). As shown in FIG. 16, the memory cell operates as an n-value memory cell until the nth rewrite count, and the memory cell operates as an (n-1) value until the (n-1) th rewrite count. Thereafter, the memory cell operates as an i value up to the i-th (i is a natural number of 3 or more) rewrite cycles. Then, after operating as a ternary value up to the third rewrite count, it is used as a binary value until the second rewrite count is reached. Thereafter, after the second number of rewrites, the data in the memory cell may not be erased or written, or the memory cell may not be used.
[0096]
Next explained is a multilevel NAND flash memory according to the fourth embodiment of the invention.
[0097]
In the flash memory according to the fourth embodiment, the value at which the flash memory operates is controlled by inputting a command from the outside of the chip. Hereinafter, a more specific 4-level NAND flash memory will be described as an example.
[0098]
In the fourth embodiment, there are four-value write / read methods and binary write / read methods as operation modes in the flash memory. Whether writing or reading for four values or writing or reading for two values is controlled by a command from a controller outside the chip.
[0099]
In the following, quaternary writing and reading methods and binary writing and reading methods will be described. Erasing is performed in block units or chip units in the same manner as in the conventional binary NAND flash memory, in the case of quaternary memory cells and binary memory cells.
[0100]
[1] When operating as a quaternary memory cell
FIG. 17 is a block diagram showing the configuration of a multi-value storage type EEPROM according to the fourth embodiment of the present invention.
[0101]
FIG. 17 shows the configuration of a multi-value storage type EEPROM. A control gate / selection gate drive circuit 2 that selects a memory cell and applies a write voltage and a read voltage to a control gate is provided for a memory cell array 1 configured by arranging memory cells in a matrix. The control gate / selection gate drive circuit 2 is connected to the address buffer 5 and receives an address signal from the address buffer 5. The data circuit 3 is a circuit for holding write data and reading memory cell data. The data circuit 3 is connected to the data input / output buffer 4 and receives an address signal from the address buffer 5. The data input / output buffer 4 performs data input / output control with the outside of the EEPROM.
[0102]
FIG. 18 is a configuration diagram showing configurations of the memory cell array 1 and the data circuit 3 shown in FIG.
[0103]
As shown in FIG. 18, the NAND cell is configured by connecting memory cells M1 to M4 in series. Both ends of the NAND cell are connected to the bit line BL and the source line Vs via the selection transistors S1 and S2, respectively. The memory cell M group sharing the control gate CG forms a unit called “page”, and data is written / read simultaneously. A block is formed by a group of memory cells connected to the four control gates CG1 to CG4. “Page” and “Block” are selected by the control gate / selection gate drive circuit 2. Data circuits 3-0 to 3-m are connected to the bit lines BL0 to BLm, and temporarily store write data to the corresponding memory cells.
[0104]
FIG. 19 shows the threshold voltage of the memory cell M and the four write states (four-value data “0”, “1”, “2” when four-value storage is performed by creating four write states in the memory cell M. It is a figure which shows the relationship of "" and "3").
[0105]
As shown in FIG. 19, the state of data “0” is the same as the state after erasing data, and has a negative threshold value, for example. The state of data “1” has a threshold value between 0.5V and 0.8V, for example. The state of data “2” has a threshold value between 1.5V and 1.8V, for example. The state of data “3” has a threshold value between 2.5V and 2.8V, for example. A read voltage VCG2R is applied to the control gate CG of the memory cell M, and the memory cell data is either “0” or “1” or “2” depending on whether the memory cell is “ON” or “OFF”. , “Any of“ 3 ”” can be detected. Subsequently, the memory cell data is completely detected by applying the read voltages VCG3R and VCG1R. The read voltages VCG1R, VCG2R, and VCG3R are, for example, 0V, 1V, and 2V, respectively. The voltages VCG1V, VCG2V and VCG3V are called verify voltages. At the time of data writing, these verify voltages are applied to the control gate to detect the state of the memory cell M and check whether or not sufficient writing has been performed. The verify voltages VCG1V, VCG2V, and VCG3V are, for example, 0.5V, 1.5V, and 2.5V, respectively.
[0106]
20 is a circuit diagram of memory cell array 1 and data circuit 3 shown in FIG.
[0107]
As shown in FIG. 20, the data circuit 3 includes a first flip-flop FF1 and a second flip-flop FF2. The first flip-flop FF1 in this embodiment is composed of n-channel MOS transistors Qn21, Qn22, Qn23 and p-channel MOS transistors Qp9, Qp10, Qp11, and is a circuit called a so-called cross-coupled latch circuit. It has become. Similarly, the second flip-flop FF2 includes n-channel MOS transistors Qn29, Qn30, and Qn31 and p-channel MOS transistors Qp16, Qp17, and Qp18, and is a so-called cross-coupled latch circuit. Yes. Write / read data is latched in the flip-flops FF1 and FF2, respectively. Each of the flip-flops FF1 and FF2 also operates as a sense amplifier that amplifies the potential of the bit line BLa or the bit line BLb, that is, amplifies data. The flip-flops FF1 and FF2 latch “write as“ 0 ”,“ 1 ”,“ 2 ”or“ 3 ”” as write data information, and Reads whether the cell holds “0” information, “1” information, “2” information, “3” information ” Sense and latch as data information.
[0108]
Data input / output lines IOA, IOB and flip-flop FF1 are connected via n-channel MOS transistors Qn28, Qn27. Data input / output lines IOC, IOD and flip-flop FF2 are connected via n-channel MOS transistors Qn35, Qn36. Data input / output lines IOA, IOB, IOC, IOD are also connected to data input / output buffer 4 in FIG.
[0109]
The gates of n-channel MOS transistors Qn27, Qn28, Qn35, Qn36 are connected to the output of a column address decoder composed of NAND logic circuit G2 and inverter I4. The n-channel MOS transistors Qn26 and Qn34 equalize the flip-flops FF1 and FF2 with the signals ECH1 and ECH2 being “H”, respectively. N-channel MOS transistors Qn24 and Qn32 control the connection between flip-flops FF1 and FF2 and MOS capacitor Qd1. N-channel MOS transistors Qn25 and Qn33 control connection between flip-flops FF1 and FF2 and MOS capacitor Qd2.
[0110]
The circuit constituted by the p-channel MOS transistors Qp12C and Qp13C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF1 by the activation signal VRFYBAC. The circuit constituted by the p-channel MOS transistors Qp14C and Qp15C changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF1 by the activation signal VRFYBBC. A circuit formed of p-channel MOS transistors Qp12C, Qp19C, and Qp20C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flops FF1 and FF2 by the activation signal VRFYBA2C. A circuit constituted by p-channel MOS transistors Qp14C, Qp21C, and Qp22C changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flops FF1 and FF2 by the activation signal VRFYBB2C.
[0111]
A circuit composed of n-channel MOS transistors Qn1C and Qn2C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF2 by the activation signal VRFYBA1C. The circuit formed of n-channel MOS transistors Qn3C and Qn4C changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF2 by the activation signal VRFYBB1C.
[0112]
MOS capacitors Qd1 and Qd2 are composed of depletion type n-channel MOS transistors, and are sufficiently smaller than the bit line capacitance. N channel MOS transistor Qn37 charges MOS capacitor Qd1 to voltage VA by signal PREA. N channel MOS transistor Qn38 charges MOS capacitor Qd2 to voltage VB by signal PREB. N-channel MOS transistors Qn39 and Qn40 control connection between the data circuit 3 and the bit lines BLa and BLb, respectively, by signals BLCA and BLCB. A circuit composed of n-channel MOS transistors Qn37 and Qn38 also serves as a bit line voltage control circuit.
[0113]
Next, the operation of the flash memory (EEPROM) including the data circuit 3 configured as shown in FIG. 20 will be described according to the timing chart. Hereinafter, a case where the control gate CG2A is selected is shown.
[0114]
<Read operation>
FIG. 21 is a timing chart during the read operation. The read operation will be described below with reference to FIG.
[0115]
As shown in FIG. 21, first, at time t1RC, the voltages VA and VB become 1.8V and 1.5V, respectively, and the potentials of the bit lines BLa and BLb become 1.8V and 1.5V, respectively. Further, the signals BLCA and BLCB become “L” level, the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected, and the bit lines BLa and BLb are in a floating state. Further, the signals PREA and PREB are respectively set to the “L” level, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state.
[0116]
Subsequently, at time t2RC, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 is set to 0 V, the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are set to VCC. The If the threshold value of the selected memory cell is 0V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 0V or higher, the bit line voltage remains 1.8V.
[0117]
Thereafter, at time t3RC, the signals BLCA and BLCB become “H” level, respectively, and the bit line data is transferred to the MOS capacitors Qd1 and Qd2. Thereafter, the signals BLCA and BLCB again become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Further, the signals SAN1 and SAP1 become “L” level and “H” level, respectively, to inactivate the flip-flop FF1, and further, the signal ECH1 becomes “H” level, and 2 of the flip-flop FF1. The two input / output terminals (nodes N3C and N4C) are equalized with each other. Further, thereafter, the signals RV1A and RV1B are set to the “H” level.
[0118]
Subsequently, at time t4RC, the signals SAN1 and SAP1 are again set to the “H” level and the “L” level, respectively, so that the voltage at the node N1 is sensed by the flip-flop FF1 and is then applied to the flip-flop FF1. Latched. Thereby, “whether the data in the memory cell is“ 0 ”,“ 1 ”,“ 2 ”or“ 3 ”) is sensed by the flip-flop FF1, and the information is latched. The selected control gate CG2A is set to 1V. As a result, if the threshold value of the selected memory cell is 1V or less, the bit line voltage becomes lower than 1.5V. If the threshold value of the selected memory cell is 1V or more, the bit line voltage remains 1.8V.
[0119]
Subsequently, at time t5RC, the signals PREA and PREB become “H” level, respectively, and the nodes N1 and N2 that are the gate electrodes of the MOS capacitors Qd1 and Qd2 become 1.8V and 1.5V, respectively. Thereafter, the signals PREA and PREB are respectively set to the “L” level, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state.
[0120]
Thereafter, at time t6RC, the signals BLCA and BLCB are set to the “H” level. Again, the signals BLCA and BLCB become “L” level, respectively, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, the signals SAN2 and SAP2 become “L” level and “H” level, respectively, so that the flip-flop FF2 is deactivated, and further, the signal ECH2 becomes “H”, so that the two flip-flops FF2 Input / output terminals (nodes N5C and N6C) are equalized with each other. Thereafter, the signals RV2A and RV2B are set to the “H” level.
[0121]
Subsequently, at time t7RC, the signals SAN2 and SAP2 are again set to the “H” level and the “L” level, respectively, so that the voltage at the node N1 is sensed by the flip-flop FF2 and then to the flip-flop FF2 Latched. Thereby, “whether the data of the memory cell is“ 0 ”or“ 1 ”,“ 2 ”or“ 3 ”” is sensed by the flip-flop FF2, and the information is latched. The relationship between the potentials of the nodes N3C and N5C of the flip-flops FF1 and FF2 at this time is as shown in FIG.
[0122]
Finally, it is sensed whether the data written in the memory cell is “2” or “3”. The selected control gate CG2A is set to 2V. If the threshold value of the selected memory cell is 2V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 2V or more, the bit line voltage remains 1.8V.
[0123]
Thereafter, at time t8RC, the signals PREA and PREB become “H” level, respectively, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 become 1.8V and 1.5V, respectively. Further, the signals PREA and PREB are respectively set to the “L” level, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state.
[0124]
Thereafter, at time t10RC, the signals BLCA and BLCB are respectively set to the “H” level. Thereafter, the signals BLCA and BLCB again become “L” level, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected.
[0125]
Prior to sensing the data of the MOS capacitor, the signal VRFYBA2C becomes 0V at time t11RC. As can be seen from FIG. 22, the node N5C is “Low level” and the node N3C is “High level” (that is, the node N4C is “Low level”) only in the case of “1” data. Therefore, only in the case of “1” data, the p-channel MOS transistors Qp12C, Qp19C, and Qp20C are turned on, and the node N1 becomes VCC. Thereafter, the signals SAN1 and SAP1 become “L” level and “H” level, respectively, the flip-flop FF1 is deactivated, and the signal ECH1 becomes “H” and equalized. Thereafter, the signals RV1A and RV1B are set to the “H” level.
[0126]
At time t12RC, the signals SAN1 and SAP1 are again set to the “H” level and the “L” level, respectively, so that the voltage of the node N1 is sensed and latched by the flip-flop FF1. Thereby, “whether the data in the memory cell is“ 2 ”or“ 3 ”” is sensed by the flip-flop FF1, and the information is latched.
[0127]
As a result of the above read operation, quaternary data is latched in the flip-flops FF1 and FF2 as shown in FIG. The threshold distribution of each data in the figure is as follows.
[0128]
Data “0”: Threshold value: 0 V or less
Data “1” ・ ・ ・ Threshold: 0.5V or more and 0.8V or less
Data “2”: Threshold: 1.5V to 1.8V
Data “3” ・ ・ ・ Threshold: 2.5V or more and 2.8V or less
During reading, the signals VRFYBAC and VRFYBBC are both at “H” level, and the signals VRFYBA1C and VRFYBB1C are both at “L” level. The voltage Vs is 0V.
[0129]
When the column activation signal CENB input to the column address decoder becomes “H” level, the data held in the data circuit 3 selected by the address signal is output to the data input / output lines IOA, IOB, IOC, and IOD. The data is output to the outside of the EEPROM via the data input / output buffer 4.
[0130]
The relationship among the data stored in the memory cell, the threshold value, and the level output after reading to the data input / output lines IOA, IOB, IOC, and IOD is as shown in FIG.
[0131]
Output data to the outside of the chip may be data converted based on signals output to the data input lines IOA, IOB, IOC, and IOD by the data input / output buffer 4.
[0132]
<Write operation>
First, write data is loaded into the flip-flops FF1 and FF2. Thereafter, “1” data, “2” data, and “3” data are written almost simultaneously. Then, verify read is performed to check whether “1” data, “2” data, and “3” data are sufficiently written. If there is an insufficiently written memory cell, rewrite is performed. Writing is completed when the writing end detection circuit detects that all the memory cells are sufficiently written.
[0133]
In the following, first, the program will be described, and then verify read will be described.
[0134]
(1) Program
Before the write operation, the input 2-bit data is converted by the data input / output buffer 4 and input to the data circuit 3. The relationship between the quaternary data and the data input / output lines IOA, IOB, IOC, and IOD is as shown in FIG.
[0135]
The converted quaternary data is transferred to the data circuit 3 at the column address designated by the address signal when the column activation signal CENB is at “H” level.
[0136]
FIG. 25 is a timing chart during the write operation. Hereinafter, the write operation will be described with reference to FIG.
[0137]
As shown in FIG. 25, first, at time t1S, the voltage VA becomes the bit line write control voltage 1V, and the bit line BLa is set to 1V. When a voltage drop corresponding to the threshold value of n channel MOS transistor Qn39 becomes a problem, signal BLCA may be boosted. Subsequently, the signal PREA becomes “L” level, and the bit line BLa is floated.
[0138]
Next, at time t2S, the signal RV2A is set to 1.5V. As a result, the bit line control voltage 0V is applied to the bit line BLa from the data circuit holding the data “1” or “3”. Assuming that the threshold value of the n-channel MOS transistor Qn32 is 1V, the n-channel MOS transistor Qn32 is “OFF” when “0” or “2” is written, and “ON” when “1” or “3” is written.
[0139]
Thereafter, at time t3S, the signal VRFYBAC becomes 0 V, and the bit line write control voltage VCC is output to the bit line BLa from the data circuit in which the data “0” or the data “1” is held.
[0140]
Then, at time t4S, the signal VRFYBA2C becomes 0V, and the bit line “1” write potential 2V is output to the bit line BLa via the terminal V1 from the data circuit holding the data “1”.
[0141]
As a result, the bit line for writing "0" is VCC, the bit line for writing "1" is 2V, the bit line for writing "2" is 1V, and the bit line for writing "3" is 0V. At times t1S to t4S, the control gate / selection gate drive circuit 2 selects the selection gate SG1A and control gates CG1A to CG4A of the block selected as VCC. The selection gate SG2A is 0V.
[0142]
Next, at time t5s, the selected control gate CG2A becomes the high voltage VPP (for example, 20V), and the non-selected control gates CG1A, CG3A, and CG4A become the voltage VM (for example, 10V). In the memory cell corresponding to the data circuit holding data “3”, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and the VPP of the control gate, and the threshold value of the memory cell rises. In the memory cell corresponding to the data circuit holding the data “2”, electrons are injected into the floating gate due to the potential difference between the channel potential of 1 V and the VPP of the control gate, and the threshold value of the memory cell rises. In the memory cell corresponding to the data circuit holding data “1”, electrons are injected into the floating gate due to the potential difference between the channel potential of 2V and the VPP of the control gate, and the threshold value of the memory cell rises. The channel potential for “2” writing is set to 1 V, and the channel potential for “1” writing is set to 2 V. The electron injection amount is “3” data writing, “2” writing, “ This is to reduce the order in the case of 1 "writing. In the memory cell corresponding to the data circuit holding data “0”, the potential difference between the channel potential and the VPP of the control gate is small, so that electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change. During the write operation, the signals SAN1, SAN2, PREB, and BLCB are at “H” level, the signals SAP1, SAP2, VRFYBA1C, RV1A, RV1B, RV2B, ECH1, and ECH2 are at “L” level, and the voltage VB is 0V.
[0143]
(2) Verify read
After the write operation, it is detected whether the write has been sufficiently performed (write verify). If the desired threshold value is reached, the data in the data circuit is changed to “0”. If the desired threshold value has not been reached, the data in the data circuit is retained and the write operation is performed again. The write operation and the write verify are repeated until all the “1” -written memory cells, the “2” -written memory cells, and the “3” -written memory cells reach a desired threshold value.
[0144]
FIG. 26 and FIG. 27 are timing charts during the write verify operation. FIG. 26 and FIG. 27 are drawings that are temporally continuous. The numbers 1 to 32 attached to the end of the signal waveform on the right side of FIG. 26 are connected to the numbers 1 to 32 attached to the end of the signal waveform on the left side of FIG. Show. The write verify operation will be described below with reference to FIGS. 26 and 27.
[0145]
First, it is detected whether the memory cell to which “1” is written has reached a predetermined threshold value.
[0146]
As shown in FIG. 26, at time t1YC, the voltages VA and VB are 1.8V and 1.5V, respectively, and the bit lines BLa and BLb are 1.8V and 1.5V, respectively. Further, the signals BLCA and BLCB become “L” level, the bit line BLa and the MOS capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are disconnected, and the bit lines BLa and BLb are in a floating state. Further, the signals PREA and PREB are respectively set to the “L” level, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state.
[0147]
Subsequently, at time t2YC, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 is 0.5V, the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are at VCC. Is done. If the threshold value of the selected memory cell is 0.5V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 0.5V or higher, the bit line voltage remains 1.8V.
[0148]
Thereafter, at time t3YC, the signals BLCA and BLCB are set to the “H” level, respectively, and the potential of the bit line is transferred to the nodes N1 and N2. Thereafter, the signals BLCA and BLCB become “L” level, respectively, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected.
[0149]
Thereafter, at time t4YC, the signal RV1A becomes 1.5V, and in the case of “2” writing and “3” writing, the node N1 is discharged to 0V.
[0150]
Subsequently, when the signal VRFYBA1C becomes “H” level at time t5YC, in the data circuit holding “0” or “2” write data, the n-channel MOS transistor Qn2 is “ON” and the node N1 is VCC. As a result, the node N1 becomes VCC when “0” or “2” is written, and becomes 0 V when “3” is written. Thereafter, the signals SAN2 and SAP2 become “L” level and “H” level, respectively, the flip-flop FF2 is inactivated, the signal ECH2 becomes “H”, and two inputs of the flip-flop FF2 are input. Output terminals (nodes N5C and N6C) are equalized with each other. Thereafter, the signals RV2A and RV2B are set to the “H” level.
[0151]
Thereafter, at time t6YC, the signals SAN2 and SAP2 are again set to the “H” level and the “L” level, respectively, so that the voltage at the node N1 is sensed and latched. As a result, only the data circuit holding the “1” write data detects whether or not the data in the corresponding memory cell is sufficiently in the “1” write state. If the data in the memory cell is “1”, the write data is changed to “0” by sensing and latching the voltage of the node N1 by the flip-flop FF2. On the other hand, if the data in the memory cell is not “1”, the voltage of the node N2 is sensed by the flip-flop FF1 and latched to hold the write data at “1”. Write data of the data circuit holding “0”, “2” or “3” write data is not changed. The selected control gate is set to 1.5V. If the threshold value of the selected memory cell is 1.5V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 1.5V or higher, the bit line voltage remains 1.8V.
[0152]
Subsequently, at time t7YC, the signals PREA and PREB become VCC, and the nodes N1 and N2 become 1.8V and 1.5V, respectively, and then float.
[0153]
Thereafter, as shown in FIG. 27, at time t8YC, the signals BLCA and BLCB are set to the “H” level, respectively, and the potentials of the bit lines are transferred to N1 and N2. Thereafter, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected.
[0154]
Thereafter, at time t9YC, the signal RV2A is set to 1.5 V, for example, equal to or lower than VCC. When the threshold value of n-channel MOS transistor Qn32 is 1V, in the data circuit holding “3” write data, n-channel MOS transistor Qn32 is “ON” and node N1 is 0V. In the data circuit in which “2” write data is held and the memory cell is sufficiently written “2”, the n-channel MOS transistor Qn32 is “OFF” and the node N1 is kept at 1.5V or higher. Be drunk. When “2” writing is insufficient, the node N1 is 1.5V or less.
[0155]
Thereafter, when the signal VRFYBAC becomes “L” level at time t10YC, in the data circuit in which “0” or “1” write data is held, the p-channel MOS transistor Qp13C is “ON”, and the node N1 is set to VCC. It becomes. Further, the signals SAN1 and SAP1 become “L” level and “H” level, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” level, so that two inputs of the flip-flop FF1 are input. Output terminals (nodes N3C and N4C) are equalized with each other. Thereafter, the signals RV1A and RV1B are set to the “H” level.
[0156]
Thereafter, at time t11YC, the signals SAN1 and SAP1 are again set to the “H” level and the “L” level, respectively, so that the voltage at the node N1 is sensed and latched. As a result, only the data circuit holding the “2” write data detects whether or not the data in the corresponding memory cell is sufficiently in the “2” write state. If the data in the memory cell is “2”, the write data is changed to “0” by sensing and latching the voltage of the node N1 by the flip-flop FF1. On the other hand, if the memory cell data is not “2”, the flip-flop FF1 senses and latches the voltage at the node N1, and the write data is held at “2”. The write data of the data circuit holding “0”, “1” or “3” write data is not changed. The selected control gate is set to 2.5V. If the threshold value of the selected memory cell is 2.5V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 2.5V or more, the bit line voltage remains 1.8V.
[0157]
Thereafter, at time t12YC, the signals BLCA and BLCB are set to the “H” level, and the potentials of the bit lines are transferred to N1 and N2. Thereafter, the signals BLCA and BLCB again become “L” level, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected.
[0158]
Thereafter, when the signal VRFYBAC becomes “L” level at time t13YC, the data circuit in which “0” or “1” write data is held and the data circuit in which “2” write is sufficiently performed The channel MOS transistor Qp13C is “ON”, and the node N1 becomes VCC. Further, the signals SAN1 and SAP1 become “L” level and “H” level, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” level, so that two inputs of the flip-flop FF1 are input. Output terminals (nodes N3C and N4C) are equalized with each other. Thereafter, the signals RV1A and RV1B are set to the “H” level.
[0159]
Thereafter, at time t14YC, the signals SAN1 and SAP1 become “H” level and “L” level, respectively, so that the voltage of the node N1 is sensed and latched. Thereafter, as shown in FIG. 27, the conversion of the write data as described above is further performed.
[0160]
Next, at time t15YC, the signals BLCA and BLCB are set to the “H” level, and the potentials of the bit lines are transferred to N1 and N2. Thereafter, the signals BLCA and BLCB again become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected.
[0161]
Thereafter, when the signal VRFYBA1C becomes “H” level at time t16YC, the n-channel MOS transistor Qn2C is used in the data circuit holding “0” or “2” write data and the data circuit sufficient for “1” write. Is turned ON, and the node N1 becomes VCC. Further, the signals SAN2 and SAP2 become “L” level and “H” level, respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes “H” level, so that two inputs of the flip-flop FF2 are input. Output terminals (nodes N5C and N6C) are equalized with each other. Thereafter, the signals RV2A and RV2B are set to the “H” level.
[0162]
Thereafter, at time t17YC, the signals SAN2 and SAP2 are set to the “H” level and the “L” level, respectively, so that the voltage at the node N1 is sensed and latched.
[0163]
In this embodiment, by setting the signal VRFYBA1C to VCC at time t16YC, the node N1 of the MOS capacitor Qd1 when “0” writing and “2” writing are performed from the potential (1.5 V) of the node N2. The battery is charged to be higher. At time t16YC, the signal RV2B may be set to 1.5 V, for example. In this case, in the case of writing “0” or “2”, since the node N6C is 0V, the n-channel MOS transistor Qn33 is turned on, and the node N2 becomes 0V. On the other hand, in the case of writing “1” or “3”, since the node N6C is VCC and the node N2 is 1.5V, the n-channel MOS transistor Qn33 is turned off and the node N2 is kept at 1.5V. At time t16YC, when the signal VRFYBA1C is set to VCC and “0” writing and “2” writing are performed, charging to the node N1 only needs to be larger than the potential of the node N2 (0V). The charging may be a low voltage of about 0.5V, for example.
[0164]
As described above, only the data circuit holding “3” write data detects whether or not the data in the corresponding memory cell is sufficiently in the “3” write state. If the data in the memory cell is “3”, the write data is changed to “0” by sensing and latching the voltage at the node N1 by the flip-flops FF1 and FF2. If the data in the memory cell is not “3”, the voltage of the node N1 is sensed and latched by the flip-flops FF1 and FF2, and the write data is held at “3”. The write data of the data circuit holding “0”, “1” or “2” write data is not changed.
[0165]
During the write verification, the signal VRFYBBC is “H”, the signal VRFYBB1C is “L”, and the voltage Vs is 0V.
[0166]
If all of the selected memory cells have reached the desired threshold value, the data in the data circuit becomes “0” data. That is, when the writing is completed, the nodes N4C and N6C become “L” level. By detecting this, it can be determined whether or not all of the selected memory cells have reached a desired threshold value. For example, the write end detection may be performed using the write end batch detection transistor Qn5C having a gate connected to the node N4C and the write end batch detection transistor Qn6C having a gate connected to the node N6C, as shown in FIG.
[0167]
After the verify read, first, the terminal VRTC is precharged to, for example, VCC. If even one memory cell is insufficiently written, at least one of the node N4C or N6C of the data circuit is at “H” level, so that at least one of the n-channel MOS transistors Qn5C and Qn6C is turned on, and the terminal VRTC The potential drops from the precharge potential. When all the memory cells are sufficiently written, the nodes N4C and N6C of the data circuits 3-0, 3-1,..., 3-m-1, 3-m become “L” level. As a result, n channel MOS transistors Qn5C and Qn6C in all data circuits are turned off, so that the potential of terminal VRTC maintains the precharge potential.
[0168]
[2] When operating as a binary memory cell
Write and read procedures when the memory cell operates as a binary cell will be described below. A circuit for controlling read / write data is the circuit shown in FIG. 20 as in the case of operating as a quaternary cell.
[0169]
<Write operation>
(1) Program
Prior to the write operation, the input data is input to the data circuit 3 via the data input / output buffer 4. Data is input to the flip-flop FF1 via IOA and IOB when the column activation signal CENB is at "H" level.
[0170]
FIG. 28 shows the relationship between the threshold voltage of the memory cell M and the two write states (binary data “0” and “1”) when binary storage is performed by creating two write states in the memory cell M. FIG. FIG. 29 is a diagram showing the relationship between the write data and the nodes N3C and N4C of the flip-flop FF1. FIG. 30 is a timing chart during the write operation. Hereinafter, the write operation will be described with reference to FIG.
[0171]
As shown in FIG. 30, first, at time t1S, the signal VRFYBAC becomes 0V, and the bit line write control voltage VCC is output to the bit line BLa from the data circuit holding the data “0”.
[0172]
After that, at time t2S, the signal RV1A becomes VCC, so that the voltage 0V is output to the bit line from the data circuit holding the data “1”.
[0173]
As a result, the bit line for writing “0” becomes VCC and the bit line for writing “1” becomes 0V. At time t1S, the control gate / selection gate drive circuit 2 sets the selection gate SG1A and control gates CG1A to CG4A of the selected block to VCC. The selection gate SG2A is 0V.
[0174]
Next, at time t3S, the selected control gate CG2A becomes the high voltage VPP (for example, 20V), and the non-selected control gates CG1A, CG3A, and CG4A become the voltage VM (for example, 10V). In the memory cell corresponding to the data circuit holding data “1”, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and the VPP of the control gate, and the threshold value of the memory cell increases. In the memory cell corresponding to the data circuit holding the data “0”, the selection gate SG1A is turned off, so that the channel of the memory cell becomes floating. As a result, the channel of the memory cell becomes about 8V due to capacitive coupling with the control gate. In the memory cell to which data “0” is written, the channel is 8V and the control gate is 20V. Therefore, electrons are not injected into the memory cell and the erased state (“0”) is maintained. During the write operation, the signals SAN1, SAN2, PREB, BLCB, and VRFYBA2C are at “H” level, the signals SAP1, SAP2, VRFYBA1C, RV1B, RV2B, ECH1, and ECH2 are at “L” level, and the voltage VB is 0V.
[0175]
(2) Verify read
After the write operation, it is detected whether the write has been sufficiently performed (write verify). If the desired threshold value is reached, the data in the data circuit is changed to “0”. If the desired threshold value has not been reached, the data in the data circuit is retained and the write operation is performed again. The write operation and the write verify are repeated until all memory cells to which “1” is written reach a desired threshold value.
[0176]
FIG. 31 is a timing chart during the write verify operation.
[0177]
Hereinafter, the write verify operation will be described with reference to the circuit diagram shown in FIG. 20 and the timing diagram shown in FIG.
[0178]
As shown in FIG. 31, first, at time t1YC, the voltages VA and VB become 1.8V and 1.5V, respectively, and the bit lines BLa and BLb become 1.8V and 1.5V, respectively. Further, the signals BLCA and BLCB become “L” level, the bit line BLa and the MOS capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are disconnected, and the bit lines BLa and BLb are in a floating state. Further, the signals PREA and PREB are respectively set to the “L” level, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state.
[0179]
Subsequently, at time t2YC, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 is 0.5V, the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are at VCC. Is done. If the threshold value of the selected memory cell is 0.5V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 0.5V or higher, the bit line voltage remains 1.8V.
[0180]
Thereafter, at time t3YC, the signals BLCA and BLCB are set to the “H” level, respectively, and the potential of the bit line is transferred to the nodes N1 and N2. Thereafter, the signals BLCA and BLCB become “L” level, respectively, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected.
[0181]
Thereafter, when the signal VRFYBAC becomes “L” at time t4YC, in the data circuit holding “0” write data, the p-channel MOS transistor Qp12C is “ON”, and the node N1 becomes VCC. As a result, the node N1 becomes VCC when “0” is written. In the case of writing “1”, the p-channel MOS transistor Qp12C is “OFF”. That is, N1 becomes VCC when “1” writing is sufficiently performed, and N1 becomes 0 V when “1” writing is insufficient. Thereafter, the signals SAN1 and SAP1 become “L” and “H”, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H”, so that two input / output terminals (nodes) of the flip-flop FF1 N3C, N4C) are equalized with each other. Thereafter, the signals RV1A and RV1B become “H”.
[0182]
Thereafter, at time t5YC, the signals SAN1 and SAP1 are again set to the “H” level and the “L” level, respectively, so that the voltage at the node N1 is sensed and latched. As a result, only the data circuit holding the “1” write data detects whether or not the data in the corresponding memory cell is sufficiently in the “1” write state. If the data in the memory cell is “1”, the write data is changed to “0” by sensing and latching the voltage of the node N1 by the flip-flop FF1. Conversely, if the data in the memory cell is not “1”, the flip-flop FF1 senses and latches the voltage at the node N1, and the write data is held at “1”. The write data of the data circuit holding “0” write data is not changed.
[0183]
If all of the selected memory cells have reached the desired threshold value, the node N4C of the data circuit becomes “L”. By detecting this, it can be determined whether or not all selected memory cells have reached a desired threshold value. For example, the write end detection may be performed by using a write end batch detection transistor Qn5C having a gate connected to the node N4C shown in FIG.
[0184]
After the verify read, first, the terminal VRTC is precharged to, for example, VCC. If even one memory cell is insufficiently written, since the node N4C of the data circuit is “H”, the n-channel MOS transistor Qn5C is turned on, and the potential of the terminal VRTC is lowered from the precharge potential. When all the memory cells are sufficiently written, the nodes N4C of the data circuits 3-0, 3-1,..., 3-m-1, 3-m all become “L” level. As a result, the n-channel MOS transistors Qn5C in all the data circuits are turned off, so that the potential of the terminal VRTC maintains the precharge potential and the end of writing is detected.
[0185]
<Read operation>
In the read operation, “0” or “1” is read.
[0186]
FIG. 32 is a timing chart during the read operation. The read operation will be described below with reference to FIG.
[0187]
As shown in FIG. 32, first, at time t1RD, the voltages VA and VB become 1.8V and 1.5V, respectively, and the potentials of the bit lines BLa and BLb become 1.8V and 1.5V, respectively. Further, the signals BLCA and BLCB become “L” level, the bit line BLa and the MOS capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are disconnected, and the bit lines BLa and BLb are in a floating state. Further, the signals PREA and PREB are respectively set to the “L” level, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state.
[0188]
Subsequently, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 is set to 0V, and the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are set to VCC. If the threshold value of the selected memory cell is 0V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 0V or higher, the bit line voltage remains 1.8V.
[0189]
Thereafter, at time t2RD, the signals BLCA and BLCB become “H” level, respectively, and the bit line data is transferred to the MOS capacitors Qd1 and Qd2. Thereafter, the signals BLCA and BLCB again become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Further, the signals SAN1 and SAP1 become “L” level and “H” level, respectively, so that the flip-flop FF1 is deactivated, and the signal ECH1 becomes “H”, so that two inputs / outputs of the flip-flop FF1 Terminals (nodes N3C and N4C) are equalized with each other. Further, thereafter, the signals RV1A and RV1B are set to the “H” level.
[0190]
Subsequently, at time t3RD, the signals SAN1 and SAP1 are again set to the “H” level and the “L” level, respectively, so that the voltage at the node N1 is sensed by the flip-flop FF1 and then to the flip-flop FF1. Latched. Thereby, “whether the data of the memory cell is“ 0 ”or“ 1 ”” is sensed by the flip-flop FF1, and the information is latched.
[0191]
Next explained is a storage system according to the fifth embodiment of the invention.
[0192]
In the storage system described in the first to fourth embodiments, the performance of the memory cell (what value memory cell is used) is monitored, the number of times the memory cell is rewritten, or the usage time of the memory cell is monitored. It was judged by doing. However, the monitoring method is not limited to the above method.
[0193]
In the storage system according to the fifth embodiment, there is provided a storage system including a new monitoring method and a new monitoring method that are particularly effective in determining the performance switching of the memory cell.
[0194]
FIG. 33 is a diagram showing an operation flow of the first storage system according to the fifth embodiment.
[0195]
As shown in FIG. 33, the first storage system monitors the number of write verifications, that is, the number of write / verify read cycles. Of course, the number of erase verifications may be monitored without being limited to the number of write verifications.
[0196]
That is, in the NAND type EEPROM, verify read is performed to check whether writing or erasing is sufficiently performed after applying a program pulse in writing and erasing. When there is a memory cell that is insufficiently written or erased, rewriting and reerasing are performed. Here, at the beginning of use, it is assumed that the memory cell has been sufficiently written by, for example, three write / verify read cycles. On the other hand, as the number of rewrites increases, electrons are trapped in the tunnel oxide film of the memory cell, and writing becomes difficult. As a result, for example, the number of write / verify read cycles increases to four times, five times, and six times. Therefore, for example, as shown in FIG. 1, the write / verify read cycle is operated as a quaternary memory cell up to a predetermined number of times (for example, 5 times), and as a ternary memory cell at the time of writing after the predetermined number of times. It only has to be operated. Even when operated as a ternary memory cell, the number of write / verify / read cycles increases as the number of rewrites increases, so that the predetermined number of times (for example, 7 times, 5 times, or 4 times) is reached. By the way, at the time of subsequent writing, it may be operated as a binary memory cell. Similarly, when the number of write / verify / read cycles of the binary memory cell reaches a predetermined number, the memory cell may not be used thereafter, or the program / erase will not be performed thereafter. May be.
[0197]
Thus, the number of write / verify read cycles can be detected, and the degree of deterioration of the memory cell can be grasped from the detection result. Therefore, by determining whether the number of write / verify read cycles has reached a predetermined number, the number of pieces of information stored in the memory cell can be changed as in the first to fourth embodiments. it can. Such a monitoring method can be used for the storage system described in the first to fourth embodiments or the multi-value storage flash memory.
[0198]
For example, the memory cell may first be used as a quaternary memory cell and used as a binary cell after the number of write / verify read cycles reaches a predetermined number of cycles.
[0199]
In addition, the novel monitoring method included in the storage system according to the fifth embodiment is effective not only in multilevel memory cells but also in binary memory cells.
[0200]
FIG. 34 is a diagram showing an operation flow of the second storage system according to the fifth embodiment.
[0201]
As shown in FIG. 34, the number of write / verify read cycles is used as a binary memory cell until a predetermined number of times, and the memory cell is not used after the predetermined number of times is exceeded. Alternatively, the memory cell may not be written or erased after a predetermined number of times has been exceeded.
[0202]
In the NAND type EEPROM, for example, one block is formed by 16 pages. By detecting the number of write / verify / read cycles for each page, the value of the memory cell to be operated can be determined for each page. You can decide.
[0203]
The value of the memory cell to be operated may be determined for each block or for each chip. In other words, if the number of write / verify read cycles that operate as a quaternary memory cell in one page out of 16 pages constituting a block exceeds a predetermined number, the memory of the block that includes this page For example, the cell may be operated as a binary cell in the subsequent writing. Of course, if the number of write / verify / read cycles to be operated as a quaternary memory cell exceeds a predetermined number even in one page among a plurality of pages constituting the chip, the page of the chip including this page is included. All memory cells may be operated as, for example, binary cells in the subsequent writing.
[0204]
Furthermore, it is possible to determine the value of the memory cell to be operated in units of memory cell blocks obtained by subdividing the page, and the operation mode is different within the page as long as the operation can be controlled. There may be memory cells. That is, the unit for changing the number of pieces of information stored in the memory cell is not particularly limited, and various modifications are possible in addition to the page unit, block unit, and chip unit as described above.
[0205]
Further, the number of information values stored in the memory cell may be changed by detecting not the number of write / verify read cycles but the number of erase / verify read cycles.
[0206]
Further, the number of write / verify read cycles or the number of erase / verify read cycles may be stored or counted in a counter circuit provided in the chip, and information of the counter circuit may be output to the chip.
[0207]
FIG. 35 is a diagram showing an operation flow of the third storage system according to the fifth embodiment.
[0208]
As shown in FIG. 35, the write (or erase) voltage may be changed by detecting the number of write / verify read cycles (or the number of erase / verify read cycles). For example, taking a binary memory cell as an example, the initial value of the write voltage is 16 V until the number of cycles reaches four. As the number of rewrites increases, the number of cycles increases because writing and erasure become difficult. When the number of cycles exceeds 4, the initial value of the write voltage is set to 17V. If the number of rewrites further increases and the initial value of the write voltage is 17V and the number of cycles exceeds four, the initial value of the write voltage may be increased to 18V.
[0209]
If the number of cycles exceeds a predetermined number, not only the write voltage but also the initial value of the erase voltage may be increased. Of course, the erase voltage or the write voltage may be changed by detecting the number of erase / verify read cycles.
[0210]
As described above, monitoring the number of write / verify read cycles or the number of erase / verify read cycles not only determines the value of the memory cell to be operated, but also monitors the number of rewrites. It is very effective in widely determining the performance of memory cells.
[0211]
As described above, in the first to fifth embodiments described above, in a storage system using a multilevel semiconductor memory device, the number of information (values) stored in one memory cell is reduced as the number of rewrites increases. For example, a quaternary memory cell operates as a quaternary memory cell up to 500,000 rewrites, and thereafter operates as a binary memory cell. Thereby, the number of rewrites of the entire storage system can be increased more than before.
[0212]
The present invention can be applied not only to NAND type EEPROMs and NOR type flash memories, but also to AND type (K. Kume et al .; IEDM Tech. Dig., Dec. 1992, pp.991-993) , DINOR type (S. Kobayashi et al .; ISSCC Tech. Dig., 1995, pp. 122) and virtual ground type array (R. Cemea et al .; ISSCC Tech. Dig., 1995, pp. 126) Good.
[0213]
Of course, a multi-level DRAM, a multi-level mask ROM, or a multi-level SRAM may be used.
[0214]
The present invention can be applied not only to ternary memory cells or quaternary memory cells, but also to quinary memory cells, octane memory cells, or 16 value memory cells.
[0215]
【The invention's effect】
As described above, according to the present invention, a memory system that includes a multi-level memory cell and has a particularly high durability regarding rewriting, and a novel system element that is particularly necessary for the memory system are included. A storage system can be provided.
[Brief description of the drawings]
FIG. 1 is a diagram showing a relationship between a threshold voltage and quaternary data in a multi-level NAND flash memory according to a first embodiment of the present invention.
FIGS. 2A, 2B, and 2C show the relationship between the threshold voltage and the ternary data of the multi-level NAND flash memory according to the first embodiment of the present invention, respectively. Figure.
FIGS. 3A and 3B are diagrams showing the relationship between the threshold voltage and binary data of the multi-level NAND flash memory according to the first embodiment of the present invention.
FIG. 4 is a block diagram of a flash memory according to a second embodiment of the present invention.
FIG. 5 is a block diagram of the flash memory chip shown in FIG. 4;
FIG. 6 is a configuration diagram of a storage system according to a modification of the second embodiment of the present invention.
FIG. 7 is a diagram showing an operation flow of the first storage system according to the third embodiment of the invention;
FIG. 8 is a diagram showing an operation flow of the second storage system according to the third embodiment of the invention;
FIG. 9 is a diagram showing an operation flow of a third storage system according to the third embodiment of the present invention;
FIG. 10 is a diagram showing an operation flow of a seventh storage system according to the third embodiment of the invention;
FIG. 11 is a diagram showing an operation flow of an eighth storage system according to the third embodiment of the invention;
FIG. 12 is a view showing an operation flow of a ninth storage system according to the third embodiment of the invention;
FIG. 13 is a view showing an operation flow of a tenth storage system according to the third embodiment of the invention;
FIG. 14 is a diagram showing an operation flow of an eleventh storage system according to the third embodiment of the invention;
FIG. 15 is a view showing an operation flow of a twelfth storage system according to the third embodiment of the invention;
FIG. 16 is a view showing an operation flow of a thirteenth storage system according to the third embodiment of the invention;
FIG. 17 is a configuration diagram showing a configuration of a multi-value storage type EEPROM according to a fourth embodiment of the present invention;
FIG. 18 is a configuration diagram showing a configuration of a memory cell array and a data circuit shown in FIG. 17;
FIG. 19 is a diagram showing a relationship between threshold voltage and quaternary data of a multi-value storage type EEPROM according to a fourth embodiment of the present invention;
20 is a circuit diagram of the memory cell array and data circuit shown in FIG. 17;
FIG. 21 is a timing chart during a read operation.
FIG. 22 is a diagram showing a relationship between a potential of a flip-flop node and quaternary data;
FIG. 23 is a diagram showing the relationship between the potential of a flip-flop node and quaternary data.
FIG. 24 is a diagram showing the relationship between the potential of a flip-flop node and quaternary data.
FIG. 25 is a timing chart during a write operation.
FIG. 26 is a timing chart during a write verify operation.
FIG. 27 is a timing chart during a write verify operation.
FIG. 28 is a diagram showing the relationship between the threshold voltage and binary data of a multi-value storage type EEPROM according to the fourth embodiment of the present invention;
FIG. 29 is a diagram showing a relationship between a potential of a flip-flop node and binary data;
FIG. 30 is a timing chart during a write operation.
FIG. 31 is a timing chart during a write verify operation;
FIG. 32 is a timing chart during a read operation.
FIG. 33 is a view showing an operation flow of the first storage system according to the fifth embodiment of the invention;
FIG. 34 is a view showing an operation flow of a second storage system according to the fifth embodiment of the invention;
FIG. 35 is a view showing an operation flow of a third storage system according to the fifth embodiment of the invention;
36A and 36B are diagrams showing a NAND cell portion of a memory cell array, in which FIG. 36A is a plan view and FIG. 36B is an equivalent circuit diagram;
37 is a cross-sectional view, and FIG. 37 (a) is a cross-sectional view taken along line AA ′ in FIG. 36 (a), and FIG. 37 (b) is a cross-sectional view taken along line BB ′ in FIG. 36 (a). Sectional drawing.
FIG. 38 is an equivalent circuit diagram of a memory cell array in which NAND cells are arranged in a matrix.
FIG. 39 is a diagram showing a relationship between a threshold voltage of a memory cell and quaternary data.
[Explanation of symbols]
1 ... Memory cell array,
2 ... Control gate / selection gate drive circuit,
3 ... Data circuit,
4 ... Data input / output buffer,
5 ... Address buffer,
6 ... Data control circuit,
M ... Memory cell,
S ... selection transistor,
SG ... selection gate,
CG ... Control gate,
BL: Bit line,
Qn: n-channel MOS transistor,
Qp ... p-channel MOS transistor,
Qd: Depletion type n-channel MOS transistor,
FF ... flip-flop,
I: Inverter,
G: NAND logic circuit.

Claims (16)

A plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewritable;
A control circuit for controlling the plurality of memory cells,
The control circuit controls a part of the plurality of memory cells as the n-value storage part, and stores a part of the different memory cells as m-value (m is a natural number of 2 or more, m <n). And further storing control information as to which memory cell is to be controlled as an m-value storage part in a part of different memory cells. A plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewritable;
A control circuit for controlling the plurality of memory cells,
The control circuit controls a part of the plurality of memory cells as the n-value storage part, and stores a part of the different memory cells as m-value (m is a natural number of 2 or more, m <n). Control information indicating which memory cell is to be controlled as an m-value storage part in some different memory cells, and rewriting the control information changes the memory cell to store the m-value. A storage system characterized by that. A plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewritable;
A control circuit for controlling the plurality of memory cells,
The control circuit controls a part of the plurality of memory cells as the storage part of the n value, and stores a part of the different memory cells in the m value (m is a natural number of 2 or more, m <n). And further storing control information as to which memory cells are controlled as n-value storage portions in some different memory cells. A plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewritable;
A control circuit for controlling the plurality of memory cells,
The control circuit controls a part of the plurality of memory cells as the storage part of the n value, and stores a part of the different memory cells in the m value (m is a natural number of 2 or more, m <n). Control information indicating which memory cell is to be controlled as an n-value storage part is stored in a part of different memory cells, and the memory cell in which the n value is stored is changed by rewriting the control information. A storage system characterized by that. Further comprising a DRAM, read the control information after the power is turned on from the memory cell, the storage system according to any one of claims 1 to claim 4, characterized in that storing in the DRAM.   5. The memory cell according to claim 1, wherein each of the plurality of memory cells is divided into a plurality of predetermined blocks, and an n-value storage portion or an m-value storage portion is controlled in units of blocks. The storage system according to item.   The storage system according to claim 6, wherein the control information is stored in a predetermined block.   5. The storage system according to claim 1, wherein the control information includes the number of rewrites of a memory cell. A memory cell array composed of a plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewriting;
A control circuit for controlling the plurality of memory cells,
The control circuit controls a part of the memory cell array as a storage part of the n value, and a different part of the memory cell array as a storage part of an m value (m is a natural number of 2 or more, m <n). And a control system for storing control information indicating which part of the memory cell array is to be controlled as an m-value storage part in a different part of the memory cell array. A memory cell array composed of a plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewriting;
A control circuit for controlling the plurality of memory cells,
The control circuit controls a part of the memory cell array as a storage part of the n value, and a different part of the memory cell array as a storage part of an m value (m is a natural number of 2 or more, m <n). A memory cell array that stores control information on which part of the memory cell array is controlled as an m-value storage part in a different part of the memory cell array, and stores the m value by rewriting the control information. A storage system characterized by changing. A memory cell array composed of a plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewriting;
A control circuit for controlling the plurality of memory cells,
The control circuit controls a part of the memory cell array as a storage part of the n value, and a different part of the memory cell array as a storage part of an m value (m is a natural number of 2 or more, m <n). And a control system for storing control information indicating which part of the memory cell array is controlled as an n-value storage part in a different part of the memory cell array. A memory cell array composed of a plurality of nonvolatile semiconductor memory cells capable of storing a plurality of n values (n is a natural number of 3 or more) and electrically rewriting;
A control circuit for controlling the plurality of memory cells,
The control circuit controls a part of the memory cell array as a storage part of the n value, and a different part of the memory cell array as a storage part of m value (m is a natural number of 2 or more, m <n). A memory cell array that stores control information that controls which part of the memory cell array is controlled as a storage part of an n value in a different part of the memory cell array, and stores the n value by rewriting the control information A storage system characterized by changing. Further comprising a DRAM, read the control information after the power is turned on from the memory cell array, storage system as claimed in any one claims 9 to 12, characterized in that storing in the DRAM.   13. The memory cell array is divided into a plurality of blocks each including a predetermined number of memory cells, and an n-value storage portion or an m-value storage portion is controlled in units of blocks. A storage system according to claim 1.   The storage system according to claim 14, wherein the control information is stored in a predetermined block.   The storage system according to any one of claims 9 to 12, wherein the control information includes a number of rewrites of a memory cell.

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