JP2002279788A - Non-volatile semiconductor memory - Google Patents

Abstract

(57) Abstract: The present invention is characterized in that variations in threshold voltage of a memory cell after data writing are reduced. Data is programmed in memory cells in odd-numbered columns and even-numbered columns, and after programming is completed, program verification is sequentially performed on memory cells in odd-numbered columns and even-numbered columns. It is characterized by having a bit line control circuit 22 for performing data reprogramming on the memory cells of the column and repeating the above operation to control data writing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory, and more particularly, to a multi-level NAND cell type EEPROM.
(Multi-level NAND cell type EEPROM), for example, a four-level NAND cell type EEPROM.

[0002]

2. Description of the Related Art One of nonvolatile semiconductor memories is NAND.
Cell-type EEPROMs are known. This NAND cell type EEPROM has a memory cell array composed of a plurality of NAND cell units. As shown in FIG. 3, each NAND cell unit includes a plurality of memory cells M connected in series, and two select transistors SGT1 and SGT2 connected one by one to both ends thereof. Each memory cell M has a control gate and a floating gate, and the control gate gate is connected to any one of the plurality of word lines WL.
One end of the select transistor SGT1 is connected to the bit line BL, and one end of the select transistor SGT2 is connected to, for example, a node of the ground potential. further,
The gate of select transistor SGT1 is commonly connected to select gate line SG1, and select transistor SGT1
The gate of GT2 is commonly connected to a select gate line SG2.

Next, a data write operation (program operation) in the NAND cell type EEPROM will be described. In order to make the following description easy to understand, the preconditions are defined as follows. It is assumed that binary data “0” and “1” are stored in the memory cell, and a state where the threshold voltage of the memory cell is low, for example, a state where the threshold voltage is negative is “0”.
A state where the threshold voltage of the memory cell is high, for example, a state where the threshold voltage is positive is defined as a state “1”.

Normally, in a binary NAND cell type EEPROM, a state where the threshold voltage of a memory cell is low is a state “1”, and a state where the threshold voltage of a memory cell is high is a state “0”. Since the present invention is mainly intended for an n-valued (eg, 4-valued) NAND type EEPROM exceeding 2, taking into account this point, as described above, the state where the threshold voltage of the memory cell is low is set to the “0” state, A state where the threshold voltage of the memory cell is high is defined as a “1” state.

[0005] Regarding the memory cells, the "0" state is an erased state and the "1" state is a written state. The term “write” includes “0” write and “1” write, and “0” write means an erase state (“0” state).
And "1" writing means changing from the "0" state to the "1" state.

The potential of the bit line BL is set to a value corresponding to the write data for the selected memory cell. For example, when the write data is "1" (in the case of "1" write), the potential of the bit line BL is set to the ground potential (0 V) Vss. Set and write data is "0"
In this case (in the case of writing "0"), the power supply potential is set to Vcc.

The potential of the select gate line SG1 is
The power supply potential is set to Vcc, and the potential of the select gate line SG2 on the ground potential side is set to the ground potential (0 V) Vss.

In the case of writing "1", the ground potential (0 V) Vss is transmitted to the channel of the selected memory cell. On the other hand, in the case of writing "0", the potential of the channel of the selected memory cell becomes Vcc-Vthsg (Vthsg is the threshold voltage of the select transistor SGT1). Thereafter, the select transistor SGT1 on the bit line side is cut off, so that the channel of the selected memory cell is set to Vcc.
A floating state is maintained while the potential of -Vthsg is maintained.

Thereafter, a write potential Vpp, for example, about 20 V, is applied to the selected word line, that is, the control gate of the selected memory cell, and the unselected word line, that is, the non-selected memory cell is applied. An intermediate potential Vpass, for example, about 10 V is applied to the control gate.

At this time, the channel potential of the selected memory cell to which "1" is to be written is the ground potential (0 V) Vss, so that "1" is necessary between the floating gate and the channel. High voltage is applied and F
Electrons move from the channel to the floating gate due to the -N tunnel effect. As a result, the threshold voltage of the selected memory cell rises and moves, for example, from negative to positive.

On the other hand, for the selected memory cell to which "0" is to be written, the channel potential is Vcc-Vthsg.
Or Vcc-Vthcell, and the channel is in a floating state. For this reason, when Vpp or Vpass is applied to the word line, the potential of the channel increases due to capacitive coupling between the control gate and the channel. As a result, a high voltage required for writing “1” is not applied between the floating gate and the channel, and the threshold voltage of the selected memory cell maintains the current state, that is, maintains the erased state.

By the way, when data is written, the write voltage and the write time are fixed and all memory cells are written under the same conditions, and it is difficult to keep the threshold voltage range after writing "1" within an allowable range. For example, memory cells have variations in cell characteristics due to variations in the manufacturing process. For this reason, some memory cells are likely to be written and some are not. Paying attention to such a difference in write characteristics, a verify write method has been proposed in which the length of the write time is adjusted and the write is performed while the verify is performed so that the threshold voltage of each memory cell falls within a desired range. I have.

On the other hand, a miniaturized NAND cell type EEP
In a read operation, a read margin is reduced due to the influence of capacitive coupling noise between adjacent bit lines in a read operation, which causes a read operation error.

The above-described bit line shield system has been developed to eliminate the influence of such capacitive coupling noise between adjacent bit lines, and one example thereof is disclosed in, for example, Japanese Patent Application Laid-Open No. 4-276393 by the present applicant. No., published in Japanese Unexamined Patent Publication No. In the case of the bit line shield system, generally, the even columns and the odd columns of the memory cells are treated as different pages.

In recent years, in order to increase the memory capacity of one chip and reduce the cost per bit, a so-called multi-value NAND cell type EEPROM in which information of more than two values is stored in one memory cell. development of,
Practical use is progressing.

In a binary NAND cell type EEPROM, binary (1 bit) data ("0", "1") can be stored in a memory cell, but n (n is a positive integer exceeding 2) The value NAND cell type EEPROM is characterized in that n-value data can be stored in a memory cell.

For example, in a four-level NAND cell type EEPROM, four-level (2-bit) data ("0") is stored in a memory cell.
0 "," 01 "," 10 "," 11 ").
In an n-value NAND cell type EEPROM, a plurality of latch circuits are provided corresponding to one bit line connected to a selected memory cell. That is, when writing or reading the n-value data to or from the selected memory cell, the plurality of latch circuits serve to temporarily store the n-value data.

However, in the above-mentioned multi-value NAND cell type EEPROM employing the bit line shield method, a problem occurs when it is desired to control the distribution of the threshold voltage after writing narrowly.

FIG. 4 is a flowchart showing a conventional write control method in a multilevel NAND cell type EEPROM employing a bit line shield method and a verify write method. According to this method, first, for example, a memory cell in an odd column is programmed.
Thereafter, program verification of the memory cells in the odd columns is performed. Program verify means reading data from a programmed memory cell and verifying whether the threshold voltage after writing is set to a desired value. If the threshold voltage is not set to a desired value, The program is executed again with the conditions changed.
When the threshold voltage is set to a desired value, the memory cells in the even columns are programmed and verified in the same manner as in the odd columns.

FIG. 5 shows an element sectional structure of a memory cell array portion of a NAND cell type EEPROM. The P-type well region 11 is an STI (Shallow Trench Isolation)
Are divided into a plurality of element regions by an element isolation insulating film 12 called “device isolation insulating film 12”. Then, a memory cell is formed in each of these element regions. Each memory cell has an N-channel MO having a so-called stack gate structure in which a control gate 14 is stacked on a floating gate 13.
It is composed of S transistors. Control gate 1
Reference numeral 4 extends in the left-right direction in the figure and is used as a word line. The N-type diffusion regions serving as the source and drain regions of the N-channel MOS transistor are formed on the surface of the P-type well region 11, but are not shown in FIG. Further, a gate insulating film 15 is formed between the P-type well region 11 and the floating gate 13 and between the floating gate 13 and the control gate 14, respectively.

Now, the memory cell M located at the center of FIG.
1 is an odd-numbered column memory cell, and two memory cells M2 and M3 located on both sides thereof are even-numbered column memory cells.

In the method shown in FIG. 4, first, one of the quaternary data is written to the memory cell M1 of the odd column, and then the memory of the even column adjacent to the memory cell M1 of the odd column in the word line direction. Consider a case in which quaternary data having a higher threshold voltage than the memory cell M1 is written to each of the cells M2 and M3. For example, as for the memory cell M1 in the odd-numbered column to be written first, writing is performed so that the threshold voltage moves to the shaded area as shown in FIG. In this writing,
As described above, program verification is performed after programming, and programming and program verification are repeatedly performed as necessary so that reprogramming is performed based on the result. Therefore, after writing, memory cell M1 is programmed. The threshold voltage has risen sufficiently.

After the threshold voltage of the memory cell M1 has risen sufficiently, the memory cells M2 and M3 in the even columns adjacent in the word line direction to the memory cells M1 in the odd columns.
The threshold voltage higher than that of the memory cell M1, for example, FIG.
It is assumed that writing is performed so as to have the highest threshold voltage among the four-value data as shown in FIG. Then, due to the influence of the parasitic capacitance C composed of the floating gate 13 of each memory cell, the element isolation insulating film 12 and the floating gate 13 of another adjacent memory cell shown in FIG. It appears that the threshold voltage of the memory cell M1 in the column has shifted from the original position to a higher direction as shown in FIG.

For this reason, among the memory cells of the odd-numbered column and the even-numbered column, the memory cell to which writing is performed first has a problem that the variation of the threshold voltage is large.

[0025]

As described above, the conventional multi-valued NAND cell type EE employing the bit line shield system is described.
In the PROM, when data is written to the memory cells of the odd and even columns, the threshold voltage of the memory cell to which the writing is performed first among the memory cells of the odd and even columns is performed first. There is a problem that a variation occurs due to the influence of a memory cell which is adjacent to the memory cell in the word line direction and to which writing is performed later.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory capable of preventing a variation in threshold voltage of a memory cell after writing.

[0027]

A nonvolatile semiconductor memory according to the present invention has a word line, a control gate and a floating gate, respectively, and a control gate is commonly connected to the word line, and each of the word lines has one n-value ( n is a positive integer greater than 2) a plurality of memory cells in the odd and even columns for storing data, and the memory cells in the odd and even columns are programmed with data. The program verification of the memory cells of the even columns is sequentially performed, the data is reprogrammed for the memory cells of the odd columns and the even columns in accordance with the verification result, and the above operation is repeated to perform the data write control. And a control circuit for performing the control.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an n-value NAND cell type EEPROM according to an embodiment of the present invention. Figure 1
, 21 is a plurality of NAs similar to the one shown in FIG.
It is a memory cell array composed of ND cell units. A bit line control circuit 22 is provided for performing data write (program), read, rewrite (reprogram), and verify read on the memory cell array 21. The bit line control circuit 22 is connected to the data input / output buffer 23.
The address signal from the address buffer 24 is input to the bit line control circuit 22 via the column decoder 25. Further, a row decoder 26 is provided to control the control gate and select gate lines (both shown in FIG. 3) in the memory cell array 22. This row decoder 26 also has an address buffer 2
4 is input.

The bit line control circuit 22 has a data latch mainly composed of a CMOS flip-flop (FF) and a sense amplifier. The data latch in the bit line control circuit 22 latches write data for writing to a memory cell and latches rewrite data. A sense amplifier in the bit line control circuit 22 performs a sensing operation for detecting a potential of a bit line (shown in FIG. 3),
A sense operation for verify reading after writing is performed.

Next, the n-valued NAN configured as described above
The basic operation of the D-cell EEPROM will be described. Also in this case, to make the following description easier to understand,
It is assumed that binary data “0” and “1” are stored in the memory cell, and a state where the threshold voltage of the memory cell is low, for example, a state where the threshold voltage is negative is set to “0” state, A state where the voltage is high, for example, a state where the threshold voltage is positive is defined as a “1” state.

Normally, in a binary NAND cell type EEPROM, a state where the threshold voltage of a memory cell is low is a state "1", and a state where the threshold voltage of a memory cell is high is a state "0". N-value (eg, 4-value) NA exceeding 2
In consideration of this point, since the ND type EEPROM is targeted, as described above, the state where the threshold voltage of the memory cell is low is set to “0” state, and the state where the threshold voltage of the memory cell is high is set to “1” state. .

Regarding the memory cell, the "0" state is set to the erase state, and the "1" state is set to the write state. The term “write” includes “0” write and “1” write, and “0” write means an erase state (“0” state).
And "1" writing means changing from the "0" state to the "1" state.

[Write operation (Program operation)]
In the write operation, the potential of the bit line BL is a value corresponding to the write data for the selected memory cell connected to the bit line, for example, when the write data is "1"("
In the case of "1" writing, it is set to the ground potential (0 V) Vss, and when the write data is "0" (in the case of "0" writing), it is set to the power supply potential Vcc.

The potential of the select gate line SG1 is
The power supply potential is set to Vcc, and the potential of the select gate line SG2 on the ground potential side is set to the ground potential (0 V) Vss.

In the case of writing "1", the ground potential (0 V) Vss is transmitted to the channel of the selected memory cell. On the other hand, in the case of writing "0", the potential of the channel of the selected memory cell becomes Vcc-Vthsg (Vthsg is the threshold voltage of the select transistor SGT1). Thereafter, the select transistor SGT1 on the bit line side is cut off, so that the channel of the selected memory cell is set to Vcc.
A floating state is maintained while the potential of -Vthsg is maintained.

Note that the selected memory cell is not the memory cell closest to the bit line, and is located on the bit line side of the selected memory cell (the bit line side of the selected memory cell). If the threshold voltage of at least one of the plurality of memory cells is a positive voltage Vthcell, the channel of the selected memory cell maintains the potential of Vcc-Vthcell. In a floating state.

Thereafter, a write potential Vpp, for example, about 20 V is applied to the selected word line, that is, the control gate of the selected memory cell, and the non-selected word line, that is, the non-selected memory cell is applied. An intermediate potential Vpass, for example, about 10 V is applied to the control gate.

At this time, since the channel potential of the selected memory cell to which "1" is to be written is the ground potential (0 V) Vss, it is necessary to write "1" between the floating gate and the channel. High voltage is applied and F
Electrons move from the channel to the floating gate due to the -N tunnel effect. As a result, the threshold voltage of the selected memory cell rises and moves, for example, from negative to positive.

On the other hand, for the selected memory cell to which "0" is to be written, the channel potential is Vcc-Vthsg.
Or Vcc-Vthcell, and the channel is in a floating state. For this reason, when Vpp or Vpass is applied to the word line, the potential of the channel increases due to capacitive coupling between the control gate and the channel. As a result, a high voltage required for writing “1” is not applied between the floating gate and the channel, and the threshold voltage of the selected memory cell maintains the current state, that is, maintains the erased state.

[Erase operation] Data erasing is performed by setting all word lines (control gates) to 0V.
After setting the select gate lines SG1 and SG2 to the initial potential Va, the floating state is set.

Thereafter, a high potential VppE for erasing, for example, about 20 V is applied to the well region where the memory cell is formed.
Is applied.

At this time, the word line (control gate)
Is 0 V and the potential of the well region is VVppE. Therefore, a high voltage sufficient for erasing is applied between the control gate and the well region.

Therefore, in all the memory cells, the electrons in the floating gate move to the well region due to the FN tunnel effect, and the threshold voltage of the memory cell decreases.
For example, it becomes negative.

[Read Operation] Data read is performed by changing the potential of the bit line according to the data of the memory cell and detecting this change. First, a bit line (all bit lines or a part of bit lines when a bit line shield method is adopted) to which a memory cell to be read is connected is precharged, and this bit line is precharged. After being set to a charge potential, for example, a power supply potential Vcc, a floating state is set.

Thereafter, the selected word line, that is, the control gate of the selected memory cell is set to 0 V, and the unselected word line (the control gate of the unselected memory cell) and the select gate line SG1 are powered. Potential V
cc, for example, about 3V.

At this time, when the data of the selected memory cell is "1", that is, when the threshold voltage Vth of the memory cell is larger than 0, the selected memory cell is turned off. Are maintained at the precharge potential.

On the other hand, if the data of the selected memory cell is "
In the case of "0", that is, when the threshold voltage Vth of the memory cell is smaller than 0, the selected memory cell is turned on.
As a result, the charge of the bit line connected to the selected memory cell is discharged, and the potential of the bit line drops by ΔV from the precharge potential.

As described above, since the potential of the bit line changes according to the data of the memory cell, the data of the memory cell can be read by detecting this potential change by the sense amplifier.

By the way, the NAND according to this embodiment
Cell type EEPROM is n-value NAND cell type EEPROM
Therefore, as described above, for example, a four-level NAND
In the case of a cell type EEPROM, quaternary (2-bit) data ("00", "01", "1") is stored in each memory cell.
0 "," 11 ") are written and read.

FIG. 2 is a flowchart showing a write control method when data write (program), verify, and rewrite (reprogram) are performed on the memory cell array 21 under the control of the bit line control circuit 22. is there. In this case as well, it is assumed that data reading is performed by the bit line shield method as in the conventional case.

First, programming of the memory cells in the odd and even columns is performed (STEP 1). In this case, the programming of the memory cells of the odd-numbered columns and the even-numbered columns may be performed in time parallel (simultaneously in the odd-numbered columns and even-numbered columns), or may be performed in time series (odd-numbered columns and even-numbered columns).
(Even columns separately).

Thereafter, program verification of one of the memory cells of the odd column and the even column, for example, the memory cell of the odd column is performed (STEP).
2). The program verify means reading data from a programmed memory cell and verifying whether a threshold voltage after writing is set to a desired value. At the time of this program verification,
Data read is performed by the bit line shield method. That is, while data is read from the memory cells in the odd columns, the bit lines of the memory cells in the even columns are fixed to a predetermined potential, for example, Vss (0 V).

Next, program verification of the memory cells in the even-numbered columns is performed (STEP 3). Also at the time of the program verify, data read is performed by the bit line shield method.

Next, it is determined whether or not the threshold voltages of the memory cells in the odd and even columns are set to desired values, respectively (STEP 4). If it is not set to the desired value, the program is executed with the conditions changed again. When the threshold voltage is set to a desired value, the write operation is completed.

As described above, the n-value NAND of the above embodiment is
In the cell type EEPROM, after the memory cells of the odd and even columns are programmed, the memory cells of the odd and even columns are sequentially verified.
If necessary, reprogramming is performed based on the result of the verification, and then the memory cells in the odd and even columns are verified. And reprogramming.

For this reason, as in the conventional case, the memory cell in one of the odd column and the even column is programmed, and then the verify operation is performed to complete the write operation of the memory cell in one column. In addition, it is possible to suppress the occurrence of variations in the threshold voltage of the memory cell to which writing is performed first.

Hereinafter, the reason will be described in detail.

Conventionally, when data is written to a memory cell in an odd-numbered column, program, verify, and reprogram are repeatedly performed to change the initial threshold voltage to a desired threshold voltage at a stretch as shown in FIG. It is moving. Thereafter, the memory cells in the even columns are similarly moved from the threshold voltage in the initial state to the desired threshold voltage at a stretch as shown in FIG. 6B. As a result, after the data was written to the memory cells in the even columns, it appeared that the threshold voltage of the memory cells in the odd columns to which data had been written was shifted to a higher direction due to the influence of each parasitic capacitance C.

However, in the above-described embodiment, verify writing is performed alternately on the memory cells of the odd-numbered columns and the even-numbered columns, and for the odd-numbered columns and the even-numbered memory cells, as shown in FIGS. Since the threshold voltage in the initial state is finely moved from the threshold voltage in the initial state to a desired threshold voltage shaded in the figure, the writing of the memory cells in the odd-numbered columns is performed by the influence of the threshold voltage of the memory cells in the even-numbered columns. When the threshold voltage in consideration of the shift amount reaches a desired threshold voltage, the operation is stopped.

As a result, the variation of the threshold voltage is reduced for both the memory cells of the odd and even columns.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above-described embodiment, the case where the program and the program verify are performed from the memory cells in the odd-numbered columns as shown in FIG. 2 has been described. However, it goes without saying that the order may be reversed.

[0063]

As described above, according to the present invention,
It is possible to provide a nonvolatile semiconductor memory which can reduce variation in threshold voltage of a memory cell after data writing.

[Brief description of the drawings]

FIG. 1 is a block diagram of an n-value NAND cell type EEPROM according to an embodiment of the present invention;

FIG. 2 is a flowchart showing a write control method in the EEPROM of FIG. 1;

FIG. 3 is a circuit diagram of a NAND cell unit in the EEPROM of FIG. 1;

FIG. 4 is a flowchart showing a conventional write control method in a multi-level NAND cell type EEPROM employing a bit line shield method and a verify write method.

FIG. 5 is an element sectional view of a memory cell array portion of a NAND cell type EEPROM.

FIG. 6 is a characteristic diagram showing a change in a threshold voltage of a memory cell due to a conventional writing.

[Explanation of symbols]

 21: memory cell array, 22: bit line control circuit, 23: data input / output buffer, 24: bit line control circuit, 25: column decoder, 26: row decoder.

Claims (4)

[Claims] 1. A semiconductor device comprising a word line, a control gate and a floating gate, respectively, a control gate commonly connected to the word line, and one n
A plurality of memory cells in odd and even columns storing data (n is a positive integer exceeding 2) and a plurality of memory cells in the odd and even columns are programmed with data. The program verification of the memory cells of the column and the even column is sequentially performed, the data is reprogrammed for the memory cells of the odd column and the even column according to the verification result, and the above operation is repeated to write data. A nonvolatile semiconductor memory, comprising: a control circuit for performing control. 2. The control circuit according to claim 1, wherein a program verify of a memory cell in one of the odd-numbered column and the even-numbered column is performed by a bit line shield method for fixing a bit line of a memory cell in the other column to a predetermined potential. 2. The non-volatile semiconductor memory according to claim 1, wherein the operation is performed. 3. The non-volatile semiconductor memory according to claim 1, wherein the control circuit performs data programming for the memory cells in the odd-numbered columns and the even-numbered columns in parallel in time. 4. The nonvolatile semiconductor memory according to claim 1, wherein said control circuit temporally serially programs data in said odd-numbered column and even-numbered column memory cells.