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JP3141364B2 - 半導体チップ - Google Patents

半導体チップ

Info

Publication number
JP3141364B2
JP3141364B2 JP04113570A JP11357092A JP3141364B2 JP 3141364 B2 JP3141364 B2 JP 3141364B2 JP 04113570 A JP04113570 A JP 04113570A JP 11357092 A JP11357092 A JP 11357092A JP 3141364 B2 JP3141364 B2 JP 3141364B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
layer
bump
bumps
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP04113570A
Other languages
English (en)
Other versions
JPH05315338A (ja
Inventor
勝規 西口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP04113570A priority Critical patent/JP3141364B2/ja
Priority to CA002095058A priority patent/CA2095058A1/en
Priority to AU38205/93A priority patent/AU663777B2/en
Priority to TW082103378A priority patent/TW260825B/zh
Priority to KR1019930007569A priority patent/KR930024090A/ko
Priority to MYPI93000824A priority patent/MY131396A/en
Priority to EP19930107292 priority patent/EP0568995A3/en
Publication of JPH05315338A publication Critical patent/JPH05315338A/ja
Priority to US08/358,979 priority patent/US5461261A/en
Application granted granted Critical
Publication of JP3141364B2 publication Critical patent/JP3141364B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、基板上の電極端子にバ
ンプが設けられた半導体チップに関する。
【０００２】
【従来の技術】半導体チップ上の全パッドを特定のバン
プにより基板上に接続するワイヤレスボンディングに
は、フリップチップ方式やＴＡＢ（Tape Automated Bon
ding）方式などがある。特にＴＡＢ方式では、バンプの
主材料にＡｕを用いて、Ａｕ−Ｓｎ共晶法などによって
半導体チップを接続するのが主流となっている。
【０００３】図３（ａ）は、Ａｕバンプを設けた従来の
半導体チップの構造を示す断面図である。この従来例
は、Ａｌパッド３１上にＴｉ−Ｗ合金３２が、Ｔｉ−Ｗ
合金３２上にＡｕ層３３が、Ａｕ層３３上にＡｕバンプ
３４がそれぞれ電気メッキ法により形成されている。
【０００４】
【発明が解決しようとする課題】ところで、Ａｕ−Ｓｎ
共晶法による実装方法では、基板上のパッドにＳｎをメ
ッキして、このパッドとＡｕバンプとの間でＡｕ−Ｓｎ
共晶合金反応を起こさせることにより、Ａｕバンプの表
面部分を溶解して接続していた。
【０００５】しかし、Ａｕ−Ｓｎ共晶合金反応はＡｕバ
ンプとパッドのＳｎメッキとの接触面でしか起きない。
このため、半導体チップ上のＡｕバンプの高さにばらつ
きがありパッドと接触しないＡｕバンプがある場合は接
触不良となる。このような接触不良のＡｕバンプの状態
を図３（ｂ）に示す。同図では、基板４１上に半導体チ
ップ４２が実装されているが、バンプ４４が非接触のた
めに、バンプ４４の表面ではＡｕ−Ｓｎ共晶合金反応が
起こらず接続不良となっている。
【０００６】このように従来の半導体チップは、実装時
の歩留りが低く問題であった。本発明は、このような問
題を解決することを目的とする。
【０００７】
【課題を解決するための手段】上記の課題を解決するた
めに、本発明の半導体チップは、共晶合金を組成する２
種類の金属材料を交互に積層しこれら２種類の金属材料
による複数の境界面を設けたバンプが設けられている。
【０００８】
【作用】本発明の半導体チップによれば、共晶合金を組
成する２種類の金属材料が交互に積層されたバンプが設
けられているので、各層の境界面で共晶合金反応が起こ
る。このため、バンプ全体が十分に溶解するので、適度
な圧力を掛ければ確実に基板上に半導体チップが接続で
きる。
【０００９】
【実施例】以下、本発明の一実施例について、添付図面
を参照しながら説明する。図１（ａ）は、本実施例の半
導体チップの構造を示す断面図である。本実施例では、
Ａｌパッド１１上にＴｉ−Ｗ合金１２が形成され、Ａｌ
パッド１１との密着性を確保し、かつ上層のＡｕ層１３
とＡｌパッド１１とが接合時の熱で金属間化合物を形成
しないバリヤメタルの役目を果たしている。Ｔｉ−Ｗ合
金１２上にはＡｕ層１３が形成され、上層のＡｕ層１４
をメッキ形成する時の良好なメッキ性の確保とＴｉ−Ｗ
合金１２との密着性を得ている。Ａｕ層１３の上にはＡ
ｕ層１４とＳｎ層１５とが電気メッキ法により交互に積
層されている。このＡｕ層１４とＳｎ層１５とで多層構
造のバンプ１６が形成されている。バンプ１６の最上層
は必ずしもＳｎ層である必要はなく、図１（ｂ）に示す
ようにＡｕ層が最上層であってもよい。この場合、最上
層のＡｕ層の厚さが十分に薄ければ、実装時にＡｕ層全
体がＡｕ−Ｓｎ共晶合金反応によって溶解するので、適
度な圧力を掛ければ確実に接続される。最上層のＡｕ層
が厚く全体が溶解しない場合は、テープあるいは電極パ
ッドにＳｎメッキを施せばよい。また、本実施例ではＳ
ｎ層の形成に電気メッキ法を用いたが、真空蒸着法を用
いて０．１〜２．０μｍの厚さにＳｎ層を付着させても
よい。
【００１０】このように、本実施例ではＡｕ層とＳｎ層
を交互に積層させてバンプ１６を形成しているので、実
装時に各層の境界面でＡｕ−Ｓｎ共晶合金反応を起こさ
せることができる。このため、バンプ１６全体が十分に
溶解するので、半導体チップ上に設けられた複数のバン
プの高さに多少のばらつきがあっても、適度な圧力を掛
ければ確実に接続することができる。
【００１１】実装状態の例を図２に示す。図２（ａ）
は、フリップチップ方式を用いて基板２１上に半導体チ
ップ２２を実装した状態を示す断面図である。半導体チ
ップ２２に設けられた各バンプ２３、２４、２５はいず
れも十分に溶解しており、適度な圧力を掛ければ、基板
２１上の端子に確実に接続される。また、図２（ｂ）
は、ＴＡＢ方式を用いて基板２６上に半導体チップ２７
を実装した状態を示す断面図である。半導体チップ２７
に設けられたバンプ２８はテープ２９に確実に接続され
る。
【００１２】
【発明の効果】本発明の半導体チップであれば、共晶合
金を組成する２種類の金属材料が交互に積層されたバン
プが設けられているので、各層の境界面で共晶合金反応
が起こる。このため、バンプ全体が十分に溶解するの
で、適度な圧力を掛ければ確実に接続できる。
【００１３】このように本発明は、共晶合金反応を用い
て接続するので、低ダメージ実装が可能となる。また、
バンプの高さばらつきに余裕が出るので、実装時の歩留
りが向上する。
【図面の簡単な説明】
【図１】本実施例の半導体チップの構造を示す断面図で
ある。
【図２】基板上に半導体チップを実装した状態を示す断
面図である。
【図３】従来例の半導体チップの構造を示す断面図であ
る。
【符号の説明】
１１…Ａｌパッド、１２…Ｔｉ−Ｗ合金、１３…Ａｕ
層、１４…Ａｕ層１４、１５…Ｓｎ層、１６…バンプ。

Claims (2)

    (57)【特許請求の範囲】
  1. 【請求項１】 共晶合金を組成する２種類の金属材料を
    交互に積層しこれら２種類の金属材料による複数の境界
    面を設けたバンプが設けられている半導体チップ。
  2. 【請求項２】 前記２種類の金属材料がＡｕとＳｎであ
    ることを特徴とする請求項１に記載の半導体チップ。
JP04113570A 1992-05-06 1992-05-06 半導体チップ Expired - Fee Related JP3141364B2 (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP04113570A JP3141364B2 (ja) 1992-05-06 1992-05-06 半導体チップ
CA002095058A CA2095058A1 (en) 1992-05-06 1993-04-28 Semiconductor device with bumps
AU38205/93A AU663777B2 (en) 1992-05-06 1993-04-28 Semiconductor device with bumps
TW082103378A TW260825B (ja) 1992-05-06 1993-04-30
KR1019930007569A KR930024090A (ko) 1992-05-06 1993-05-03 반도체칩
MYPI93000824A MY131396A (en) 1992-05-06 1993-05-03 Semiconductor device with bumps
EP19930107292 EP0568995A3 (en) 1992-05-06 1993-05-05 Semiconductor device with bumps
US08/358,979 US5461261A (en) 1992-05-06 1994-12-19 Semiconductor device with bumps

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04113570A JP3141364B2 (ja) 1992-05-06 1992-05-06 半導体チップ

Publications (2)

Publication Number Publication Date
JPH05315338A JPH05315338A (ja) 1993-11-26
JP3141364B2 true JP3141364B2 (ja) 2001-03-05

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US (1) US5461261A (ja)
EP (1) EP0568995A3 (ja)
JP (1) JP3141364B2 (ja)
KR (1) KR930024090A (ja)
AU (1) AU663777B2 (ja)
CA (1) CA2095058A1 (ja)
MY (1) MY131396A (ja)
TW (1) TW260825B (ja)

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MY131396A (en) 2007-08-30
AU3820593A (en) 1993-11-11
US5461261A (en) 1995-10-24
JPH05315338A (ja) 1993-11-26
KR930024090A (ko) 1993-12-21
CA2095058A1 (en) 1993-11-07
AU663777B2 (en) 1995-10-19
EP0568995A2 (en) 1993-11-10
EP0568995A3 (en) 1993-12-08
TW260825B (ja) 1995-10-21

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