JP2023032901A - Substrate and mounted substrate - Google Patents

Abstract

The present invention provides a substrate and a mounting substrate capable of suppressing melted solder alloy from reaching the other main surface side from one main surface side through a through hole.
A substrate includes a base material having a main surface, a conductor pattern disposed on the main surface and having a central pad portion, and a first annular wall. A through hole is formed in the substrate so as to pass through the substrate in the thickness direction and to overlap the central pad portion in a plan view. The first annular wall is arranged on the central pad portion so as to surround the through hole in plan view.
[Selection drawing] Fig. 1

Description

The present invention relates to substrates and mounting substrates.

For example, Japanese Patent Application Laid-Open No. 2016-18846 (Patent Document 1) describes a semiconductor package. The semiconductor package described in Patent Document 1 is a QFN (Quad Flat Non-leaded) package. A central electrode and a plurality of peripheral electrodes are exposed from the back surface of the semiconductor package of Patent Document 1. A central electrode is in the center of the back surface. A peripheral electrode surrounds the central electrode.

JP 2016-18846 A

The semiconductor package described in Patent Document 1 is mounted on a substrate. The board has, for example, a base material, a conductor pattern, and a solder resist. The substrate has a first major surface and a second major surface opposite to the first major surface. A conductor pattern is disposed on the first main surface and has a central pad, a plurality of peripheral pads, and wiring. Peripheral pads surround the central pad. The wiring connects the outer edge of the central pad and the peripheral pads. A solder resist is arranged on the first main surface so as to cover the conductor pattern. The solder resist is formed with a first opening exposing the central pad and a plurality of second openings exposing the peripheral pads.

The semiconductor package described in Patent Document 1 is mounted on a substrate by bonding the central electrode to the central pad with a solder alloy, and by bonding the peripheral electrode to the peripheral pad with a solder alloy.

Cream solder is used for bonding between the central electrode and the central pad and for bonding between the peripheral electrode and the peripheral pad. Cream solder is a paste made by mixing flux, organic solvent, and solder alloy powder. When the solder alloy powder in the cream solder is melted, the flux and the organic solvent are volatilized, so that through-holes are formed in the base material at positions overlapping the central pads in plan view. However, the molten solder alloy may reach the second main surface side through the through holes.

When the molten solder alloy solidifies on the second main surface side, the metal mask used when printing the cream solder on the pads arranged on the second surface comes into contact with the solidified solder alloy, and the second main surface Printing cream solder on top becomes unstable.

The present invention has been made in view of the problems of the prior art as described above. More specifically, the present invention provides a board and a mounting board capable of preventing molten solder alloy from reaching the other main surface side from one main surface side through a through hole.

A substrate of the present invention includes a substrate having a main surface, a conductor pattern disposed on the main surface and having a central pad portion, and a first annular wall. A through hole is formed in the substrate so as to pass through the substrate in the thickness direction and to overlap the central pad portion in a plan view. The first annular wall is arranged on the central pad portion so as to surround the through hole in plan view.

The substrate may further include a solder resist disposed on the main surface so as to cover the conductor pattern and having a first opening for exposing the central pad portion. The first annular wall may be made of the same material as the solder resist.

The substrate may further comprise a second annular wall located on the first annular wall. The second annular wall may be made of a different material than the first annular wall.

In the substrate described above, the second annular wall may be formed of resin ink colored in a color different from that of the solder resist.

In the substrate described above, the conductor pattern may further have a peripheral pad portion surrounding the central pad portion. A second opening exposing the peripheral pad portion may be further formed in the solder resist. In the substrate described above, the through hole may be a gas vent hole.

A mounting substrate according to the present invention includes the substrate described above, a semiconductor package having a back surface, and a solder alloy. The semiconductor package has a central electrode facing the central pad portion and a peripheral electrode surrounding the central electrode and facing the peripheral pad portion on the back surface. The solder alloy joins the central electrode and the portion of the central pad section outside the first annular wall in plan view, and also joins the peripheral electrode and the peripheral pad section.

In the mounting substrate described above, the semiconductor package may be a QFN package.

According to the substrate and mounting substrate of the present invention, it is possible to suppress the melted solder alloy from reaching the other main surface side from one main surface side through the through holes.

2 is a plan view of the substrate 100; FIG. FIG. 2 is a cross-sectional view along II-II in FIG. 1; 2 is a cross-sectional view of a mounting substrate 200; FIG. 3 is a bottom view of the semiconductor package 300; FIG. It is a top view of 100 A of board|substrates. It is a top view of the board|substrate 100B. FIG. 7 is a cross-sectional view along VII-VII in FIG. 6;

Details of embodiments of the present invention will be described with reference to the drawings. In the drawings below, the same or corresponding parts are denoted by the same reference numerals, and redundant description will not be repeated.

(First embodiment)
A substrate according to the first embodiment will be described. The substrate according to the first embodiment is hereinafter referred to as substrate 100 .

<Configuration of substrate 100>
The configuration of the substrate 100 will be described below.

FIG. 1 is a plan view of the substrate 100. FIG. FIG. 2 is a cross-sectional view along II-II in FIG. As shown in FIGS. 1 and 2, the substrate 100 has a base material 10, a conductor pattern 20, a solder resist 30, and a first annular wall 40. As shown in FIGS.

The substrate 10 has a first major surface 10a and a second major surface 10b. The first main surface 10a and the second main surface 10b are end surfaces in the thickness direction of the base material 10 . The second principal surface 10b is the opposite surface of the first principal surface 10a. The base material 10 is made of an electrically insulating material. The base material 10 is made of glass epoxy, for example. However, the electrically insulating material used for the base material 10 is not limited to this.

The conductor pattern 20 is arranged on the first main surface 10a. The conductor pattern 20 is made of an electrically conductive material. The conductor pattern 20 is made of copper, for example. However, the electrically conductive material used for the conductor pattern 20 is not limited to this.

The conductor pattern 20 has a central pad 21 and a plurality of peripheral pads 22 . The central pad 21 has, for example, a rectangular shape in plan view. More specifically, the central pad 21 has a square shape in plan view. Peripheral pads 22 are arranged around central pad 21 . The peripheral pad 22 has, for example, a rectangular shape in plan view. More specifically, the peripheral pad 22 is rectangular in plan view. The peripheral pad 22 is arranged apart from the outer peripheral edge (outer peripheral edge 21a) of the central pad 21 . A short side of the peripheral pad 22 in plan view faces the outer peripheral edge 21a with a gap therebetween. A plurality of peripheral pads 22 facing one side of the outer peripheral edge 21a are arranged in a row along the direction of the one side.

Some of the plurality of peripheral pads 22 (referred to as peripheral pads 22 a ) are connected to the outer peripheral edge 21 a by wiring 23 .

A through hole 100 a is formed in the substrate 100 . The through hole 100a penetrates the substrate 100 in the thickness direction. The through hole 100a is formed at a position overlapping the central pad 21 in plan view. The through hole 100a has, for example, a circular shape in plan view.

A through hole 10 c is formed in the base material 10 . The through hole 10c penetrates the base material 10 in the thickness direction. A conductor layer 24 is arranged on the inner wall surface of the through hole 10c. A conductor layer 24 is connected to the central pad 21 . The conductor layer 24 is also arranged on the second main surface 10b around the through hole 10c. The conductor layer 24 is made of an electrically conductive material (eg, copper). In this case, the hole surrounded by the conductor layer 24 becomes the through hole 100a. When the conductor layer 24 is not formed, the through hole 10c becomes the through hole 100a.

A solder resist 30 is arranged on the first main surface 10 a so as to cover the conductor pattern 20 . The solder resist 30 is also arranged on the second main surface 10b. The solder resist 30 covers a conductor pattern (not shown) arranged on the second main surface 10b. The solder resist 30 is made of an electrically insulating material. The solder resist 30 is made of epoxy resin, for example. However, the electrically insulating material used for the solder resist 30 is not limited to this. Solder resist 30 may be colored.

A first opening 31 and a plurality of second openings 32 are formed in the solder resist 30 . The first opening 31 and the second opening 32 pass through the solder resist 30 in the thickness direction. The central pad 21 is exposed through the first opening 31 . The peripheral pad 22 is exposed through the second opening 32 .

The first opening 31 is rectangular in plan view. More specifically, the first opening 31 has a square shape in plan view. The first opening 31 is, for example, outside the outer peripheral edge 21a in plan view. The second opening 32 is rectangular in plan view. More specifically, the second opening 32 is rectangular in plan view.

A first annular wall 40 is located on the central pad 21 . The first annular wall 40 surrounds the through hole 100a in plan view. The first annular wall 40 is preferably toric. The inner peripheral edge of the first annular wall 40 may reach the edge of the through hole 100a or may be spaced apart from the edge of the through hole 100a. The width of the first annular wall 40 is defined as width W1. The width W1 is the distance between the inner peripheral edge of the first annular wall 40 and the outer peripheral edge of the first annular wall 40 . The width of the central pad 21 is assumed to be width W2. The width W2 is preferably at least six times the width W1.

The first annular wall 40 is made of the same material as the solder resist 30, for example. The thickness of the first annular wall 40 is, for example, the same as the thickness of the solder resist 30 . That is, the solder resist 30 and the first annular wall 40 are formed by, for example, the same process. The solder resist 30 and the first annular wall 40 are formed by, for example, attaching a dry film of the constituent material of the solder resist 30 onto the first main surface 10a, and developing and exposing the attached dry film for patterning. Formed by Instead of sticking the dry film, a liquid constituent material of the solder resist 30 may be applied.

<Configuration of Mounting Board 200>
The configuration of the mounting substrate 200 will be described below.

FIG. 3 is a cross-sectional view of the mounting board 200. As shown in FIG. As shown in FIG. 3 , the mounting substrate 200 has a substrate 100 and a semiconductor package 300 .

The semiconductor package 300 is, for example, a QFN package. However, the semiconductor package 300 is not limited to this. The semiconductor package 300 may be, for example, an LGA (Lead Grid Array) package. The semiconductor package 300 has a lead frame 310 , a semiconductor chip 320 , bonding wires 330 and a sealing resin 340 .

The lead frame 310 has a die pad portion 311 and a plurality of lead portions 312 . A plurality of lead portions 312 are arranged around the die pad portion 311 . Lead frame 310 is made of an electrically conductive material. Lead frame 310 is made of, for example, a copper alloy. However, the electrically conductive material used for the lead frame 310 is not limited to this.

The semiconductor chip 320 has a front surface 320a and a back surface 320b. The front surface 320a and the back surface 320b are end surfaces of the semiconductor chip 320 in the thickness direction. The back surface 320b is the opposite surface of the front surface 320a. A semiconductor chip 320 is arranged on the die pad portion 311 . More specifically, the back surface 320b is connected to the die pad section 311 by a solder alloy (not shown), a conductive adhesive (not shown), or the like. Although not shown, bonding pads are formed on surface 320a.

The bonding wire 330 has one end connected to the bonding pad of the semiconductor chip 320 and the other end connected to the lead portion 312 . Bonding wire 330 is made of an electrically conductive material such as gold or copper. The sealing resin 340 seals the lead frame 310 , the semiconductor chip 320 and the bonding wires 330 . The sealing resin 340 is made of, for example, epoxy resin. However, the resin material used for the sealing resin 340 is not limited to this.

The semiconductor package 300 has a front surface 300a and a back surface 300b. The front surface 300a and the back surface 300b are end surfaces of the semiconductor package 300 in the thickness direction. FIG. 4 is a bottom view of the semiconductor package 300. FIG. As shown in FIG. 4, the die pad portion 311 and the lead portion 312 are exposed from the sealing resin 340 on the back surface 300b. The die pad portion 311 and the lead portion 312 exposed from the sealing resin 340 on the back surface 300b become the central electrode 300c and the peripheral electrode 300d of the semiconductor package 300, respectively. The peripheral electrode 300d is arranged around the central electrode 300c.

As shown in FIG. 3, the semiconductor package 300 is mounted on the substrate 100. As shown in FIG. More specifically, solder alloy 210 joins central pad 21 and central electrode 300c and joins peripheral pad 22 and peripheral electrode 300d. Solder alloy 210 is made of, for example, a tin alloy.

In mounting the semiconductor package 300 on the substrate 100 , cream solder is first applied onto the central pad 21 and the peripheral pad 22 . Cream solder is applied, for example, to the vicinity of the four corners of the center pad 21 exposed from the first opening 31 in plan view.

Second, a semiconductor package 300 is mounted on the substrate 100 . At this time, the central pad 21 faces the central electrode 300c with cream solder interposed therebetween, and the peripheral pad 22 faces the peripheral electrode 300d with cream solder interposed therebetween. By mounting the semiconductor package 300 on the substrate 100, the cream solder applied on the central pad 21 is spread.

Third, the substrate 100 with the semiconductor package 300 mounted thereon is put into a reflow furnace. As a result, the solder alloy 210 melts and spreads between the central pad 21 and the central electrode 300c and between the peripheral pad 22 and the peripheral electrode 300d, thereby forming a bond between the central pad 21 and the central electrode 300c and the peripheral pad. 22 and peripheral electrode 300d. As described above, the semiconductor package 300 is mounted on the substrate 100 to form the mounting substrate 200 .

The gas generated when the flux and the organic solvent evaporate from the cream solder is discharged through the through holes 100a. That is, the through hole 100a is a gas release hole during reflow.

<Effect of substrate 100>
The effect of the substrate 100 will be described below in comparison with the substrate according to the comparative example. A substrate according to the comparative example is referred to as a substrate 100A.

FIG. 5 is a plan view of the substrate 100A. As shown in FIG. 5, the substrate 100A has a base material 10 (not shown in FIG. 5), a conductor pattern 20, and a solder resist 30. As shown in FIG. In the substrate 100A, the conductor pattern 20 has a central pad 21, a plurality of peripheral pads 22, and wiring 23. As shown in FIG. Regarding these points, the configuration of the substrate 100A is common to the configuration of the substrate 100. FIG.

Substrate 100A does not have first annular wall 40 . In this respect, the configuration of the substrate 100A differs from that of the substrate 100. FIG.

Since the substrate 100A does not have the first annular wall 40, the solder alloy 210 melted on the central pad 21 when the semiconductor package 300 is mounted wets not only the central pad 21 but also the conductor layer 24. spread. As a result, the solder alloy 210 melted on the central pad 21 reaches the second main surface 10b side and solidifies on the second main surface 10b side.

After the components are mounted on the first main surface 10a side including the mounting of the semiconductor package 300, a metal mask is used to mount the components on the second main surface 10b side. It is applied onto the pads of the conductor pattern arranged on the surface 10b. However, when the semiconductor package 300 is mounted, the solder alloy 210 reaches the second main surface 10b side through the through holes 100a, and the solidified solder alloy 210 on the second main surface 10b side comes into contact with the metal mask. Therefore, the application of the cream solder onto the pads of the conductor pattern arranged on the second main surface 10b is not stable.

On the other hand, in the substrate 100, the first annular wall 40 is arranged on the central pad 21 so as to surround the through hole 100a. Wetting and spreading of 210 onto conductor layer 24 is prevented by first annular wall 40 . Therefore, according to the substrate 100, the melted solder alloy 210 is suppressed from reaching the second main surface 10b side from the first main surface 10a side.

When the first annular wall 40 is made of the same material as the solder resist 30, the first annular wall 40 and the solder resist 30 can be formed in the same process. Therefore, in this case, the melted solder alloy 210 is suppressed from reaching the second main surface 10b side from the first main surface 10a side without adding a new step.

(Second embodiment)
A substrate according to the second embodiment will be described. The substrate according to the second embodiment is hereinafter referred to as a substrate 100B. Here, points different from the substrate 100 will be mainly described, and redundant description will not be repeated.

<Structure of substrate 100B>
The configuration of the substrate 100B will be described below.

FIG. 6 is a plan view of the substrate 100B. FIG. 7 is a cross-sectional view along VII-VII in FIG. As shown in FIGS. 6 and 7, the substrate 100B has a base material 10, a conductor pattern 20, a solder resist 30, and a first annular wall . In this respect, the configuration of the substrate 100B is common to the configuration of the substrate 100. As shown in FIG.

Substrate 100B further has a second annular wall 50 . In this regard, the configuration of the substrate 100B differs from that of the substrate 100. FIG.

The second annular wall 50 is annular in plan view. More specifically, the second annular wall 50 has an annular shape in plan view. The second annular wall 50 is arranged on the first annular wall 40 . The second annular wall 50 is made of a material different from that of the first annular wall 40 . From another point of view, the second annular wall 50 is made of a material different from that of the solder resist 30 .

The second annular wall 50 is made of resin ink, for example. The resin ink is, for example, silk ink. This resin ink is preferably colored in a color different from that of the solder resist 30 . For example, when the solder resist 30 (the first annular wall 40) is colored green, the second annular wall 50 is made of resin ink colored white.

Although not shown, characters are drawn on the solder resist 30 with the same resin ink as that used for the second annular wall 50 . These characters indicate, for example, information necessary for mounting components on the board 100B and information regarding handling of the board 100B.

<Effect of substrate 100B>
The effect of the substrate 100B will be described below.

In the substrate 100B, since the second annular wall 50 is arranged on the first annular wall 40, the molten solder alloy 210 on the central pad 21 does not flow onto the conductor layer 24 when the semiconductor package 300 is mounted. The structure that prevents wetting and spreading is high. Therefore, according to the substrate 100B, the melted solder alloy 210 is further suppressed from reaching the second main surface 10b side from the first main surface 10a side.

Further, in the manufacturing process of the substrate 100B, characters for displaying various information are drawn on the solder resist 30 using a resin ink colored in a color different from that of the solder resist 30 . In the substrate 100B, the second annular wall 50 is formed using the same ink as the resin ink used for drawing characters as described above, so the second annular wall 50 can be formed in this process. , and there is no need to add a new process to form the second annular wall 50 .

Although the embodiment of the present invention has been described as above, it is also possible to modify the above-described embodiment in various ways. Moreover, the scope of the present invention is not limited to the above embodiments. The scope of the present invention is indicated by the scope of claims, and is intended to include all changes within the meaning and scope of equivalence to the scope of claims.

Reference Signs List 10 base material 10a first main surface 10b second main surface 10c through hole 20 conductor pattern 21 central pad 21a outer peripheral edge 22, 22a peripheral pad 23 wiring 24 conductor layer 30 solder resist 31 First opening 32 Second opening 40 First annular wall 50 Second annular wall 100, 100A, 100B Substrate 100a Through hole 200 Mounting substrate 210 Solder alloy 300 Semiconductor package 300a, 320a Surface 300b , 320b rear surface, 300c central electrode, 300d peripheral electrode, 310 lead frame, 311 die pad portion, 312 lead portion, 320 semiconductor chip, 320a front surface, 320b rear surface, 330 bonding wire, 340 sealing resin, W1, W2 width.

Claims (8)

a substrate,
a substrate having a major surface;
a conductor pattern disposed on the main surface and having a central pad portion;
a first annular wall;
a through hole is formed in the substrate, penetrating through the substrate in a thickness direction and overlapping the central pad portion in a plan view;
The substrate, wherein the first annular wall is arranged on the central pad portion so as to surround the through hole in plan view. further comprising a solder resist disposed on the main surface so as to cover the conductor pattern and having a first opening that exposes the central pad portion;
2. The substrate according to claim 1, wherein said first annular wall is made of the same material as said solder resist. further comprising a second annular wall disposed on the first annular wall;
3. The substrate according to claim 2, wherein said second annular wall is made of a different material than said first annular wall. 4. The substrate according to claim 3, wherein said second annular wall is formed of resin ink colored in a color different from said solder resist. The conductor pattern further has a peripheral pad portion surrounding the central pad portion,
5. The substrate according to claim 2, wherein the solder resist further has a second opening for exposing the peripheral pad portion. The substrate according to any one of claims 1 to 5, wherein the through holes are gas vent holes. the substrate of claim 5;
a semiconductor package having a bottom surface;
with a solder alloy,
the semiconductor package has, on the bottom surface, a central electrode facing the central pad portion, and a peripheral electrode surrounding the central electrode and facing the peripheral pad portion;
The solder alloy joins the central electrode and a portion of the central pad portion outside the first annular wall in plan view, and also joins the peripheral electrode and the peripheral pad portion, mounting board. 8. The mounting substrate according to claim 7, wherein said semiconductor package is a QFN package.

Images