JP2020008731A - Display device and method of manufacturing display device - Google Patents

Abstract

In a display device, connection failure of an IC is suppressed.
The display device includes an IC having a first bump and a second bump, a display region, and a region surrounding the display region. A substrate on which a first electrode to be connected and a second electrode to be connected to the second bump are formed; an insulating first block member disposed between the first bump and the first electrode; An insulating second block member disposed between a second bump and the second electrode, wherein the first block member and the second block member are spaced apart from each other; , A through hole is formed, the bump and the electrode are connected via a conductive ball disposed in the through hole, and the IC is mounted on the substrate.
[Selection diagram] FIG.

Description

  The present invention relates to a display device and a method for manufacturing the display device.

  In a display device such as an organic electroluminescence (EL) display device or a liquid crystal display device, for example, an IC such as a driver IC (Integrated Circuit) configuring a drive unit of the display device or a touch driver IC controlling a touch detection unit of the display device is used. Is mounted on a substrate having a display area. Specifically, a bump exists in an IC, and the bump is connected to an electrode formed on a substrate.

  There are a plurality of bumps in an IC, and it is required that all of the plurality of bumps and a plurality of corresponding electrodes are securely connected. For example, when an IC is connected to an electrode by thermocompression bonding, a phenomenon may occur in which the IC is bent and the bumps are not uniformly pressed. In order to solve such a phenomenon, it has been proposed to dispose a dummy bump between an input bump and an output bump to eliminate a connection failure (see Patent Document 1).

JP-A-2014-26042

  Regarding the connection of the IC, higher reliability is required.

  An object of the present invention is to provide a display device in which connection failure of an IC is suppressed.

  According to one aspect of the present invention, a display device is provided. A display device according to one embodiment of the present invention includes an IC having a first bump and a second bump, a display region, and a region surrounding the display region. A substrate on which a first electrode connected to one bump and a second electrode connected to the second bump are formed, and an insulating first block member disposed between the first bump and the first electrode And an insulating second block member disposed between the second bump and the second electrode, wherein the first block member and the second block member are disposed apart from each other, A through-hole is formed in the block member, and the bump and the electrode are connected via a conductive ball disposed in the through-hole, and the IC is mounted on the substrate.

  A display device according to another embodiment of the present invention includes an IC having a first bump and a second bump, a display region, and a region surrounding the display region. A substrate on which a first electrode connected to one bump and a second electrode connected to the second bump are formed, and disposed between the bump and the electrode over the first bump and the second bump; An insulating block member, wherein the block member has a through-hole formed therein, and the bump and the electrode are connected to each other through a conductive ball disposed in the through-hole. An IC is mounted on the substrate.

  According to another aspect of the present invention, a method for manufacturing a display device is provided. A method of manufacturing a display device according to the present invention includes a display region and a region surrounding the display region, and forming a temporary fixing layer on the electrode on a substrate on which an electrode is formed in the region surrounding the display region. Disposing an insulating block member having a through-hole formed on the electrode of the substrate via the temporary fixing layer; and disposing a conductive ball in the through-hole of the block member. Disposing an IC having a bump on the electrode of the substrate, and connecting the electrode and the bump via the conductive ball disposed in the through hole of the block member by applying pressure. Including.

FIG. 1 is a schematic diagram illustrating a schematic configuration of an organic EL display device according to one embodiment of the present invention. FIG. 2 is a schematic plan view illustrating an example of a display panel of the organic EL display device illustrated in FIG. 1. FIG. 3 is a schematic diagram illustrating an example of a III-III cross section in FIG. 2. FIG. 3 is a schematic diagram illustrating an example of a II section of FIG. 2. FIG. 5 is a plan view showing the arrangement of the block members shown in FIG. 4. It is a schematic diagram showing an example of a manufacturing process of an organic EL display device concerning an embodiment. It is a figure following FIG. 6A. It is a figure following FIG. 6B. It is a figure following FIG. 6C. It is a figure following FIG. 6D. It is the schematic which shows the modification of the II section of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention, which are naturally included in the scope of the present invention. In addition, in order to make the description clearer, the width, thickness, shape, and the like of each part may be schematically illustrated as compared with actual embodiments, but this is merely an example, and the interpretation of the present invention is not limited thereto. There is no limitation. In the specification and the drawings, components similar to those described in regard to a drawing thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.

  Furthermore, in the detailed description of the present invention, when defining the positional relationship between a certain component and another component, `` above '' and `` below '' are only when located directly above or directly below a certain component. Unless otherwise specified, it is intended to include the case where another component is further interposed therebetween.

  FIG. 1 is a schematic diagram showing a schematic configuration of a display device according to one embodiment of the present invention, taking an organic EL display device as an example. The organic EL display device 2 includes a pixel array unit 4 that displays an image, and a driving unit that drives the pixel array unit 4. The organic EL display device 2 is configured by forming a laminated structure such as a thin film transistor (TFT) and an organic light emitting diode (OLED) on a base material. The schematic diagram shown in FIG. 1 is an example, and the present embodiment is not limited to this.

  In the pixel array section 4, OLEDs 6 and pixel circuits 8 are arranged in a matrix corresponding to the pixels. The pixel circuit 8 includes a plurality of TFTs 10 and 12 and a capacitor 14.

  The driving section includes a scanning line driving circuit 20, a video line driving circuit 22, a driving power supply circuit 24, and a control device 26, and drives the pixel circuit 8 to control light emission of the OLED 6.

  The scanning line driving circuit 20 is connected to a scanning signal line 28 provided for each pixel row (pixel row) in the horizontal direction. The scanning line driving circuit 20 sequentially selects the scanning signal lines 28 according to the timing signal input from the control device 26, and applies a voltage for turning on the lighting TFT 10 to the selected scanning signal lines 28.

  The video line drive circuit 22 is connected to a video signal line 30 provided for each pixel array (pixel column) in the vertical direction. The video line driving circuit 22 receives a video signal from the control device 26 and, in accordance with the selection of the scanning signal line 28 by the scanning line driving circuit 20, applies a voltage corresponding to the video signal of the selected pixel row to each video signal line. Output to 30. The voltage is written to the capacitor 14 via the lighting TFT 10 in the selected pixel row. The drive TFT 12 supplies a current corresponding to the written voltage to the OLED 6, and the OLED 6 of the pixel corresponding to the selected scanning signal line 28 emits light.

  The drive power supply circuit 24 is connected to a drive power supply line 32 provided for each pixel column, and supplies a current to the OLED 6 via the drive power supply line 32 and the drive TFT 12 of the selected pixel row.

  Here, the lower electrode of the OLED 6 is connected to the driving TFT 12. On the other hand, the upper electrode of each OLED 6 is constituted by an electrode common to the OLEDs 6 of all pixels. When the lower electrode is configured as an anode (anode), a high potential is input, and the upper electrode becomes a cathode (cathode) and a low potential is input. When the lower electrode is configured as a cathode (cathode), a low potential is input, and the upper electrode becomes an anode (anode) and a high potential is input.

  FIG. 2 is a schematic plan view showing an example of the display panel of the organic EL display device shown in FIG. The pixel array unit 4 shown in FIG. 1 is provided in the display area 42 of the display panel 40, and the OLEDs 6 are arranged in the pixel array unit 4 as described above. As described above, the upper electrode constituting the OLED 6 is formed in common for each pixel and covers the entire display area 42.

  A component mounting area 46 is provided on one side of the rectangular display panel 40, and wiring connected to the display area 42 is arranged. In the component mounting area 46, a driver IC 48 constituting a driving unit is mounted, and a flexible printed circuit (FPC) 50 is connected. The FPC 50 is connected to the control device 26 and other circuits 20, 22, 24, and the like, or has an IC mounted thereon.

  FIG. 3 is a schematic view showing an example of a cross section taken along the line III-III of FIG. The display panel 40 has a structure in which a circuit layer 74 on which a TFT 72 and the like are formed, an OLED 6, a sealing layer 106 for sealing the OLED 6, and the like are laminated on a base material 70. The base member 70 is formed of, for example, a glass plate or a resin film containing a resin such as a polyimide resin. In the case of being formed of a resin film, the base material 70 is formed, for example, by applying a resin material to a film. On the sealing layer 106, a protective film 114 is laminated. Specifically, a sheet-like or film-like protective film 114 is attached to the sealing layer 106 via an adhesive layer. In the present embodiment, the pixel array section 4 is of a top emission type, and the light generated by the OLED 6 is emitted to the opposite side (upward in FIG. 3) from the substrate 70 side.

  In the circuit layer 74 of the display area 42, the above-described pixel circuit 8, the scanning signal line 28, the video signal line 30, the driving power supply line 32, and the like are formed. At least a part of the driving unit can be formed as a circuit layer 74 on the base material 70 in a region adjacent to the display region 42. As described above, the driver IC 48 and the FPC 50 that constitute the drive unit can be connected to the wiring 116 of the circuit layer 74 in the component mounting area 46.

As shown in FIG. 3, a base layer 80 formed of an inorganic insulating material is disposed on a base material 70. As the inorganic insulating material, for example, silicon nitride (SiN _y ), silicon oxide (SiO _x ), and a composite thereof are used.

  In the display region 42, a semiconductor region 82 serving as a channel portion and a source / drain portion of the top gate type TFT 72 is formed on the base material 70 via the base layer 80. The semiconductor region 82 is formed of, for example, polysilicon (p-Si). The semiconductor region 82 is formed, for example, by providing a semiconductor layer (p-Si film) on the base material 70, patterning the semiconductor layer, and selectively leaving portions used for the circuit layer 74.

  A gate electrode 86 is disposed on the channel portion of the TFT 72 with a gate insulating film 84 interposed therebetween. Gate insulating film 84 is typically formed of TEOS. The gate electrode 86 is formed by patterning a metal film formed by, for example, sputtering. Over the gate electrode 86, an interlayer insulating layer 88 is arranged so as to cover the gate electrode 86. The interlayer insulating layer 88 is formed of, for example, the above-mentioned inorganic insulating material. Impurities are introduced into the semiconductor region 82 (p-Si) serving as source / drain portions of the TFT 72 by ion implantation, and a source electrode 90a and a drain electrode 90b electrically connected to the impurity are formed. Is done.

On the TFT 72, an interlayer insulating film 92 is arranged. A wiring 94 is arranged on the surface of the interlayer insulating film 92. The wiring 94 is formed, for example, by patterning a metal film formed by sputtering or the like. For example, the wiring 116 and the scanning signal line 28 and the video signal line 30 shown in FIG. The drive power supply line 32 can be formed with a multilayer wiring structure. A flattening film 96 and a passivation film 98 are formed thereon, and the OLED 6 is formed on the passivation film 98 in the display area 42. The flattening film 96 is formed of, for example, a resin material. The passivation film 98 is formed of, for example, inorganic insulating material SiN _y, and the like.

  The OLED 6 includes a lower electrode 100, an organic material layer 102, and an upper electrode 104. The OLED 6 is typically formed by laminating a lower electrode 100, an organic material layer 102, and an upper electrode 104 in this order from the base material 70 side. In the present embodiment, the lower electrode 100 is the anode (anode) of the OLED 6, and the upper electrode 104 is the cathode (cathode).

  Assuming that the TFT 72 shown in FIG. 3 is the driving TFT 12 having an n-channel, the lower electrode 100 is connected to the source electrode 90a of the TFT 72. Specifically, after the above-described flattening film 96 is formed, a contact hole 110 for connecting the lower electrode 100 to the TFT 72 is formed. For example, a conductor portion formed in the surface of the flattening film 96 and in the contact hole 110 is formed. Is patterned to form a lower electrode 100 connected to the TFT 72 for each pixel. The lower electrode 100 is formed of, for example, a transparent metal oxide such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or a metal such as Ag or Al.

  On the above structure, a bank 112 for partitioning pixels is arranged. For example, after the lower electrode 100 is formed, a bank 112 is formed at a pixel boundary, and an organic material layer 102 and an upper electrode 104 are stacked in an effective area of the pixel surrounded by the bank 112 (an area where the lower electrode 100 is exposed). You. The organic material layer 102 typically includes a plurality of layers. Specifically, the organic material layer 102 is formed by stacking a hole transport layer, a light emitting layer, and an electron transport layer in this order from the anode side. Further, the organic material layer 102 may include other layers. Examples of the other layers include a hole injection layer and an electron block layer disposed between the anode and the light emitting layer, and an electron injection layer and a hole block layer disposed between the cathode and the light emitting layer. The upper electrode 104 is made of a transparent conductive film. The transparent conductive film is formed of, for example, an ultrathin alloy of Mg and Ag, or a transparent metal oxide such as ITO and IZO.

A sealing layer 106 is disposed on the upper electrode 104 so as to cover the entire display area 42. The sealing layer 106 has a laminated structure including a first sealing film 161, a sealing flattening film 160, and a second sealing film 162 in this order. The first sealing film 161 and the second sealing film 162 are formed of an inorganic material (for example, an inorganic insulating material). Specifically, it is formed by depositing SiN _y film by chemical vapor deposition (CVD). The sealing flattening film 160 is formed using an organic material (for example, a resin material such as a curable resin composition). On the other hand, in the component mounting area 46, the sealing layer 106 is not provided.

  For example, in order to secure the mechanical strength of the surface of the display panel 40, the protective film 114 is laminated on the surface of the display area 42. On the other hand, no protective film 114 is provided in the component mounting area 46 in order to easily connect the driver IC 48 and the FPC 50.

  FIG. 4 is a schematic view showing an example of the II section of FIG. 2, and FIG. 5 is a plan view showing the arrangement of the block members shown in FIG. In FIG. 4, the structure disposed below the wiring 116 shown in FIG.

  The wiring 116 and the driver IC 48 are electrically connected via the block member 64. In the illustrated example, one block member 64 is arranged corresponding to one bump 62 of the driver IC 48. Specifically, two adjacent block members 64, 64 are arranged apart from each other.

  In the block member 64, through holes 64a penetrating in the thickness direction are formed in an array, and two adjacent through holes 64a, 64a are arranged apart from each other. In the through-hole 64a, the bump 62 of the driver IC 48 is electrically connected to the electrode 60 of the wiring 116 by a solder ball (conductive ball) 66. Specifically, a solder ball 66 is arranged between the electrode 60 and the bump 62, and the electrode 60 and the bump 62 are joined to the solder ball 66. The size (hole diameter) of the through hole 64a is, for example, about 1 μm. In the illustrated example, one solder ball 66 is arranged in one through hole 64a, but a plurality of solder balls 66 may be arranged in one through hole 64a.

Block member 64 is formed of any suitable insulating material. In one embodiment, the thermal expansion coefficient of the block member is formed of a material similar to the thermal expansion coefficient of an IC (driver IC 48 in the illustrated example) that is electrically connected. As a specific example, block member 64, a resin (e.g., epoxy resin) and a filler (e.g., an inorganic insulating material such as SiO _x) is formed of a resin composition containing. In this case, the coefficient of thermal expansion can be controlled by adjusting the content ratio of the filler. The content ratio of the filler is, for example, 80% by weight or more of the resin composition.

  The block member 64 is, for example, formed into a plate shape so that the resin composition has a predetermined thickness, cured by baking or the like to produce a plate member, and a through hole is formed in the obtained plate member. Can be obtained. The through-hole is formed by, for example, a drill, a laser drill, or the like.

  6A to 6E are diagrams illustrating an example of a manufacturing process of the organic EL display device according to the embodiment. 6A to 6E, the structure disposed below the wiring 116 shown in FIG. 3 is simplified as the substrate 108, and the stacked structure disposed above the wiring 116 is simplified as the upper structure layer 118. ing.

  FIG. 6A shows a state in which a laminated structure such as a TFT, an OLED, and a sealing layer 106 is completed on the base material 70. In the component mounting area 46, an electrode 60 for electrically connecting to the driver IC 48 is provided.

  Next, after forming the temporary fixing layer 68 on the electrode 60 as shown in FIG. 6B, the block member 64 having the through hole 64a formed therein is arranged at a predetermined position as shown in FIG. 6C. The temporary fixing layer 68 can fix the block member 64 so as not to shift from a predetermined position. The temporary fixing layer 68 contains, for example, a silane coupling agent.

  FIG. 6D shows a step of arranging the solder balls 66 in the through holes 64a of the block member 64. The solder balls 66 may be arranged in all the through holes 64a, or the solder balls 66 may be arranged in some of the through holes 64a. As shown, the thickness of the block member 64 is set to be smaller than the diameter of the solder ball 66, for example. The temporary fixing layer 68 can fix the solder ball 66 so as not to shift from a predetermined position.

  Unlike the illustrated example, for example, a block member 64 in which solder balls 66 are arranged in advance may be arranged on the temporary fixing layer 68.

  FIG. 6E shows a step of mounting the driver IC 48. Specifically, the driver IC 48 is disposed on the electrode 60 of the substrate 108 via the block member 64, and in this state, pressure is applied to the substrate 108 from the driver IC 48 side as indicated by an arrow in the drawing. Thus, the electrode 60 and the bump 62 are electrically connected. By using the block member 64 in which the through holes 64a are formed, the solder balls 66 can be reliably arranged at desired positions (for example, at equal intervals). In addition, the presence of the block member 64 alleviates the stress generated when the driver IC 48 is deformed due to heat from being concentrated on the solder balls 66, thereby suppressing the occurrence of connection failure. By controlling the thermal expansion coefficient of the block member 64, the occurrence of connection failure due to heat can be further suppressed. Thus, a highly reliable terminal structure can be obtained. Since the connection is made by pressurization, the conductivity is not hindered by the temporary fixing layer 68 provided earlier.

  FIG. 7 is a schematic diagram showing a modification of the II section of FIG. The present invention is not limited to the above embodiment, and one block member 64 may be arranged across a plurality of bumps 62 (electrodes 60) as shown in FIG. In this case, the solder balls 66 may be arranged between the bumps 62, 62 (electrodes 60, 60) which are arranged apart from each other. However, since the insulating block member 64 is present, a problem such as a short circuit occurs. Absent.

  The present invention is not limited to the above embodiment, and various modifications are possible. For example, it can be replaced with a configuration substantially the same as the configuration shown in the above embodiment, a configuration having the same operation and effect, or a configuration that can achieve the same object.

  Within the scope of the idea of the present invention, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. For example, those skilled in the art may appropriately add, delete, or change the design of the above-described embodiments, or may add, omit, or change the conditions of the process. As long as it is provided, it is included in the scope of the present invention.

  2 organic EL display device, 4 pixel array section, 6 OLED, 8 pixel circuit, 10 lighting TFT, 12 driving TFT, 14 capacitor, 20 scanning line driving circuit, 22 video line driving circuit, 24 driving power supply circuit, 26 control device, 28 scanning signal line, 30 video signal line, 32 drive power line, 40 display panel, 42 display area, 46 component mounting area, 48 driver IC, 50 FPC, 60 electrode, 62 bump, 64 block member, 66 solder ball, 68 Temporary fixing layer, 70 base material, 72 TFT, 74 circuit layer, 80 base layer, 82 semiconductor region, 84 gate insulating film, 86 gate electrode, 88 interlayer insulating layer, 90a source electrode, 90b drain electrode, 92 interlayer insulating film, 94 wiring, 96 planarization film, 98 passivation film, 100 lower electrode, 102 Organic material layer, 104 upper electrode, 106 sealing layer, 110 contact hole, 112 bank, 114 protective film, 116 wiring.

Claims (9)

An IC having a first bump and a second bump;
A substrate having a display region and a region surrounding the display region, wherein a first electrode connected to the first bump and a second electrode connected to the second bump are formed in the region surrounding the display region; ,
An insulating first block member disposed between the first bump and the first electrode;
An insulating second block member disposed between the second bump and the second electrode,
The first block member and the second block member are arranged apart from each other,
A through-hole is formed in the block member, and the bump and the electrode are connected through a conductive ball disposed in the through-hole,
The IC is mounted on the substrate,
Display device. An IC having a first bump and a second bump;
A substrate having a display region and a region surrounding the display region, wherein a first electrode connected to the first bump and a second electrode connected to the second bump are formed in the region surrounding the display region; ,
Between the bump and the electrode, an insulating block member disposed over the first bump and the second bump,
A through-hole is formed in the block member, and the bump and the electrode are connected through a conductive ball disposed in the through-hole,
The IC is mounted on the substrate,
Display device.   The display device according to claim 2, wherein a conductive ball is disposed between the first bump and the second bump.   The display device according to claim 1, wherein the block member includes a filler-containing resin composition.   The display device according to claim 1, wherein a thickness of the block member is smaller than a diameter of the conductive ball. Having a display region and a region surrounding the display region, and forming a temporary fixing layer on the electrode of the substrate on which an electrode is formed in the region surrounding the display region;
On the electrode of the substrate, via the temporary fixing layer, disposing an insulating block member having a through hole formed therein,
Arranging a conductive ball in the through hole of the block member,
Arranging an IC having a bump on the electrode of the substrate, and connecting the electrode and the bump via the conductive ball arranged in the through hole of the block member by applying pressure; including,
A method for manufacturing a display device.   The method according to claim 6, wherein the temporary fixing layer includes a silane coupling agent.   The method according to claim 6, wherein the block member includes a filler-containing resin composition.   The method according to claim 6, wherein the thickness of the block member is smaller than the diameter of the conductive ball.

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