JP2020048184A - High frequency power amplifier and power amplifier module - Google Patents

Abstract

To provide a high frequency power amplifier capable of suppressing reduction in thermal stability of operation at a time of temperature rise of a heterojunction bipolar transistor for amplification.SOLUTION: A semiconductor chip includes at least one first transistor which amplifies a high frequency signal, a first external connection conductive member connected to the first transistor, a bias circuit including a second transistor which gives a bias voltage to the first transistor, and a second external connection conductive member connected to the second transistor. In a plan view, the second external connection conductive member at least partially overlaps with the second transistor.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a high-frequency power amplifier and a power amplification module.

  2. Description of the Related Art Heterojunction bipolar transistors are used in high-frequency power amplifiers such as portable terminals. Patent Documents 1 and 2 below disclose a high-frequency power amplifier for supplying a temperature-compensated base bias potential to a heterojunction bipolar transistor of an amplifier circuit.

  In the base bias circuit of the high-frequency power amplifier disclosed in Patent Literature 1, a diode-connected transistor for detecting temperature is arranged near a bipolar transistor for amplification. The base bias circuit of the high-frequency power amplifier disclosed in Patent Literature 2 includes a bias voltage lowering unit that lowers a bias voltage according to a temperature rise of the bipolar transistor of the high-frequency amplifier. The bias voltage lowering section has a diode, and the cathode of the diode is thermally coupled to a metal wiring connected to the emitter of the bipolar transistor of the high frequency amplifier.

JP 2001-274636 A JP-A-2002-217378

  By disposing an element such as a diode for temperature detection near the heterojunction bipolar transistor, the thermal stability of the heterojunction bipolar transistor is improved. According to the simulation by the inventor of the present application, it has been found that merely arranging the element for temperature detection in the vicinity of the heterojunction bipolar transistor for amplification may not provide sufficient thermal stability of the operation of the high-frequency power amplifier. . This is presumably because the emitter follower transistor (drive transistor) of the base bias circuit is affected by the heat generated by the amplifier circuit, so that the hFE of the drive transistor is reduced and the current supply capability is reduced.

  An object of the present invention is to provide a high-frequency power amplifier capable of suppressing a decrease in thermal stability of operation when a temperature of an amplifying heterojunction bipolar transistor rises. Another object of the present invention is to provide a power amplification module having the high-frequency power amplifier.

According to one aspect of the invention,
At least one first transistor formed on the substrate and amplifying a high-frequency signal;
A first external connection conductive member connected to the first transistor;
A bias circuit including a second transistor for applying a bias voltage to the first transistor;
A second external connection conductive member connected to the second transistor.
In a plan view, a high-frequency power amplifier is provided in which the second external connection conductive member at least partially overlaps the second transistor.

According to another aspect of the invention,
A semiconductor chip,
A module substrate on which the semiconductor chip is mounted,
The semiconductor chip,
At least one first transistor for amplifying a high-frequency signal;
A first external connection conductive member connected to the first transistor;
A bias circuit including a second transistor for applying a bias voltage to the first transistor;
A second external connection conductive member connected to the second transistor;
In a plan view, the second external connection conductive member at least partially overlaps the second transistor,
The module substrate,
A dielectric portion formed of a dielectric material;
A first land and a second land respectively opposed to the first external connection conductive member and the second external connection conductive member and connected to the first external connection conductive member and the second external connection conductive member, respectively; Land and
A power amplification module is provided, which is disposed on an inner layer of the dielectric portion and is connected to the second land, and has a conductor pattern having a size and a shape including the second land in a plan view.

  When the second transistor and the second conductive member for external connection are arranged so as to partially overlap each other in a plan view, heat radiation characteristics from the second transistor are enhanced. As a result, an increase in the temperature of the second transistor is suppressed, and a decrease in the thermal stability of the operation of the high-frequency power amplifier can be suppressed.

FIG. 1 is a block diagram of the high-frequency power amplifier according to the first embodiment. FIG. 2 is an equivalent circuit diagram of the output stage amplifier circuit and the output stage bias circuit (FIG. 1). FIG. 3 is a diagram showing a planar layout of a plurality of components of the high-frequency power amplifier according to the first embodiment on a semiconductor chip. FIG. 4 is a cross-sectional view of the first transistor Q1 and the second transistor Q2 of the high-frequency power amplifier (FIG. 1) according to the first embodiment. 5A to 5F show the layout of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 of the sample to be simulated, and the planar positional relationship of the second pad, respectively. FIG. FIG. 6 is a graph showing simulation results of the samples shown in FIGS. 5A to 5F. FIG. 7 is a diagram illustrating a planar layout of a plurality of components of a high-frequency power amplifier according to a modification of the first embodiment on a semiconductor chip. FIG. 8 is an equivalent circuit diagram of the output stage amplifier circuit and the output stage bias circuit of the high frequency power amplifier according to the second embodiment. FIG. 9 is an equivalent circuit diagram of the output stage amplifier circuit and the output stage bias circuit of the high frequency power amplifier according to the third embodiment. FIGS. 10A, 10B, and 10C are equivalent circuit diagrams of an output-stage amplifier circuit and an output-stage bias circuit of a high-frequency power amplifier according to a modification of the third embodiment. FIGS. 11A, 11B, and 11C are equivalent circuit diagrams of an output-stage amplifier circuit and an output-stage bias circuit of a high-frequency power amplifier according to another modification of the third embodiment. FIG. 12 is an equivalent circuit diagram of an output stage amplifier circuit and an output stage bias circuit of a high frequency power amplifier according to still another modification of the third embodiment. FIG. 13 is a sectional view of a high-frequency power amplifier according to the fourth embodiment.

[First embodiment]
A high-frequency power amplifier according to a first embodiment will be described with reference to FIGS. 1 to 6.
FIG. 1 is a block diagram of a high-frequency power amplifier 40 according to the first embodiment. An input signal input from the high-frequency signal input terminal RFin is input to the first-stage amplifier circuit 41 via the input matching circuit 43. The signal amplified by the first-stage amplifier 41 is input to the output-stage amplifier 42 via the interstage matching circuit 44. The signal amplified by the output stage amplifier circuit 42 is output from the high-frequency signal output terminal RFout via the output matching circuit 45.

  A bias power supply voltage is supplied from the bias voltage input terminal Vbat to the first-stage bias circuit 46 and the output-stage bias circuit 47. The first-stage bias circuit 46 supplies a bias voltage to the first-stage amplifier circuit 41 based on a bias control signal input from the first-stage bias control terminal Vbias1. The output stage bias circuit 47 supplies a bias voltage to the output stage amplifier circuit 42 based on a bias control signal input from the output stage bias control terminal Vbias2. A power supply voltage is applied to the first-stage amplifier circuit 41 from the first-stage amplifier circuit power supply voltage supply terminal Vcc1 via the inductor. A power supply voltage is applied from the power supply voltage supply terminal for output stage amplifier circuit Vcc2 to the output stage amplifier circuit 42 via the inductor 49.

  The first-stage amplifier circuit 41, the interstage matching circuit 44, the output-stage amplifier circuit 42, the first-stage bias circuit 46, and the output-stage bias circuit 47 are incorporated in one semiconductor chip 50. The input matching circuit 43, the output matching circuit 45, and the inductors 48 and 49 are mounted on a module substrate on which the semiconductor chip 50 is mounted. Various input / output terminals of the semiconductor chip 50 are constituted by pads provided on the upper surface of the semiconductor chip 50 and bumps on the pads. Although the input matching circuit 43 and the output matching circuit 45 are mounted on the module substrate in the first embodiment, the whole or a part of the input matching circuit 43 and the output matching circuit 45 may be incorporated in the semiconductor chip 50.

  FIG. 2 is an equivalent circuit diagram of the output stage amplifier circuit 42 and the output stage bias circuit 47 (FIG. 1). The basic circuit configurations of the first-stage amplifier circuit 41 and the first-stage bias circuit 46 are the same as the basic circuit configurations of the output-stage amplifier circuit 42 and the output-stage bias circuit 47, and thus description thereof is omitted here.

  The first transistor Q1 for amplification, the DC cut capacitance C0, and the base ballast resistor R1 constitute one basic cell. The DC cut capacitance C0 and the base ballast resistor R1 are both connected to the base of the first transistor Q1. The output stage amplifier circuit 42 includes a plurality of (for example, 16) basic cells connected in parallel with each other. Each of the first transistors Q1 is a heterojunction bipolar transistor. A high-frequency signal is input from the inter-stage matching circuit 44 to each base of the first transistor Q1 via the DC cut capacitor C0. A base bias voltage is supplied from the output stage bias circuit 47 to each base of the first transistor Q1 via the base ballast resistor R1. The base ballast resistor R1 has a function of suppressing thermal runaway of the first transistor Q1. The first transistor Q1 is, for example, a heterojunction bipolar transistor.

  A power supply voltage is supplied to each collector of the plurality of first transistors Q1 via the inductor 49. The emitter of each of the plurality of first transistors Q1 is grounded.

  The output stage bias circuit 47 includes a second transistor Q2 that functions as an emitter follower transistor that applies a base bias voltage to the first transistor Q1. The second transistor Q2 is, for example, a heterojunction bipolar transistor. The emitter of the second transistor Q2 is connected to the base ballast resistor R1 of each of the first transistors Q1 via the resistor R2. The collector of the second transistor Q2 is connected to the bias voltage input terminal Vbat.

  The third transistor Q3 and the fourth transistor Q4 are connected in series to form a temperature characteristic correction circuit S1. The third transistor Q3 and the fourth transistor Q4 are, for example, heterojunction bipolar transistors. In each of the third transistor Q3 and the fourth transistor Q4, a collector and a base are connected. The form in which the collector and the base of the transistor are connected is called diode connection. The diode-connected third transistor Q3 and fourth transistor Q4 function as diodes. Further, the base of the fourth transistor Q4 and the base of the second transistor Q2 are connected to form a current mirror.

  The output stage bias control terminal Vbias2 is connected to the ground via the resistor R3 and the temperature characteristic correction circuit S1. Each of the diode-connected third transistor Q3 and fourth transistor Q4 of the temperature characteristic correction circuit S1 is connected in the forward direction, and the point at which the resistor R3 and the temperature characteristic correction circuit S1 are connected to each other (the fourth transistor The voltage of (base of Q4) is applied to the base of the second transistor Q2. The base of the second transistor Q2 is connected to the ground via the bypass capacitance C1.

  The third transistor Q3 is arranged near the first transistor Q1, for example, as described later with reference to FIG. 3, and is affected by the heat of the first transistor Q1, and functions as a temperature compensating element. As the temperature of the first transistor Q1 increases, the temperature of the third transistor Q3 also increases. As a result, the voltage between the collector and the emitter of the third transistor Q3 decreases, and the bias voltage supplied to the base of the second transistor Q2 decreases. descend. When the bias voltage supplied to the base of the second transistor Q2 decreases, the bias voltage and the current supplied to the base of the first transistor Q1 also decrease. As described above, the temperature compensating element including the third transistor Q3 controls the second transistor Q2 in a direction to decrease the bias voltage and the current supplied to the base of the first transistor Q1 as the temperature rises. That is, the third transistor Q3 serving as a temperature compensating element performs feedback so as to suppress the increase in the collector current when the collector current increases with the temperature rise of the first transistor Q1.

  FIG. 3 is a diagram showing a planar layout of each component in the semiconductor chip 50 constituting the high-frequency power amplifier 40 according to the first embodiment. A region for forming the first-stage amplifier circuit 41, the output-stage amplifier circuit 42, the first-stage bias circuit 46, the output-stage bias circuit 47, and the like is secured on the upper surface of the semiconductor chip 50. In addition, areas for forming matching circuits, protection circuits, terminals for external connection, and the like are secured.

  The sixteen first transistors Q1 are arranged in an area reserved for the output stage amplifier circuit 42. The plurality of first transistors Q1 are divided into two groups of eight each, and two first pads 51 and two first bumps 52 are arranged corresponding to the two groups. In this specification, the first pad 51 and the corresponding first bump 52 are referred to as a first external connection conductive member 53. In plan view, the plurality of first transistors Q1 are arranged so as to at least partially overlap the first external connection conductive member 53. Here, that the transistor overlaps with a specific member in plan view means that at least one of a collector layer, a base layer, and an emitter layer of the transistor overlaps with the specific member in plan view. Further, “partially overlap” means that at least a part of one member overlaps at least a part of the other member. For example, the plurality of first transistors Q1 are arranged inside the first pad 51 and the first bump 52 in plan view. The first bump 52 is connected to the first transistor Q1 via the first pad 51.

  The second transistor Q2 and the fourth transistor Q4 of the output stage bias circuit 47 are arranged in a region reserved for the output stage bias circuit 47. That is, the second transistor Q2 and the fourth transistor Q4 are arranged apart from the first transistor Q1 at positions not overlapping with the first transistor Q1. The third transistor Q3 functioning as a temperature compensating element of the output stage bias circuit 47 is disposed not in the region reserved for the output stage bias circuit 47 but in the region reserved for the output stage amplifier circuit 42. . That is, the third transistor Q3 is arranged near the first transistor Q1. More specifically, it is arranged between the two groups of the first transistor Q1 and close to the first transistor Q1. The shortest distance between the centers of gravity of the plurality of first transistors Q1 to the second transistor Q2 is longer than the shortest distance between the centers of gravity of the plurality of first transistors Q1 to the third transistor Q3.

  Next, the definition of the shortest distance between the centers of gravity from the plurality of first transistors Q1 to the second transistors Q2 will be described. Each of the first transistor Q1 and the second transistor includes a collector mesa including at least a part of the collector layer, a base mesa including the base layer, and an emitter mesa including the emitter layer, as described later with reference to FIG. . Note that a configuration in which the base mesa matches the collector mesa in plan view may be employed.

  In plan view, the distance from the center of gravity (geometric center) of each emitter mesa of the plurality of first transistors Q1 to the center of gravity of the emitter mesa of the second transistor Q2 is referred to as the distance between the centers of gravity. The shortest distance between the centers of gravity of the plurality of first transistors Q1 to the second transistor Q2 is defined as the shortest distance between the centers of gravity of the plurality of first transistors Q1 to the second transistor Q2. The same applies to the definition of the shortest distance between the centers of gravity of the plurality of first transistors Q1 to the third transistors Q3.

  The second bump 56 is connected to the second transistor Q2 via the second pad 55. In this specification, the second pad 55 and the corresponding second bump 56 are referred to as a second external connection conductive member 57. The second external connection conductive member 57 corresponds to the bias voltage input terminal Vbat (FIG. 2). The second transistor Q2 and the fourth transistor Q4 are arranged so as to at least partially overlap the second external connection conductive member 57 in plan view. For example, the second transistor Q2 and the fourth transistor Q4 are arranged inside the second pad 55 in plan view.

  As described above, the first transistor Q1 and the first pad 51 have a so-called pad-on-element (POE) structure in which a pad is disposed right above the transistor. Similarly, the second transistor Q2 and the second pad 55 also have a POE structure. The semiconductor chip 50 constituting the high-frequency power amplifier 40 according to the first embodiment is mounted face-down with the surface on which the first bumps 52 and the second bumps 56 are formed facing the module substrate.

  FIG. 4 is a sectional view of the first transistor Q1 and the second transistor Q2 of the high-frequency power amplifier 40 (FIG. 1) according to the first embodiment. A layer made of n-type GaAs is formed on a substrate 60 made of semi-insulating GaAs. Part of the region 61I of this layer is insulated by ion implantation. The non-insulated region of the n-type GaAs layer is called a sub-collector layer 61. The first transistor Q1 and the second transistor Q2 are arranged on the sub-collector layer 61. The first transistor Q1 includes a collector layer Q1C, a base layer Q1B, and an emitter layer Q1E. The second transistor Q2 includes a collector layer Q2C, a base layer Q2B, and an emitter layer Q2E. The sub-collector layer 61 in which the first transistor Q1 is arranged and the sub-collector layer 61 in which the second transistor Q2 is arranged are electrically separated by an insulated region 61I. The collector layers Q1C and Q2C are formed of n-type GaAs, and the base layers Q1B and Q2B are formed of p-type GaAs. The emitter layers Q1E and Q2E are formed of n-type InGaP or the like.

  The collector layers Q1C and Q2C each constitute a mesa-shaped collector mesa CM, the base layers Q1B and Q2B each constitute a mesa-shaped base mesa BM, and the emitter layers Q1E and Q2E each constitute a mesa-shaped emitter mesa. EM. FIG. 4 shows a case where the collector mesa CM and the base mesa BM coincide with each other in a plan view. A step may be provided between them.

  A collector electrode 62 disposed on the sub-collector layer 61 is ohmically connected to the collector layer of the first transistor Q1 via the sub-collector layer 61. The base electrode 63 and the emitter electrode 64 are ohmically connected to the base layer and the emitter layer of the first transistor Q1, respectively. Similarly, a collector electrode 65 disposed on the sub-collector layer 61 is ohmically connected to the collector layer of the second transistor Q2 via the sub-collector layer 61. The base electrode 66 and the emitter electrode 67 are ohmically connected to the base layer and the emitter layer of the second transistor Q2, respectively.

  Collector wirings 72 and 75 are arranged on collector electrodes 62 and 65, respectively. Emitter wirings 74 and 77 are arranged on the emitter electrodes 64 and 67, respectively. An insulating film 80 is formed so as to cover these wirings. Note that an insulating film is disposed between the collector electrodes 62 and 65, the emitter electrodes 64 and 67, and these wirings, but illustration of the insulating film is omitted in FIG.

  The first pad 51 and the second pad 55 are arranged on the insulating film 80. The first pad 51 is connected to the emitter wiring 74 through an opening provided in the insulating film 80. Second pad 55 is connected to collector wiring 75 through another opening provided in insulating film 80. In a plan view, the first pad 51 is arranged to at least partially overlap the first transistor Q1, and the second pad 55 is arranged to at least partially overlap the second transistor Q2.

  A protective film 81 is disposed on the insulating film 80 so as to cover the first pad 51 and the second pad 55. Openings 82 and 86 are formed in the protective film 81 to expose portions of the upper surfaces of the first pad 51 and the second pad 55, respectively. The first bump 52 is arranged on the first pad 51 exposed in the opening 82, and the second bump 56 is arranged on the second pad 55 exposed in the opening 86. Each of the first bump 52 and the second bump 56 has a metal pillar made of copper or the like, and a solder layer disposed on the upper surface thereof.

Next, the excellent effects of the first embodiment will be described.
When the output stage amplifier circuit 42 operates, the temperature of the first transistor Q1 (FIG. 2) rises. When the temperature of the second transistor Q2 rises under the influence of the temperature rise of the first transistor Q1, the hFE of the second transistor Q2 decreases, and the ability to supply the base current to the first transistor Q1 decreases. When the ability to supply the base current to the first transistor Q1 is reduced, sufficient temperature compensation control cannot be performed. In particular, when the semiconductor chip 50 is mounted face-down, since the heat radiation path is limited to the bump, heat is more likely to be stored in the substrate 60 (FIG. 4) than in a configuration in which the semiconductor chip 50 is bonded to a heat sink. As a result, the second transistor Q2 is easily affected by the temperature rise of the first transistor Q1. For example, when the semiconductor chip 50 is bonded to a heat sink and connected by wire bonding, the temperature of the semiconductor chip 50 other than the heat generation point is approximately 25 ° C. On the other hand, when the semiconductor chip 50 is mounted face-down, the temperature of the semiconductor chip 50 other than the heat generation point rises to about 40 ° C.

  In the first embodiment, since the second transistor Q2 and the second pad 55 have the POE structure, the second transistor Q2 to the second pad 55 and the second bump 56 (FIG. 4), that is, the second conductive member for external connection The heat resistance of the heat dissipation path via 57 becomes small. For this reason, the temperature rise of the second transistor Q2 can be suppressed. Thereby, even if the temperature of the first transistor Q1 rises, the temperature rise of the second transistor Q2 is suppressed. As a result, it is possible to suppress a decrease in the ability to supply the base current to the first transistor Q1.

  Next, with reference to FIGS. 5A to 6, a simulation performed to confirm the excellent effects of the first embodiment will be described. An electro-thermal analysis was performed on six samples in which the positional relationship among the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 was different, and whether the POE structure was applied to the second transistor Q2 was different. A simulation was performed.

  5A to 5F show the layout of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 of the sample to be simulated, and the planar position of the second bump 56, respectively. It is a figure showing a relation.

  In each of the samples shown in FIGS. 5A to 5F, 16 first transistors Q1 are arranged in a line along a straight line extending in the vertical direction in the drawing. When the 16 first transistors Q1 are numbered sequentially from 1 to 16 from the upper end to the lower end, the first to eighth first transistors Q1 and the ninth to sixteenth first transistors Q1 are: They are arranged at an equal pitch (40 μm pitch). The center distance between the eighth first transistor Q1 and the ninth first transistor Q1 is larger than the pitch of the other first transistors Q1. A third transistor Q3 is arranged between the eighth first transistor Q1 and the ninth first transistor Q1.

  In the samples shown in FIGS. 5A and 5D, the second transistor Q2 is arranged on an extension of the column of the first transistor Q1 extending downward, and the 16th (lower end) first transistor Q1 and the second transistor Q2 The distance between the center and the transistor Q2 is 31.4 μm. The fourth transistor Q4 is arranged at a position deviated leftward from an extension of the column of the first transistor Q1 extending downward. The center-to-center distance between the second transistor Q2 and the fourth transistor Q4 at the lower end is about five times the pitch of the first transistors Q1 arranged at an equal pitch, specifically 190 μm.

  The position of the fourth transistor Q4 of the sample shown in FIGS. 5B and 5E is the same as the position of the fourth transistor Q4 of the sample shown in FIGS. 5A and 5B. In the samples shown in FIGS. 5B and 5E, the second transistor Q2 is arranged near the fourth transistor Q4. The center-to-center distance between the second transistor Q2 and the fourth transistor Q4 is 22.8 μm. That is, in the samples shown in FIGS. 5B and 5E, the second transistor Q2 is arranged farther away from the first transistor Q1 than in the samples shown in FIGS. 5A and 5D.

  In the samples shown in FIGS. 5C and 5F, the second transistor Q2 and the fourth transistor Q4 are farther away from the 16th (lower end) first transistor Q1 than the samples shown in FIGS. 5B and 5E. Are located. The distance from the first transistor Q1 at the lower end to the second transistor Q2 in the samples shown in FIGS. 5C and 5F is about twice the distance in the samples shown in FIGS. 5B and 5E, specifically 375 μm. .

  In the samples shown in FIGS. 5A, 5B, and 5C, the second transistor Q2 does not employ the POE structure. In the samples shown in FIGS. 5D, 5E, and 5F, the POE structure is employed for the second transistor Q2. That is, the second pad 55 is arranged so as to overlap the second transistor Q2.

  The DC operation of the first transistor Q1 of each of the samples of FIGS. 5A to 5F was analyzed by simulation. Specifically, the condition is such that the current flowing from the output stage bias control terminal Vbias2 becomes a constant 3.6 mA, the collector-emitter voltage Vce is changed, and the first transistor Q1 at the time of thermal steady state is changed. The collector current was determined.

  FIG. 6 is a graph showing simulation results of the samples shown in FIGS. 5A to 5F. The horizontal axis of FIG. 6 represents the collector-emitter voltage Vce of the first transistor Q1 in the unit “V”, and the vertical axis represents the total collector current Ice of the 16 first transistors Q1 in the unit “A”. The simulation result of the sample of FIG. 5A is represented by a circle and a broken line, the simulation result of the sample of FIG. 5B is represented by a triangle and a broken line, and the simulation result of the sample of FIG. 5C is represented by a square and a broken line. The simulation result of the sample of FIG. 5D is represented by a circle and a solid line, the simulation result of the sample of FIG. 5E is represented by a triangle and a solid line, and the simulation result of the sample of FIG. 5F is represented by a square and a solid line.

  When comparing the simulation results of the samples of FIGS. 5A, 5B, and 5C, a graph showing the relationship between the collector-emitter voltage Vce and the collector current Ice as the second transistor Q2 approaches the first transistor Q1 (hereinafter, Vce-Ice). It can be seen that the slope of the curve becomes larger. The large slope of the Vce-Ice curve means that the operation of the first transistor Q1 is easily affected by heat generation.

  From the comparison between the sample in FIG. 5A and the sample in FIG. 5D, the comparison between the sample in FIG. 5B and the sample in FIG. 5E, and the comparison between the sample in FIG. 5C and the sample in FIG. 5F, the POE structure is adopted for the second transistor Q2. Then, it can be seen that the slope of the Vce-Ice curve becomes small. This is because the heat radiation characteristic from the second transistor Q2 is improved, and the temperature rise of the second transistor Q2 is suppressed.

  Comparing the simulation results of the sample of FIG. 5B, the sample of FIG. 5C, and the sample of FIG. 5E, the following findings are obtained. Rather than moving the second transistor Q2 away from the first transistor Q1, adopting a POE structure for the second transistor Q2 without changing the distance from the first transistor Q1 to the second transistor Q2 will reduce the slope of the Vce-Ice curve. The effect of reducing is high. In the case of face-down mounting, since heat is easily stored in the substrate, even if the second transistor Q2 is moved away from the first transistor Q1, the effect of the second transistor Q2 reducing the thermal effect from the first transistor Q1 is low. It is thought to be. In particular, in the case of face-down mounting, by adopting the POE structure for the second transistor Q2, the effect of suppressing the temperature rise of the second transistor Q2 increases.

Next, a modification of the first embodiment will be described.
In the first embodiment, a third transistor Q3 (FIG. 3) is arranged between two groups each including eight first transistors Q1. The third transistor Q3 may be arranged near the first transistor Q1 other than between the two groups. Here, "near" means that the third transistor Q3 is close enough to be thermally affected by the temperature rise of the first transistor Q1.

  Next, a specific example in which the third transistor Q3 is arranged near the first transistor Q1 will be described. When a wiring not directly connected to either the first transistor Q1 or the third transistor Q3 or another electronic element is arranged between the third transistor Q3 and the first transistor Q1 in a plan view, the third transistor The distance between Q3 and the first transistor Q1 must be increased according to the size of the electronic elements and the wiring arranged between them. In order to arrange the third transistor Q3 so close that the third transistor Q3 is thermally affected by the first transistor Q1, a wiring not directly connected to any of the first transistor Q1 and the third transistor Q3 is provided between them. It is preferable that other electronic elements are not provided.

  For example, a line connecting the first transistor Q1 and the third transistor Q3 at the shortest distance in a plan view may be connected to a wiring not directly connected to any of the first transistor Q1 and the third transistor Q3, or to another electronic element. It is preferable to adopt a configuration that does not intersect. Here, a line segment connecting two transistors in a plan view refers to any one of the collector layer, the base layer, and the emitter layer of one transistor and any one of the collector layer, the base layer, and the emitter layer of the other transistor. Means the connecting line segments.

  The number of lines connecting the first transistor Q1 and the third transistor Q3 at the shortest distance in plan view is not limited to one line. For example, when the shapes of the first transistor Q1 and the third transistor Q3 in a plan view are rectangular, and the sides of the two rectangles are arranged in parallel and face each other, the two are connected at the shortest distance in a plan view. There are countless line segments.

  In the first embodiment, the third transistor Q3 (FIGS. 2 and 3) is used as a temperature compensating element, but a fourth transistor Q4 may be used as a temperature compensating element instead of the third transistor Q3. In this case, the fourth transistor Q4 may be arranged close to the first transistor Q1, and the third transistor Q3 may be arranged away from the first transistor Q1. Further, both the third transistor Q3 and the fourth transistor Q4 may be used as temperature compensating elements. In this case, both the third transistor Q3 and the fourth transistor Q4 may be arranged close to the first transistor Q1.

  The POE structure may also be used for circuit elements (bias elements) of the output stage bias circuit 47 other than the third transistor Q3 used as a temperature compensation element. That is, the POE structure may be used for the fourth transistor Q4, the bypass capacitor C1, and the resistor R3. Thereby, the temperature rise of these bias elements can be suppressed. As a result, the output stage bias circuit 47 is less likely to be affected by the heat generated by the first transistor Q1, and the operation is stabilized. A POE structure in which these bias elements of the output stage bias circuit 47 are arranged so as to partially overlap the second pad 55 in plan view may be employed.

  In the first embodiment, a GaAs / InGaP heterojunction bipolar transistor is used as the first transistor Q1, but a heterojunction bipolar transistor made of another compound semiconductor may be used.

  In the first embodiment, the first pad 51 and the first bump 52 constitute a first conductive member 53 for external connection, and the second pad 55 and the second bump 56 constitute a second conductive member 57 for external connection. I have. The first external connection conductive member 53 may be configured only by the first bump 52 without disposing the first pad 51. Similarly, the second external connection conductive member 57 may be constituted only by the second bump 56 without disposing the second pad 55.

Next, another modified example of the first embodiment will be described with reference to FIG.
FIG. 7 is a diagram showing a planar layout of each component in a semiconductor chip 50 constituting the high-frequency power amplifier 40 according to the present modification. In the first embodiment (FIG. 3), the plurality of first transistors Q1 are included in the first external connection conductive member 53 in plan view. On the other hand, in the present modification, a part of each of the plurality of first transistors Q1 extends outside the first external connection conductive member 53 in a plan view. As described above, the first external connection conductive member 53 may be arranged so as to partially overlap the plurality of first transistors Q1 in plan view.

  In the first embodiment, the first external connection conductive member 53 (FIG. 3) connected to the emitter of the first transistor Q1 is arranged so as to overlap the first transistor Q1 in plan view. The conductive member for external connection connected to the collector of Q1 may overlap the first transistor Q1 in plan view.

  In the first embodiment, a heterojunction bipolar transistor is used as the first transistor Q1, but a field effect transistor may be used. In this case, it is preferable to connect the first external connection conductive member 53 to the drain of the first transistor Q1. The second transistor Q2 may apply a bias voltage to the gate of the first transistor Q1.

  The conductive member for external connection connected to the source of the first transistor Q1, which is a field-effect transistor, may be arranged so as to overlap the first transistor Q1 in plan view.

[Second embodiment]
Next, a high-frequency power amplifier according to a second embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the high-frequency power amplifier (FIGS. 1, 2, 3, and 4) according to the first embodiment will be omitted.

  FIG. 8 is an equivalent circuit diagram of the output stage amplifier circuit 42 and the output stage bias circuit 47 of the high frequency power amplifier according to the second embodiment. In the second embodiment, a resistor R4 is inserted between the bias voltage input terminal Vbat and the collector of the second transistor Q2. The emitter of the second transistor Q2 is connected to the base of the third transistor Q3 via the resistor R5. A base bias voltage is supplied from the second transistor Q2 to the first transistor Q1 and the third transistor Q3. The capacitor C2 is inserted between the base and the collector of the third transistor Q3.

  Further, the collector of the fourth transistor Q4 is connected to the output stage bias control terminal Vbias2 via the resistors R6 and R3. Further, the collector of the third transistor Q3 and the emitter of the fourth transistor Q4 are connected to the output stage bias control terminal Vbias2 via the resistors R7 and R3.

  Also in the second embodiment, the third transistor Q3 functions as a temperature compensation element. Therefore, similarly to the first embodiment, the third transistor Q3 is arranged near the first transistor Q1. Further, as in the first embodiment, the second transistor Q2 is arranged away from the first transistor Q1, and the second transistor Q2 has a POE structure. With such an arrangement, excellent effects similar to those of the first embodiment can be obtained in the second embodiment.

[Third embodiment]
Next, a high-frequency power amplifier according to a third embodiment will be described with reference to FIG. Hereinafter, description of the configuration common to the high-frequency power amplifier (FIG. 8) according to the second embodiment will be omitted.

  FIG. 9 is an equivalent circuit diagram of the output stage amplifier circuit 42 and the output stage bias circuit 47 of the high frequency power amplifier according to the third embodiment. The output stage bias circuit 47 of the eighth embodiment has the same configuration as the output stage bias circuit 47 of the second embodiment except that the fourth transistor Q4 (FIG. 8) is removed. Also in the third embodiment, the third transistor Q3 functions as a temperature compensating element. In the third embodiment, the same excellent effects as in the second embodiment can be obtained.

  Next, an output stage bias circuit 47 of a high-frequency power amplifier according to a modification of the third embodiment will be described with reference to FIGS. 10A to 12.

  10A to 10C, FIGS. 11A to 11C, and FIG. 12 are equivalent circuit diagrams of the output stage bias circuit 47 of the high frequency power amplifier according to the modification of the third embodiment.

  The output stage bias circuit 47 according to the modification shown in each drawing of FIGS. 10A to 10C and each drawing of FIGS. 11A to 11C is similar to the first embodiment, the second embodiment, and the third embodiment. And a second transistor Q2 functioning as an emitter follower transistor for applying a bias voltage to the base of the first transistor Q1 (FIG. 2). Further, it includes a third transistor Q3 functioning as a temperature compensating element.

  The output stage bias circuit 47 according to the modified example shown in FIG. 12 is a bias circuit in the case where a field effect transistor (FET) is used as an amplification transistor of the output stage amplifier circuit 42. The output stage bias circuit 47 according to the present modification includes a second transistor Q2 that is an FET and a third transistor Q3 that is a bipolar transistor. The second transistor Q2 functions as a source follower transistor that applies a bias voltage to the gate of the FET of the output stage amplifier circuit 42. The third transistor Q3 functions as a temperature compensating element.

[Fourth embodiment]
Next, a power amplification module according to a fourth embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the high-frequency power amplifier (FIGS. 1, 2, 3, and 4) according to the first embodiment will be omitted.

  FIG. 13 is a sectional view of a power amplification module according to the fourth embodiment. The power amplification module according to the fourth embodiment includes a module substrate 90 and a semiconductor chip 50. As the semiconductor chip 50, the semiconductor chip 50 of the high-frequency power amplifier according to any one of the first to third embodiments is used. The semiconductor chip 50 is mounted face down on the module substrate 90. Module substrate 90 has a dielectric portion made of a dielectric material.

  A first land 91 and a second land 92 are provided on one surface of the module substrate 90, and a third land 99 and a fourth land 100 are provided on the other surface. The first land 91 and the second land 92 face the first bump 52 and the second bump 56 of the semiconductor chip 50, respectively. The first bump 52 and the first land 91 are mechanically and electrically connected by the solder 111. The second bump 56 and the second land 92 are mechanically and electrically connected by the solder 112. The third land 99 and the fourth land 100 are for mounting on a motherboard or the like.

  A first conductor pattern 93 and a second conductor pattern 94 are arranged in an inner layer of the dielectric portion of the module substrate 90. The first land 91 and the first conductor pattern 93 are connected by a plurality of via conductors 95, and the first conductor pattern 93 and the third land 99 are connected by a plurality of via conductors 96. Similarly, the second land 92 and the second conductor pattern 94 are connected by a plurality of via conductors 97, and the second conductor pattern 94 and the fourth land 100 are connected by a plurality of via conductors 98.

  The heat generated in the first transistor Q1 (FIGS. 3 and 4) of the semiconductor chip 50 is generated by the first bump 52, the solder 111, the first land 91, the via conductor 95, the first conductor pattern 93, the via conductor 96, and the It is transmitted to the motherboard and the like via the third land 99. The heat generated in the second transistor Q2 (FIGS. 3 and 4) of the semiconductor chip 50 is generated by the second bump 56, the solder 112, the second land 92, the via conductor 97, the second conductor pattern 94, the via conductor 98, and the second It is transmitted to the motherboard or the like via the four lands 100. The via conductors 95, 96, 97, 98, the first conductor pattern 93, and the second conductor pattern 94 serve as heat flow paths for radiating heat from the semiconductor chip 50. Therefore, the via conductors 95, 96, 97, 98, the first conductor pattern 93, and the second conductor pattern 94 can be said to be heat dissipation patterns.

  In order for these heat dissipation patterns to function as heat channels, it is preferable to secure a sufficient channel cross-sectional area. For example, in plan view, it is preferable that the first conductor pattern 93 has a size and shape that includes the first land 91, and the second conductor pattern 94 has a size and shape that includes the second land 92. Here, “having the included size and shape” does not mean that the first land 91 is arranged at a position included in the first conductor pattern 93 in plan view. Even when the first land 91 can be included in the first conductor pattern 93 by moving the first land 91 in parallel in the in-plane direction, the size of the first conductor pattern 93 including the first land 91 and It can be said that it has a shape.

  Further, in order to increase the cross section of the heat flow path between one land and the conductor pattern of the inner layer, it is preferable to arrange a plurality of via conductors for connecting the two. When a plurality of via conductors are arranged to connect one land and one inner layer conductor pattern, these via conductors can be called a heat dissipation pattern.

  Next, a modification of the fourth embodiment will be described. In the fourth embodiment (FIG. 13), the first conductor pattern 93 is arranged between the via conductor 95 and the via conductor 96. However, the third conductor pattern 93 is arranged without the first conductor pattern 93. It may be extended to the land 99. In this configuration, the first land 91 and the third land 99 are connected by a plurality of via conductors 95.

  A communication device may be configured by combining the power amplification module according to the fourth embodiment with an antenna element, a diplexer, and the like.

  Each of the embodiments described above is an exemplification, and it goes without saying that the configurations shown in the different embodiments can be partially replaced or combined. The same operation and effect of the same configuration of the plurality of embodiments will not be sequentially described for each embodiment. Furthermore, the invention is not limited to the embodiments described above. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

Reference Signs List 40 High frequency power amplifier circuit 41 First stage amplifier circuit 42 Output stage amplifier circuit 43 Input matching circuit 44 Interstage matching circuit 45 Output matching circuit 46 First stage bias circuit 47 Output stage bias circuit 48, 49 Inductor 50 Semiconductor chip 51 First pad 52 First Bump 53 First conductive member for external connection 55 Second pad 56 Second bump 57 Second conductive member for external connection 60 Substrate 61 Sub-collector layer 61I Insulated region 62 Collector electrode 63 Base electrode 64 Emitter electrode 65 Collector electrode 66 Base electrode 67 emitter electrode 72 collector wiring 74 emitter wiring 75 collector wiring 77 emitter wiring 80 insulating film 81 protective film 82, 86 opening 90 module substrate 91 first land 92 second land 93 first conductive pattern 94 second conductive pattern 95, 96, 97, 98 via Body 99 third land 100 the fourth land 111, 112 solder BM mesa C0 DC cut capacitor C1 bypass capacitor C2 capacitance CM mesa EM emitter mesa Q1 first transistor (amplification transistor)
Q1B Base layer Q1C Collector layer Q1E Emitter layer Q2 Second transistor (driving transistor)
Q2B Base layer Q3C Collector layer Q4E Emitter layer Q3 Third transistor (element for temperature compensation)
Q4 Fourth transistor R1 Base ballast resistors R2, R3, R4, R5, R6, R7 Resistance RFin High frequency signal input terminal RFout High frequency signal output terminal S1 Temperature characteristic compensation circuit Vbat Bias voltage input terminal Vbias1 First stage bias control terminal Vbias2 Output stage bias control Terminal Vcc1 Power supply voltage supply terminal for first stage amplifier circuit Vcc2 Power supply voltage supply terminal for output stage amplifier circuit

Position of the fourth transistor Q4 of the samples shown in FIGS. 5B and 5E is identical to the position of the fourth transistor Q4 of the samples shown in FIGS. 5A and FIG. 5 D. In the samples shown in FIGS. 5B and 5E, the second transistor Q2 is arranged near the fourth transistor Q4. The center-to-center distance between the second transistor Q2 and the fourth transistor Q4 is 22.8 μm. That is, in the samples shown in FIGS. 5B and 5E, the second transistor Q2 is arranged farther away from the first transistor Q1 than in the samples shown in FIGS. 5A and 5D.

FIG. 9 is an equivalent circuit diagram of the output stage amplifier circuit 42 and the output stage bias circuit 47 of the high frequency power amplifier according to the third embodiment. The output stage bias circuit 47 of the third embodiment has the same configuration as the output stage bias circuit 47 of the second embodiment except that the fourth transistor Q4 (FIG. 8) is removed. Also in the third embodiment, the third transistor Q3 functions as a temperature compensating element. In the third embodiment, the same excellent effects as in the second embodiment can be obtained.

Claims (14)

At least one first transistor for amplifying a high-frequency signal;
A first external connection conductive member connected to the first transistor;
A bias circuit including a second transistor for applying a bias voltage to the first transistor;
A second external connection conductive member connected to the second transistor.
A high-frequency power amplifier in which the second external connection conductive member at least partially overlaps the second transistor in plan view. The bias circuit further includes a temperature compensating element that controls the second transistor in a direction to decrease a bias voltage applied to the first transistor with a rise in temperature,
The high-frequency power amplifier according to claim 1, wherein a shortest distance from the first transistor to the second transistor is longer than a shortest distance from the first transistor to the temperature compensating element. The bias circuit further includes a bias element that is at least one of a resistor, a capacitor, and a transistor, in addition to the second transistor and the temperature compensation element,
The high-frequency power according to claim 2, wherein the bias element does not overlap with the first external connection conductive member but overlaps with the second external connection conductive member or another external connection conductive member in a plan view. amplifier.   A plurality of the at least one first transistor is disposed on the semiconductor chip, the plurality of first transistors are divided into at least two groups, and the first external connection is provided for each of the at least two groups. 4. The high-frequency power amplifier according to claim 2, further comprising a conductive member for use, wherein the temperature compensation element is disposed between the first transistor in one group and the first transistor in the other group. 5. .   The first transistor is a heterojunction bipolar transistor, the first external connection conductive member is connected to an emitter or a collector of the first transistor, and the second transistor is connected to a base or a collector of the first transistor. The high-frequency power amplifier according to any one of claims 1 to 4, which applies a voltage.   The first transistor is a field-effect transistor, the first conductive member for external connection is connected to a drain or a source of the first transistor, and the second transistor has a voltage applied to a gate or a drain of the first transistor. The high frequency power amplifier according to any one of claims 1 to 4, which provides:   The high-frequency power amplifier according to any one of claims 1 to 6, wherein the first transistor is included in the first external connection conductive member in a plan view. A semiconductor chip,
A module substrate on which the semiconductor chip is mounted,
The semiconductor chip,
At least one first transistor for amplifying a high-frequency signal;
A first external connection conductive member connected to the first transistor;
A bias circuit including a second transistor for applying a bias voltage to the first transistor;
A second external connection conductive member connected to the second transistor;
In a plan view, the second external connection conductive member at least partially overlaps the second transistor,
The module substrate,
A dielectric portion formed of a dielectric material;
A first land and a second land facing the first external connection conductive member and the second external connection conductive member, respectively, and connected to the first external connection conductive member and the second external connection conductive member, respectively; Land and
A power amplifying module comprising: a conductor pattern disposed on an inner layer of the dielectric portion, connected to the second land, and having a size and shape that includes the second land in plan view. The bias circuit further includes a temperature compensating element that controls the second transistor in a direction to decrease a bias voltage applied to the first transistor with a rise in temperature,
The power amplifier module according to claim 8, wherein a shortest distance from the first transistor to the second transistor is longer than a shortest distance from the first transistor to the temperature compensation element. The bias circuit further includes a bias element that is at least one of a resistor, a capacitor, and a transistor, in addition to the second transistor and the temperature compensation element,
The power amplifier according to claim 9, wherein the bias element does not overlap the first external connection conductive member but overlaps the second external connection conductive member or another external connection conductive member in plan view. module.   A plurality of the at least one first transistor is disposed on the semiconductor chip, the plurality of first transistors are divided into at least two groups, and the first external connection is provided for each of the at least two groups. The power amplification module according to claim 9, further comprising: a conductive member for use in the power amplifier, wherein the temperature compensation element is disposed between the first transistor in one group and the first transistor in the other group. .   The first transistor is a heterojunction bipolar transistor, the first external connection conductive member is connected to an emitter or a collector of the first transistor, and the second transistor is connected to a base or a collector of the first transistor. The power amplification module according to any one of claims 8 to 11, which applies a voltage.   The first transistor is a field-effect transistor, the first conductive member for external connection is connected to a drain or a source of the first transistor, and the second transistor has a voltage applied to a gate or a drain of the first transistor. The power amplification module according to any one of claims 8 to 11, which provides:   The power amplification module according to any one of claims 8 to 13, wherein the first transistor is included in the first external connection conductive member in a plan view.

Images