JP2019521454A - Control the operating speed of asynchronous pipeline stages - Google Patents

Abstract

The asynchronous pipeline (105) includes a first stage (112) and one or more second stages (111, 113). The controller (162) provides a control signal to the first stage indicating a change in the operating speed of the first stage. The change is determined based on a comparison of the completion status of the first stage and one or more completion statuses of one or more second stages. In some cases, the controller provides a control signal indicative of a change to the operating voltage applied to the first stage and the drive strength of the buffer (226) in the first stage. [Selection] Figure 1

Description

(Government license right)
This invention was made with government support under main contract number DE-AC 52-07NA 27344, outsourced number B 609 201, ordered by the Department of Energy (DOE). The government has certain rights in the invention.

  Processing systems typically implement a pipelined architecture that includes a series of stages for processing instructions. Each stage performs the task of computing input data and generating output data. Data is communicated between stages by registers that can be implemented as flip flops or latches. The stage accesses input data from the input register and provides output data to the output register. The input register of the stage of the pipeline can receive as output data the output data provided to the corresponding output register by the previous stage of the pipeline, and the output register of the stage is the input data of the subsequent stage It can be done. The stages in the pipeline sometimes operate on multiple sets of input data simultaneously. For example, a pipelined architecture implementing single instruction multiple data (SIMD) operations can simultaneously execute a set of identical instruction multiple input data called "waves" or "computed waves". A wave is composed of a plurality of work items corresponding to different sets of input data. Work item execution times for each wave may be completed at different times, as the execution time of the work item usually varies depending on the input data.

  The present disclosure may be better understood by those of ordinary skill in the art by reference to the accompanying drawings, and its numerous features and advantages will be apparent. The use of the same reference symbols in different drawings indicates similar or identical items.

FIG. 1 is a block diagram of a processing system that includes an asynchronous pipeline, according to some embodiments. FIG. 6 is a block diagram of a portion of an asynchronous pipeline, according to some embodiments. FIG. 7 is a block diagram of a portion of an asynchronous pipeline that includes replica critical paths, according to some embodiments. FIG. 6 is a block diagram of a portion of an asynchronous pipeline, according to some embodiments. FIG. 7 is a block diagram of a portion of an asynchronous pipeline that implements intermediate completion status detection in a replica critical path, according to some embodiments. FIG. 7 is a block diagram of a portion of an asynchronous pipeline that implements intermediate completion status detection, according to some embodiments. FIG. 7 is a block diagram of a portion of an asynchronous pipeline that implements parallel processing, according to some embodiments. FIG. 7 is a flow diagram of a method of changing the operating speed of a stage in an asynchronous pipeline, according to some embodiments.

  If the stages of the execution pipeline are synchronous, and if the registers between the stages are clocked or asynchronous using the same clock signal, then each stage of the pipeline is self-timed, This allows different stages to read input data, execute instructions, and write output data independently of other stages. In any case, the stage completes the task with different latencies depending on the type of operation performed by the stage, the data operated on by the stage, and the series of data values operated by the stage. Stages that complete tasks earlier than other stages remain idle while waiting for other stages to complete, which reduces the overall throughput of the pipeline and reduces static power consumed by idle stages. waste. The timing of the synchronization pipeline is usually the latency of the critical path across all stages of the synchronization pipeline during logic synthesis and the hardware of the synchronization pipeline in order to try to maximize the operating frequency of the synchronization pipeline. It is adjusted based on the physical layout of the wear. However, synchronization pipelines typically perform a variety of different operations that have different latencies than the critical path latency used during synchronization pipeline design. As a result, the performance of the synchronous pipeline is not always optimal and not always as energy efficient as expected.

  The performance and energy efficiency of the asynchronous pipeline is based on the comparison of the completion status of the first stage in the asynchronous pipeline with the completion status of at least one other (second) stage. 1) It can be improved by changing the operating speed of the stage. In some embodiments, changing the operating speed of the first stage of the asynchronous pipeline changes the operating voltage applied to the first stage (or a portion thereof) or within the first stage Changing the buffer drive strength applied to one or more of the drive buffers. For example, when the completion status of the first stage is set to "complete", it indicates that the first stage has completed the operation on the input data and generated the output data. At the same time, if both the completion status of an adjacent stage providing input data to the first stage and another adjacent stage receiving the output data from the first stage are both set to “in process” Indicates that the stage has not completed the operation on the input data. In this case, the buffer drive strength or voltage supply to the first stage can be reduced to save energy in the first stage while the adjacent stages complete processing. In another example, an adjacent stage providing input data to the first stage, and another adjacent stage receiving output data from the first stage, while the completion status of the first stage is "in process". Buffer drive strength for the first stage to accelerate processing by the first stage to reduce its latency and reduce idle time in the second stage, if both completion statuses of the The voltage supply can be increased.

  Determining the completion status of the first stage and the second stage by monitoring the output signals generated by the first stage and the second stage in response to the start of execution of the calculation wave by the first stage and the second stage it can. In some variations, the completion status of the first stage and the second stage apply the input signal to the replica critical path of the first stage and the second stage simultaneously with the start of the execution of the calculation wave in the first stage and the second stage Then, it is determined by determining that the first stage and the second stage have been completed in response to the detection of the output signal at the output of the replica critical path. The replica critical path is defined based on circuit simulation of the stage. In some embodiments, the stage completion status indicates an estimated completion time for the stage or part of the stage. For example, determine the completion status of the first and second stages using a look-up table that provides an estimate of completion time based on the type of instruction (as indicated by the opcode of the instruction) and the characteristics of the input data be able to. In other embodiments, the completion status of the stage is determined based on the monitoring signal in the logical cloud of the stage or the output signal of the activity. For example, if all output signals from a stage do not change for a while, the stage may have completed the task. In another example, the stage may have completed a certain percentage of operations (e.g., 50% of operations, etc.) if one or more signals at predetermined locations within the stage's logic cloud have not changed.

  FIG. 1 is a block diagram of a processing system 100 that includes an asynchronous pipeline 105, according to some embodiments. As used herein, the term "asynchronous pipeline" refers to a clock or timing at which the stages of the asynchronous pipeline are not synchronized with the global clock or timing reference used by an entity external to the asynchronous pipeline within processing system 100. Indicates to operate according to the standard. Furthermore, the individual stages in the asynchronous pipeline are not necessarily synchronized with one another, and in some cases can operate according to their own internal clock. Stages within an asynchronous pipeline are sometimes referred to as "self-timed" stages. Thus, as described herein, the operating speed of a stage in an asynchronous pipeline can vary independently of the operating speeds of other stages in the asynchronous pipeline.

  The asynchronous pipeline 105 includes a plurality of stages 110, 111, 112, 113, 114, collectively referred to herein as "stages 110-114." Data may be implemented using flip-flops, latches or other storage devices pipeline registers 120, 121, 122, 123, 124, 125 (collectively referred to herein as "registers 120-125") Are stored at various places in the asynchronous pipeline 105. In the illustrated embodiment, stage 110 performs a logical operation on input data stored in register 120, which may be implemented as a flip flop. Stage 110 generates output data that is stored in register 121, which may be implemented as a latch. Stage 111 performs a multiplication operation on the input data stored in register 121 and generates output data stored in register 122, which can be implemented as a latch. Stage 112 performs an addition operation on the input data stored in register 122 and produces output data stored in register 123 which may be implemented as a latch. Stage 113 performs a normalization operation on the input data stored in register 123 and produces output data stored in register 124 which may be implemented as a latch. Stage 114 performs rounding operations on the input data stored in register 124 and produces output data stored in register 125, which may be implemented as a flip flop. Although five stages and a corresponding number of pipeline registers are shown in asynchronous pipeline 105, some embodiments of asynchronous pipeline 105 may have more or fewer stages performing the same or different operations. And include more or less pipeline registers.

  Input controller 130 provides clock signal 131 and enable signal 132 to register 120 and module 135. Clock signal 131 is synchronized with an external clock signal used in a synchronous domain to provide data to register 120. Thus, module 135 acts as a boundary between the synchronization domain and asynchronous pipeline 105, eg, by converting signals from the synchronous domain into the asynchronous domain of pipeline 105. Module 135 provides feedback 133 indicating whether asynchronous pipeline 105 is ready to process additional data. For example, feedback 133 can indicate that logic 110 is ready to process additional data, which is then clocked into register 120 by input controller 130. Module 140 is used to control the signal output from asynchronous pipeline 105. Some embodiments of module 140 serve as a boundary between an asynchronous domain of asynchronous pipeline 105 and a synchronous domain within processing system 100. For example, module 140 may provide a valid signal 141 indicating that valid data is ready to be clocked into register 125. Also, module 140 and register 125 may receive clock signal 145 synchronized to an external clock signal used in the synchronization domain.

  Modules 150, 151, 152 (collectively referred to herein as "modules 150-152") operate in conjunction with modules 135, 140 to coordinate the operation of stages 110-114. For example, module 150 may receive a completion status signal 155 from stage 111 indicating the completion status of stage 111, and may indicate start signal 156 indicating that execution of the task on the input data stored in register 121 has been initiated by stage 111. Received from module 135. Module 150 controls feedback to indicate that the next stage 112 is ready to begin performing the task on the next data set, and latch control to control the latching of data provided by stage 111 into register 122. Provides signal 158 and access by stage 112 to data from register 122. Also, module 150 initiates execution of the task of computing the data stored in register 122 and provides an initiation signal 159 that indicates to subsequent module 151 that execution has begun. For clarity of explanation, modules 135, 140, 151, 152 provide and receive corresponding signals (not indicated by corresponding reference numbers).

  Stage controllers 161, 162, 163, 164 (collectively referred to herein as “stage controllers 161-164”) are used to control the operation of stages 111-114 in asynchronous pipeline 105. Some embodiments of stage controller 162 are provided by signal 165 indicating that it is provided by module 150 to indicate completion status information of stage 111 and by module 151 to indicate completion status information of stage 113. The stage 112 is configured to be controlled based on the signal 166. Stage controller 162 provides control signals 167 that are used to set or change the operating speed of stage 112. The stage controller 162 determines the operating speed of the stage 112 (or its change) based on the completion status of the stage 111, the completion status of the stage 112, the completion status of the stage 113, or a combination thereof. As described herein, stage controllers 161, 163, 164 may control the operating speed of corresponding stages 111, 113, 114 based on the completion status of one or more other stages. For the sake of clarity, reference numbers indicating all corresponding signaling provided or received by stages 111, 113, 114 are not provided.

In some embodiments, the operating speed of stages 111-114 is determined by the drive strength of one or more buffers implemented in stages 111-114, the operating voltage of stages 111-114, or a combination thereof . For example, stage controller 162 may determine changes to the speed of operation of stage 112 based on the completion status of stages 111-113 according to Table 1.

  The completion status in Table 1 indicates that the corresponding stage is executing (processing) the current task, or the corresponding stage has completed the execution of the current task (completion), whereby the new task is performed. Indicates that it is ready to accept execution. The operating speed can be changed to save energy or to accelerate processing by stage 112. For example, if the completion status of stage 111 is in progress, the completion status of stage 112 is complete, and the completion status of stage 113 is in progress, then stage controller 162 may reduce energy consumption by stage 112. , Reduce the buffer drive strength and voltage supply provided to stage 112. In another example, if the completion status of stage 111 is complete, the completion status of stage 112 is in progress, and the completion status of stage 113 is complete, then stage controller 162 may accelerate processing by stage 112. To increase the buffer drive strength and voltage supply provided to the stage 112. As described herein, some embodiments of Table 1 can be stored in a look-up table.

  Changing the voltage supply to stages 111-114 affects the operating speed of all the logic in stages 111-114. However, as described herein, in some embodiments, the voltages supplied to portions or regions of stages 111-114 may be stages to control the speed of operation of the separate portions or regions. It is changed separately from the other part or area | region of 111-114. Changing the drive strength of the buffer in stages 111-114 affects the part or area of stages 111-114 upstream of the buffer. For example, changing the drive strength of the buffer at the beginning, middle and end of each stage 111-114 can be used to change the operating speed of the path in the corresponding part of stages 111-114. Configurable drive buffers can also be placed on long wires in the logic of stages 111-114 to control routing delays. Increasing the drive strength of the buffer can typically reduce the propagation time of the signal along the path in stages 111-114, which can reduce the computation time along the path. In some embodiments, separate voltage sources are used to control the signal propagation rate to provide interconnect logic. The separate voltage sources are controlled independently of the other voltage sources used to supply the other parts of the logic in stages 111-114. In some variations, the voltage can be changed in fine voltage control (e.g., in 10 millivolt (mV) steps with transition times between voltage states as short as 1 nanosecond). Foot transistors can be used for power gating or voltage control of part of the logic of stages 111-114.

  Some embodiments of the processing system 100 include a pipeline controller 170 connected to an input controller 130 or stage controllers 161-164. Pipeline controller 170 determines the completion time of pipeline stages 110-114. Stage controllers 161-164 may attempt to adjust the completion time of corresponding stages 110-114 based on the overall completion time of asynchronous pipeline 105. As described herein, tuning includes changing the supply voltage at the logic cones of stages 110-114 and changing the drive strength of the buffer. For example, pipeline controller 170 may control asynchronous execution of instructions in the lanes of an asynchronous single instruction multiple data (SIMD) pipeline implemented by a computer unit. Other circuits or pipelines within the computer unit can operate synchronously and communicate with the asynchronous SIMD pipeline through dedicated buffers. The pipeline controller 170 monitors the progress of execution of a single instruction across multiple lanes of an asynchronous SIMD pipeline, and perhaps the last pipeline stage 114 to minimize the speed of task completion. Can be supported to eliminate lane differences (ie, differences in instruction completion time across all SIMD lanes in a wave), so that all lanes have the same instruction Complete tasks against at almost the same time. Write results back to (a) logic that bypasses data to consumer instructions traveling in the SIMD pipeline by controlling lane differences using the pipeline controller 170 and (B) VRF in the synchronization domain You can simplify the logic. In some variations, the individual stage controllers 161-164 attempt to improve timing and reduce energy consumption by completing instruction execution in less overall time.

  FIG. 2 is a block diagram of a portion 200 of an asynchronous pipeline in accordance with some embodiments. Portion 200 includes stage 205 that accesses input data from input register 210 and provides output data to output register 215. Portion 200 is used in some embodiments of asynchronous pipeline 105 shown in FIG. In some variations, the input register 210 and the output register 215 are used to implement one or more of the registers 121-124 shown in FIG. 1, and the stage 205 is shown in FIG. Used to implement the corresponding stage of 114. Stage 205 includes logic regions 220, 221, 222 (collectively referred to herein as "logic regions 220-222") that implement logic to perform some of the tasks assigned to stage 205. Logic regions 220-222 are interconnected by an interconnect network including buffers 225, 226, 227 (collectively referred to herein as "buffers 225-227") that provide drive current to regions upstream of the logic in portion 200. It is connected. Buffers 225-227 are configurable buffers that can operate with variable drive strengths determined based on control signals received by buffers 225-227.

  Also, the portion 200 includes a stage controller 230 that can set or change the operation speed of the stage 205 (or a portion thereof) based on the completion status of other stages (not shown) in the asynchronous pipeline. . In some variations, stage controller 230 may correspond to any of stage controllers 161-164 shown in FIG. Some embodiments of stage controller 230 change the operating voltage of stage 205 to change the operating speed of stage 205. The operating voltage applied to the entire stage 205 can be changed to change the operating speed of the logic regions 220-222, or the operating voltage applied to the logic regions 220-222 can be changed individually to The operating speed of one or more of the one or more logic regions of regions 220-222 can be changed. Some embodiments of the stage controller 230 change the drive strength of one or more of the buffers 225-227 to change the operating speed of the logic downstream of the corresponding buffer 225-227. For example, the stage controller 230 can change the drive strength of the buffer 225 to change the operating speed of downstream logic such as the logic area 222 and the logic area 221.

  Some embodiments of the portion 200 include a look-up table (LUT) 235 incorporated into the stage controller 230 or stored in a memory accessible to the stage controller 230. Look-up table 235 includes an entry that contains estimates of completion times of different types of instructions that can be executed by stage 205. For example, each entry in look-up table 235 includes an estimate of completion time indexed by instruction opcode, instruction type, input data value, etc. In some variations, the estimate of completion time is determined using circuit simulation or random circuit simulation for stage 205. Next, the stage controller 230 determines, based on the opcode or type of the instruction being executed by the stage 205 or the value of the data being operated on by the instruction (eg, the value of the data stored in the input register 210) The completion status of stage 205 can be estimated. For example, the stage controller 230 receives a signal indicating a start time at which the stage 205 starts executing the task including the instruction from a module (for example, any of the modules 135, 140, 150 to 152 shown in FIG. 1). Can. The stage controller 230 estimates the completion status of the stage 205 by comparing the current time with the start time plus the estimated completion time determined based on the entries in the look-up table 235. Some embodiments of stage controller 230 may access other stages (providing input data to input register 210, or output data from output register 215) based on the information stored in look-up table 235 Estimate the completion time of the

  FIG. 3 is a block diagram of a portion 300 of an asynchronous pipeline that includes replica critical paths, according to some embodiments. Portion 300 includes a stage 305 that accesses input data from input register 310 and provides output data to output register 315. Portion 300 is used in some embodiments of asynchronous pipeline 105 shown in FIG. In some variations, input register 310 and output register 315 are used to implement one or more of registers 121-124 shown in FIG. 1, and stage 305 is shown in stages 110-110 of FIG. Used to implement the corresponding stage of 114.

  Stage 305 is associated with a replica critical path 320 that includes logic configured to replicate the timing of one or more critical paths in stage 305, such that the critical paths in stage 305 are input data. After a time interval corresponding to the time required to complete the process, replica critical path 320 completes the processing of the input data. For example, replica critical path 320 can include a number of gates that matches the number of gates implemented along the critical path of stage 305. Also, replica critical path 320 may be configured to match the fan-in and fan-out values of the gate along the critical path of stage 305. Some embodiments of replica critical path 320 include logic that is not necessarily identical to the logic of the critical path in stage 305. Instead, the logic of replica critical path 320 causes the value of the input signal to change as it passes through the gate of replica critical path 320 to facilitate monitoring of the flow of signals along replica critical path 320. It is configured. The latency between the replica critical path 320 and the actual critical path can be determined using circuit simulation.

  Also, portion 300 includes modules 325, 330 that provide and receive signals that are used to estimate the completion status of stage 305. Modules 325, 330 are used to implement some embodiments of modules 120, 125, 150-152 shown in FIG. Some embodiments of module 325 provide an initiation signal 335 for causing replica critical path 320 to begin processing input data. The start signal 335 is provided at the same time as the start signal used by the stage 305 to start processing the input data stored in the input register 310. Module 330 monitors the output signal 340 generated by replica critical path 320 in response to start signal 335 to determine the completion status of replica critical path 320. In some variations, module 330 may detect the particular pattern of output signal 340 or determine that the data stored in the output register associated with replica critical path 320 has reached steady state. Thus, it is determined that the replica critical path 320 has completed the operation on the input data. Latency may be added to or subtracted from the completion time determined by module 330 for replica critical path 320 to compensate for the difference between the estimated completion time of stage 305 and the actual completion time.

  FIG. 4 is a block diagram of a portion 400 of an asynchronous pipeline in accordance with some embodiments. Portion 400 includes stage 405 that accesses input data from input register 410 and provides output data to output register 415. Portion 400 is used in some embodiments of asynchronous pipeline 105 shown in FIG. In some variations, the input register 410 and the output register 415 are used to implement one or more of the registers 121-124 shown in FIG. 1, and stage 405 is the stage 110-110 shown in FIG. 1. Used to implement the corresponding stage of 114.

  Status module 420 is configured to monitor the output signal provided by stage 405. Status module 420 uses the characteristics of the output signal to determine the completion status of stage 405. For example, status module 420 can monitor changes in the output signal generated by stage 405. The status module 420 determines that the stage 405 is processing the current task if the value of the output signal is changing. In some variations, status module 420 determines that stage 405 has completed processing of the current task if the value of the output signal is steady state or changing at a rate below the threshold.

  Portion 400 also includes modules 425 and 430 that provide and receive signals that are used to estimate the completion status of stage 405. Modules 425 and 430 are used to implement some embodiments of the modules 120, 125 and 150 to 152 shown in FIG. Some embodiments of module 425 provide status module 420 with a start signal 435 indicating that stage 405 has begun processing of the task using the input data stored in input register 410. The start signal 435 is provided at the same time as the start signal used by the stage 405 to start processing the input data stored in the input register 410. As described above, module 430 initiates monitoring of the output signal generated by stage 405 in response to start signal 435 to determine the completion status of stage 405. Status module 420 provides a signal to module 430 indicating the completion status of stage 405. For example, status module 420 asserts a logic low signal to logic module 430 while the completion status of stage 405 is "in process", and then in response to the completion status of stage 405 transitioning to "complete". And a logic high signal may be asserted to module 430.

  FIG. 5 is a block diagram of a portion 500 of an asynchronous pipeline that implements intermediate completion status detection in a replica critical path, according to some embodiments. Portion 500 includes stage 505 that accesses input data from input register 510 and provides output data to output register 515. Portion 500 is used in some embodiments of asynchronous pipeline 105 shown in FIG. In some variations, input register 510 and output register 515 are used to implement one or more of registers 121-124 shown in FIG. 1, and stage 505 is shown in stages 110-110 of FIG. 1. Used to implement the corresponding stage of 114.

  Stage 505 is associated with a replica critical path 520 that includes logic configured to replicate the timing of one or more critical paths within stage 505, such that replica critical path 520 is within stage 505. The processing of the input data is completed after an interval of time corresponding to the time required for the critical path to complete the processing of the input data. The replica critical path 520 shares some features with the replica critical path 320 shown in FIG. However, replica critical path 520 includes logic 525 (such as a register, flip flop, latch or other circuit) used to determine an intermediate completion status at a location between the beginning and the end of replica critical path 520. Therefore, it is different from the replica critical path 320. For example, logic 525 may include a register that stores the results generated by replica critical path 520 at a point during execution of processing on replica critical path 520.

  Portion 500 also includes modules 530 and 535 that provide and receive signals used to estimate the completion status of stage 505. Modules 530, 535 can be used to implement some embodiments of modules 120, 125, 150-152 shown in FIG. Some embodiments of module 530 provide start signal 540 to cause replica critical path 520 to begin processing input data. A start signal 540 is also provided to the logic 525. The start signal 540 is provided at the same time as the start signal used by the stage 505 to start processing the input data stored in the input register 510. The logic 525 may determine the intermediate completion status of the replica critical path 520 in response to the initiation signal 540, for example, by monitoring the characteristics of the signal generated in the logic 525 by the replica critical path 520. For example, the logic 525 may detect the particular pattern of the signal received by the logic 525 or may determine that the data stored in the register associated with the logic 525 has reached steady state. Can be determined that the operation on the input data has been completed. Logic 525 may provide a signal to module 535 indicating an intermediate completion status of replica critical path 520. Add latency to the intermediate completion time determined by logic 525 for replica critical path 520 to compensate for the difference between the estimated intermediate completion time of stage 505 and the actual intermediate completion time, as described herein Or can be subtracted.

  The intermediate completion status is used by a stage controller (such as stage controllers 161-164) to change the operating speed of a portion of stage 505. For example, the stage controller may use a completion status generated by logic 525 to cause a portion of stage 505 that precedes logic 525 (eg, a circuit upstream of logic 525) or a subsequent stage 505 of logic 525. The speed of operation of some (eg, circuitry downstream of logic 525) can be changed. Although a single logic 525 is shown in FIG. 5, some embodiments of replica critical path 520 include additional completion status logic that can be located at different locations within replica critical path 520. Further, in some embodiments, the logic for detecting one or more intermediate completion status of replica critical path 520 may be the entire replica critical path 520, such as the logic implemented in module 330 shown in FIG. Combined with logic to detect completion status.

  FIG. 6 is a block diagram of a portion 600 of an asynchronous pipeline that implements intermediate completion status detection in accordance with some embodiments. Portion 600 includes a stage 605 that accesses input data from input register 610 and provides output data to output register 615. Portion 600 is used in some embodiments of asynchronous pipeline 105 shown in FIG. In some variations, the input register 610 and the output register 615 are used to implement one or more of the registers 121-124 shown in FIG. 1, and the stage 605 is the stage 110-110 shown in FIG. Used to implement the corresponding stage of 114.

  Stage 605 includes an area 620 of the circuit that performs part of the tasks assigned to stage 605 and an area 625 of the circuit that performs another part of the tasks assigned to stage 605. A set of registers 630 is implemented between regions 620 and 625. Register 630 is configured to store the results of the processing performed by region 620 and provide the results to region 625 for additional processing at stage 605. The register 630 is connected to a status monitor 635 configured to monitor the output signal provided to the register 630 by the area 620. Status module 635 uses the characteristics of the values stored in register 630 to determine the completion status of area 620. For example, status module 635 monitors for changes in the output signal generated by area 620, and area 620 is processing the current task if the value of the output signal stored in register 630 is changing. It can be determined that Also, some variations of status module 635 may assume that region 620 has completed processing of the current task if the value stored in register 630 is steady state or changing at a rate below a threshold. It can be determined.

  Also, portion 600 includes modules 640 and 645 that provide and receive signals used to estimate the intermediate completion status of stage 605. Modules 640 and 645 are used to implement some of the embodiments of modules 120, 125 and 150-152 shown in FIG. Some embodiments of module 640 provide start signal 650 to status module 635 indicating that stage 605 has begun processing the task using the input data stored in input register 610. The start signal 650 is provided at the same time as the start signal used by the stage 605 to start processing the input data stored in the input register 610. As described above, status module 635 initiates monitoring of the output signal provided to register 630 in response to start signal 650 to determine the completion status of region 620. Status module 635 then provides signal 655 to module 645 indicating the completion status of region 620. For example, status module 635 asserts a logic low signal to module 645 while the completion status of region 620 is "in process", and then in response to the completion status of region 620 transitioning to "complete". A logic high signal can be asserted to module 645.

  The intermediate completion status is used by the stage controller (such as stage controllers 161-164 shown in FIG. 1) to change the speed of operation of regions 620, 625 of stage 605. For example, the stage controller can use the completion status generated by status module 635 to change the operating speed of region 620, region 625, or a combination thereof. Although a single set of registers 630 and a single status module 635 are shown in FIG. 6, some embodiments of the portion 600 may have additional completion status located at different locations within the stage 605. Include logic Further, in some embodiments, the logic for detecting one or more intermediate completion status of regions 620, 625 may be complete for stage 605, such as the logic implemented in module 420 shown in FIG. Combined with logic to detect status.

  FIG. 7 is a block diagram of a portion 700 of an asynchronous pipeline that implements parallel processing, according to some embodiments. Portion 700 includes a high speed stage 705 that completes the task at a relatively high rate or speed, and a low speed stage 710 that completes the task at a relatively low rate or speed. Portion 700 is implemented in some embodiments of asynchronous pipeline 105 shown in FIG. In some variations, each of stages 110-114 shown in FIG. 1 represents multiple stages operating in parallel. For example, stages 111 represent at least one pair of stages configured to perform multiplication operations on different input data in parallel. One stage can complete the task at a relatively high rate or rate, and one other stage can complete the task at a relatively low rate or rate.

  The asynchronous pipeline starts execution of parallel stages 705 and 710 at fork 715, and the operation results of parallel stages 705 and 710 are combined at join 720. Parallel branches can not complete join 720 until both execution of tasks by parallel stages 705 and 710 are complete. Thus, one or more stage controllers (such as stage controllers 161-164 shown in FIG. 1) coordinate the operation of stages 705, 710 based on their completion status. For example, the stage controller can perform the operation of the relatively fast stage 705, slow down the operation of the relatively slow stage 710, or a combination of these modifications, thereby causing both stages 705 to operate. , 710 complete in a time approximately equal to the goal completion time of the parallel stages 705, 710.

  FIG. 8 is a flow diagram of a method 800 of changing the operating speed of stages in an asynchronous pipeline, according to some embodiments. Method 800 is implemented in some embodiments of the processing system 100 shown in FIG. The stages receive input data generated by the left adjacent stage and generate output data to be provided as input data to the right adjacent stage. Some embodiments of the stage correspond to the stage 112 shown in FIG. In this case, the left adjacent stage corresponds to the stage 111 shown in FIG. 1 and the right adjacent stage corresponds to the stage 113.

  At block 805, the stage controller (such as the stage controller 162 shown in FIG. 1) accesses information indicating the completion status of the stage. The completion status may include information indicating that the stage has not completed the task being executed, in which case the completion status of the stage is "in process". Also, the completion status may include information indicating that the stage has completed the task, in which case the completion status of the stage is "done". Additionally, the completion status may include information indicating an intermediate completion status associated with a portion or region of the stage, as described herein.

  At block 810, the stage controller accesses information indicating the completion status of the left adjacent stage. The completion status may include information indicating that the left adjacent stage has not yet completed the task being executed, in which case the completion status of the left adjacent stage is “in process”. Also, the completion status may include information indicating that the left adjacent stage has completed the task, in which case the completion status of the left adjacent stage is “Done”. Additionally, the completion status may include information indicating an intermediate completion status associated with a portion or region of the left adjacent stage, as described herein. Some embodiments of the stage are not associated with the left adjacent stage of the asynchronous pipeline. For example, the stage 110 shown in FIG. 1 is not associated with the left adjacent stage, and in this case, block 810 can be bypassed.

  At block 815, the stage controller accesses information indicating the completion status of the right adjacent stage. The completion status may include information indicating that the right adjacent stage has not yet completed the task being executed, in which case the completion status of the right adjacent stage is "in process". Also, the completion status may include information indicating that the right adjacent stage has completed the task, in which case the completion status of the right adjacent stage is "completed". Additionally, the completion status may include information indicating an intermediate completion status associated with a portion or region of the right adjacent stage, as described herein. Some embodiments of the stage are not associated with the right adjacent stage of the asynchronous pipeline. For example, the stage 114 shown in FIG. 1 is not associated with the right adjacent stage, which may bypass block 815 in this case.

  At block 820, the stage controller is based on the stage's completion status, the completion status of the left adjacent stage (if available), and the completion status of the right adjacent stage (if available). Change the operating speed. As described herein, the speed of operation can be changed by changing the buffer drive strength or voltage applied to the stage or a portion of the stage.

  In some embodiments, the above-described apparatus and techniques, such as the asynchronous pipeline described above with reference to FIGS. 1-8, comprise one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips) In a system comprising Electronic design automation (EDA) and computer aided design (CAD) software tools are typically used to design and manufacture these IC devices. These design tools are usually represented as one or more software programs. One or more software programs are computer configured to operate with code representing a circuit of one or more IC devices to perform at least a portion of a process for designing or adapting a manufacturing system for manufacturing a circuit. Contains code that is executable by a computer system to operate the system. The code can include instructions, data, or a combination of instructions and data. Software instructions representative of design tools or manufacturing tools are typically stored on a computer readable storage medium accessible by a computing system. Similarly, code representing one or more phases of IC device design or manufacture may be stored on the same computer readable storage medium or different computer readable storage medium, from the same computer readable storage medium or from different computer readable storage medium It may be accessed.

  Computer readable storage media may include any storage media or combination of storage media accessible by a computer system in use to provide instructions and / or data to the computer system. Such storage media include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray (R) discs), magnetic media (e.g., floppy discs, magnetic) Tape, magnetic hard drive) volatile memory (eg random access memory (RAM), cache) non-volatile memory (eg read only memory (ROM) flash memory) or micro electromechanical system (MEMS) based Storage media may be included. The computer readable storage medium may be embedded in a computer system (e.g. system RAM or ROM) or fixedly attached to the computer system (e.g. magnetic hard drive) or may be a computer system (e.g. optical) It may be removably attached to a disk or universal serial bus (USB) based flash memory, or connected to a computer system (eg network accessible storage (NAS)) via a wired or wireless network It is also good.

  In some embodiments, some aspects of the above techniques may be implemented by one or more processors of a processing system executing software. The software is stored in non-transitory computer readable storage medium or includes one or more sets of executable instructions tangibly embodied on non-transitory computer readable storage medium. The software may include instructions and specific data that, when executed by the one or more processors, operate the one or more processors to perform one or more aspects of the above techniques. Non-transitory computer readable storage media may include, for example, magnetic or optical disk storage devices, solid state storage devices such as flash memory, cache, random access memory (RAM), or other non-volatile memory devices etc. it can. Executable instructions stored in a non-transitory computer readable storage medium may be source code, assembly language code, object code, or other instruction format interpretable or executable by one or more processors.

  In addition to the ones described above, not all activities or elements described in the summary description may be required, and part of a particular activity or device may not be required, and one or more additional activities It should be noted that it may be implemented and one or more additional elements may be included. Furthermore, the order in which activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, one of ordinary skill in the art will understand that various changes and modifications can be made without departing from the scope of the present invention as set forth in the claims. Accordingly, the specification and drawings are to be considered in an illustrative rather than a restrictive sense, and all of these variations are intended to be included within the scope of the present invention.

  Benefits, other advantages and solutions to problems have been described above with regard to specific embodiments. However, benefits, advantages, solutions to problems, and features that may benefit or manifest any benefits, advantages, or solutions are essential, essential, or important to any or all of the claims. It is not interpreted as an essential feature. Further, the disclosed invention is a method apparent to those skilled in the art having the benefit of the teachings herein, and can be modified and practiced in a different but similar manner, and thus the specific embodiments described above. Is merely an example. The details of the arrangements or designs presented herein, other than as described in the claims below, are not limiting. Thus, it is apparent that the particular embodiments described above may be altered or modified and that all such variations are considered to be within the scope of the disclosed invention. Accordingly, the protection sought herein is as set forth in the claims below.

Claims (15)

An asynchronous pipeline (105) comprising a first stage (112) and at least one second stage (111);
A controller (162) for providing a control signal to the first stage indicating a change in the operating speed of the first stage, the change being a completion status of the first stage and the at least one second stage. And (d) a controller (162) determined based on the comparison with the at least one completion status.
Device (100). The at least one second stage comprises at least one of a left stage (111) generating input data for the first stage and a right stage (113) receiving output data generated by the first stage. Have one,
The device of claim 1. The controller is configured to provide the first stage with a control signal indicating a change in operating voltage applied to the first stage, wherein the changing of the operating voltage is performed by the first stage and the at least one. Determined based on the comparison of completion status with two second stages,
The device of claim 1. At least one buffer (226) for driving signals between portions of the first stage, the controller controlling signals indicating at least one change in at least one drive strength of the at least one buffer; And / or at least one change in the at least one drive strength is determined based on a comparison of completion status of the first stage and the at least one second stage. Further comprising a buffer (226),
The device of claim 1. The plurality of modules (150, 151) for determining the completion status of the first stage and the at least one second stage,
The device of claim 1. The plurality of modules monitor output signals generated by the first stage and the at least one second stage in response to initiation of execution of a task by the first stage and the at least one second stage. Determine the completion status of the first stage and the at least one second stage by
The device of claim 5. A first replica critical path (320) corresponding to the first stage critical path;
At least one second replica critical path associated with the at least one second stage, the plurality of modules simultaneously with the start of execution of a task by the first stage and the at least one second stage According to one replica critical path and an input signal provided to the at least one second replica critical path, based on an output signal generated by the first replica critical path and the at least one second replica critical path At least one second replica critical path determining the completion status of the first stage and the at least one second stage;
The device of claim 5. At least one look-up table (235) indicating estimated completion times for different instruction types, instruction opcodes or characteristics of the input data, the completion status of the first stage and the at least one second stage being: At least one look determined based on a completion time indicated by at least one of a type of an instruction associated with a task performed by one stage and the at least one second stage, an instruction opcode or a characteristic of input data Further comprising an up table (235),
The device of claim 1. The change is determined based on a partial completion status determined at a predetermined position in the first stage and the at least one second stage.
The device of claim 1. Comparing the completion status of the first stage (112) of the asynchronous pipeline (105) with the completion status of at least one second stage (111) of the asynchronous pipeline;
Providing (820) a control signal to the first stage indicating a change in the operating speed of the first stage, wherein the change is determined based on the comparison.
Method. The at least one second stage comprises at least one of a left stage (111) generating input data for the first stage and a right stage (113) receiving output data generated by the first stage. Have one,
11. The method of claim 10. Further comprising determining a change in operating voltage applied to the first stage based on the comparison;
Providing the control signal may include providing a control signal to the first stage indicating a change in operating voltage applied to the first stage.
11. The method of claim 10. Determining at least one change in at least one drive strength used by at least one buffer to drive a signal between portions of the first stage, the at least one drive strength at least one Further including that the change is determined based on the comparison;
Providing the control signal includes providing a control signal indicative of at least one change in drive strength of at least one of the at least one buffer.
11. The method of claim 10. Further comprising determining a completion status of the first swage and the at least one second stage using a plurality of modules associated with the first stage and the at least one second stage,
11. The method of claim 10. Determining the completion status may include outputting an output signal generated by the first stage and the at least one second stage in response to initiation of execution of a task by the first stage and the at least one second stage. Including monitoring,
The method of claim 14.

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