JP2013140884A - Lsi design method - Google Patents

Abstract

A retention flip-flop cell in which only a slave side of a master-slave type can maintain power supply and retain data in the low power consumption mode in an LSI design method for stopping power supply to some circuits in the low power consumption mode There is provided a design method capable of arbitrarily synthesizing a normal-phase and a reverse-phase retention flip-flop using only one type.
A netlist is synthesized by mapping a retention flip-flop based on an inputted power supply specification to a flip-flop of a logic circuit synthesized based on an inputted RTL. Referring to the cell library provided with the positive phase clock fixed cell and the reverse phase clock fixed cell, the synthesized netlist is analyzed to determine the clock phase of the retention flip-flop, and based on the result, the positive phase or reverse phase is determined. A phase clock fixed cell is inserted into the clock input of the retention flip-flop of the netlist.
[Selection] Figure 1

Description

  The present invention particularly relates to a semiconductor integrated circuit (LSI) design method in which power supply to some circuits is cut off in a low power consumption mode and a state or data that needs to be held is held in a retention flip-flop during that period. Further, the present invention relates to a technique that is effective even when a normal phase and a reverse phase retention flip-flop are mixed.

  As semiconductor integrated circuits (LSIs) are miniaturized, leakage current has become remarkable. One of the effective techniques for reducing the power consumption of an LSI is a technique for cutting off the power supply to a part of the LSI in a low power consumption mode such as a sleep mode. In sleep mode, the clock is stopped and computation processing is stopped to wait, so there is no dynamic power consumption associated with computation processing, etc., so static power consumption mainly due to leakage current is significant. Become. Therefore, a technique for shutting off the power supply is effective particularly in the sleep mode, but it is necessary to retain the state and data required when the mode is returned from the sleep mode to the normal operation mode.

  Therefore, a flip-flop having a portion connected to a power supply that does not cut off power supply even during the sleep mode is provided, and a technology for holding a state or data that needs to be held even during the sleep mode is adopted. However, it is common. Such a flip-flop is called a retention flip-flop.

  Patent Document 1 discloses various circuit examples of a retention flip-flop. In general, a flip-flop is configured by cascading a master latch and a slave latch. The master latch is a level sense latch that captures data during the low level period of the clock and holds it during the high level period. The slave latch is also a level sense latch, which captures the output of the master latch while the clock is high and holds it during the low level. As a result, a so-called positive-phase flip-flop that captures data at the rising edge of the clock can be configured. The flip-flop disclosed in Patent Document 1 has a circuit configuration in which the power supply of the master latch is shut off during the sleep mode, and the power supply of the slave latch is maintained even during the sleep mode. During the sleep mode, data in the master latch is lost, but data in the slave latch is retained by maintaining the clock at a low level. Furthermore, since the slave latch is configured using a transistor having a high threshold voltage, the leakage current at the time of data retention is more effectively suppressed.

  On the other hand, in addition to the normal-phase flip-flops as described above, so-called reverse-phase flip-flops that capture data at the falling edge of the clock are also used. There are many logic circuits that use a mix of logic.

  Patent Document 2 discloses a logic circuit including both a normal-phase retention flip-flop and a reverse-phase retention flip-flop. That is, the positive-phase retention flip-flop holds data while the clock is at a low level, and the reverse-phase retention flip-flop holds data when the clock is at a high level. During sleep mode, the clock supplied to each retention flip-flop is maintained at an appropriate voltage level. A circuit that maintains the clock low during sleep mode is connected to the positive-phase retention flip-flop, and a circuit that maintains the clock high during sleep mode is connected to the negative-phase retention flip-flop. Has been.

Special table 2008-535300 gazette JP 2011-205355 A

  In general, a logic circuit is designed by a high-level logic description such as RTL (Register Transfer Level), and by logic synthesis using a cell library prepared in a design apparatus such as CAD (Computer Aided Design).

  In logic circuit design using the technique disclosed in Patent Document 2, it is necessary to prepare each of a normal-phase retention flip-flop and a reverse-phase retention flip-flop in the cell library.

  In many cases, flip-flop logic cells prepared by a design apparatus such as CAD do not distinguish between positive and negative phases. The normal-phase flip-flop is synthesized by connecting a clock having the same phase as the clock supply source, and the reverse-phase flip-flop is synthesized by connecting the clock supply source and the anti-phase clock. Only the positive-phase flip-flop is used, and the operation of the flip-flop is determined depending on which of the positive-phase clock and the reverse-phase clock is connected.

  For such a design, a flip-flop that holds data in the sleep mode only by a slave latch as described in Patent Document 1 cannot be applied. In the sleep mode, the normal phase clock is fixed at the low level in the clock generation source, and the reverse phase clock is inverted, and is fixed at the high level. In the flip-flop to which the reverse phase clock is connected, the data is held in the master latch, and the slave latch is taking in, but not holding it. When the power supply is cut off in this state, the master latch loses power supply, loses the retained data, and the slave latch has not yet reached the state of retaining the data, so the correct data is not retained. In order to hold the value of the flip-flop connected to the reverse phase clock, a flip-flop that maintains the power supply of the master latch in the sleep mode is required.

  Furthermore, there is a circuit in which the phase of the clock changes depending on the operation mode. In this case, it is not possible to properly hold data when the power is shut down by only maintaining the power supply of only the latch of either the master or the slave in the sleep mode.

  Two countermeasures are conceivable as countermeasures.

  The first countermeasure is to maintain the power supply of both the master latch and the slave latch during the sleep mode. As a result, appropriate data is held in either the master latch or the slave latch regardless of which clock phase is fixed, so flip-flop cells that do not distinguish between positive and negative phases are used to reverse the positive and negative phases. A phase flip-flop function can be configured. However, in this case, the leakage current is almost doubled compared to the flip-flop that maintains the power supply of only one latch during the sleep mode, and the cell area is increased because it is configured using a transistor having a high threshold voltage. is there.

  A second countermeasure is to add a state holding latch or flip-flop separately from the master latch and the slave latch. However, even in this case, there is a problem that the cell area increases.

  As described above, using one of the master latch or slave latch with a retention flip-flop cell that has a data retention function by maintaining the power supply in the sleep mode, together with a positive-phase retention flip-flop, a reverse-phase clock and variable phase The prior art is insufficient to construct a retention flip-flop connected with a clock. In the case of a new design, such a flip-flop can be designed not to retain. However, when diverting existing design assets, such as IP (Intellectual Property) -based design, or when purchasing and using design data, these flip-flops are identified and excluded from retention. It is difficult to do. Since it is difficult for a designer who uses IP to specify a flip-flop to be retained, all flip-flops may be targeted for retention. Further, in the case of the purchased IP, there is a case where it is not permitted in the contract to modify the RTL, and the flip-flop excluded from the retention target cannot be appropriately changed.

  An object of the present invention is to use only one type of retention flip-flop cell having a data holding function by maintaining power in a low power consumption mode such as a sleep mode in only one of a master latch and a slave latch, and a positive phase retention flip-flop And an anti-phase retention flip-flop and a phase variable retention flip-flop of a normal phase and an anti-phase can be arbitrarily configured.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, in the LSI design method, the cell library includes a retention flip-flop cell, a positive phase clock fixed cell, and a reverse phase clock fixed cell.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, using only one type of retention flip-flop cell having a data holding function by maintaining power in a low power consumption mode such as a sleep mode in only one of the master latch and the slave latch, The phase retention flip-flop and the phase variable retention flip-flop of the normal phase and the reverse phase can be arbitrarily configured.

FIG. 1 is a diagram showing a flow of an LSI design method according to a typical embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a retention flip-flop cell. FIG. 3 is a circuit diagram illustrating an example of a positive phase clock fixed cell and a reverse phase clock fixed cell. FIG. 4 is an example of an LSI circuit including retention flip-flops of positive and negative phases. FIG. 5 is a timing chart for explaining the operation of the LSI shown in FIG. FIG. 6 shows an example of an LSI circuit including a phase variable retention flip-flop.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <LSI design method including clock fixed cells for normal phase and reverse phase>
An LSI design method (70) for generating an LSI netlist (4) in which power supply to a part of circuits is stopped in a low power consumption mode and data is retained by a retention flip-flop, and is configured as follows. The

  The cell library (1) includes a retention flip-flop cell (10), a first clock fixed cell (20), and a second clock fixed cell (30).

  The retention flip-flop cell includes a clock input terminal (11), a data input terminal (12), and a data output terminal (13), and includes a master latch (14) and a slave latch (15). Holds data to be output to the data output terminal when the clock input terminal is at the first voltage level during the low power consumption mode.

  The first clock fixed circuit cell includes a clock input terminal (21) and a clock output terminal (23) to the retention flip-flop, and the clock input terminal is the first when the transition to the low power consumption mode is made. A circuit (24) for fixing the clock output terminal to the first voltage level during a period of the voltage level and holding the clock output terminal at the first voltage level during the low power consumption mode; Yes.

  The second clock fixed circuit cell includes a clock input terminal (31) and a clock output terminal (33) to the retention flip-flop, and the clock input terminal is the second when the transition to the low power consumption mode is made. A circuit (35) for fixing the clock output terminal to the first voltage level after ½ clock period of a period at the voltage level and holding the clock output terminal at the first voltage level during the low power consumption mode. It is comprised including.

  As a result, only one type of retention flip-flop cell that has a data retention function by maintaining power in the low power consumption mode such as the sleep mode is used for the slave latch, and the normal-phase retention flip-flop and the reverse-phase retention flip-flop. In addition, it is possible to arbitrarily configure a retention flip-flop having a variable phase between the normal phase and the reverse phase.

[2] <Retention flip-flop cell circuit>
The LSI design method according to Item 1, which is configured as follows.

  In the retention flip-flop cell, the master latch is connected to a power supply line (42) in which power supply is cut off during the low power consumption mode.

  In the retention flip-flop cell, the slave latch is connected to a power supply line (41) in which power supply is maintained during the low power consumption mode, and when the clock input terminal is at the first voltage level, the data When the data output to the output terminal is held and the clock input terminal is at the second voltage level, the output of the master latch is captured.

  As a result, only one type of retention flip-flop cell having a data holding function by maintaining the power supply in the sleep mode only in the slave latch is used, and the positive-phase retention flip-flop, the reverse-phase retention flip-flop, and the reverse of the normal phase. A phase-variable retention flip-flop can be arbitrarily configured.

[3] <Clock fixed cell circuit>
The LSI design method according to Item 1 or 2, which is configured as follows.

  The first clock fixed circuit cell further includes a retention control signal input terminal (22), and includes a latch (24) for holding data during the low power consumption mode, and the clock input terminal is a first clock input terminal. When at the voltage level, the logic level input from the retention control signal input terminal is transferred to the latch.

  The second clock fixed circuit cell further includes a retention control signal input terminal (32), and includes a latch (34) and a flip-flop (35) for holding data during the low power consumption mode. When the clock input terminal is at the second voltage level, the logic level input to the retention control signal input terminal is transferred to the latch, and the clock input terminal transitions from the first voltage level to the second voltage level. Sometimes the output of the latch is transferred to the flip-flop.

  Thus, each of the first and second clock fixed cells can be controlled by the retention control signal.

[4] <Clock fixed cell insertion for each of normal phase clock and reverse phase clock>
Item 4. The LSI design method according to Item 1, Item 2, or Item 3, wherein the LSI design method includes the following steps.

  A logic circuit including a plurality of flip-flops is generated from the high-level logic description (2) (step 72).

  Thereafter, the retention flip-flop cell is technology-mapped to all or a part of the plurality of flip-flops to form a retention flip-flop (step 74).

  Thereafter, the clock phase of the clock connected to the clock input terminal of the retention flip-flop is analyzed (step 75).

  When the clock phase is positive, the first clock fixed circuit cell is inserted into the input portion of the clock input terminal of the retention flip-flop of the logic circuit (step 76).

  When the clock phase is reversed, the second clock fixed circuit cell is inserted into the input portion of the clock input terminal of the retention flip-flop of the logic circuit (step 76).

  Thereafter, the logic circuit is generated as the net list (step 77).

  As a result, the first or second clock fixed cell is automatically inserted into the netlist appropriately according to the phase of the clock driving the retention flip-flop.

[5] <Retention flip-flop specified by power supply specification>
4. The LSI design method according to item 4, wherein a power supply specification (3) is further input, and a retention flip-flop that should hold data in the low power consumption mode is specified from the plurality of flip-flops based on the power supply specification (Step 73).

  As a result, flip-flops that map retention flip-flops can be limited to those requiring retention.

2. Details of Embodiments Embodiments will be further described in detail.

[First Embodiment] Flow of LSI Design Method FIG. 1 is a diagram showing a flow of an LSI design method according to a typical embodiment of the present invention.

  First, a conventional design method for realizing state (data) retention during the low power consumption mode will be described.

  Elaboration (step 71) and logic optimization (step 72) are performed on the input high-level logic description such as RTL2, and then the retention target flip-flop (F / F) is extracted (step 73). The retention target flip-flop is extracted based on the power supply specification 3. The power supply specification 3 describes information such as which flip-flops are to be retained or which control signals are to be subjected to retention control. Based on the information, the flip-flops to be retained are described. Are extracted. The power supply specification 3 can be described in a format such as CPF (Common Power Format) or UPF (Unified Power Format).

  Next, the retention flip-flop cell 10 is mapped to the extracted flip-flop to be retained with reference to the cell library 1 (step 74), and is output as the netlist 4 (step 77).

  According to the conventional design method, when the normal-phase and negative-phase flip-flops are mixed, or when the normal-phase and negative-phase flip-flops exist depending on the mode, the method described above is used. Without it, it could not be designed properly. That is, the normal-phase and reverse-phase retention flip-flop cells are provided in the cell library in advance, and the reverse-phase and phase-variable flip-flops are specified by RTL and appropriately mapped. Alternatively, a retention flip-flop cell that functions both for the normal phase and for the reverse phase needs to be provided in the cell library in advance.

  Therefore, in a typical embodiment of the present invention, the cell library 1 is further provided with a normal phase clock fixed cell 20 and a reverse phase clock fixed cell 30 in advance. First, as in the conventional design method, elaboration (step 71) and logic optimization (step 72) are performed on the input high-level logic description such as RTL2, and then the flip-flop (F / F) to be retained ) Is extracted (step 73).

  In technology mapping (step 74), the retention flip-flop cell 10 is mapped to the extracted retention target flip-flop with reference to the cell library 1. The retention flip-flop cell 10 may be a positive-phase retention flip-flop cell.

  Next, clock phase analysis is performed (step 75). In the clock phase analysis, the logic on the clock line is analyzed to extract a reverse phase clock or a phase variable clock.

  Next, a clock fixed cell is inserted (step 76). In the insertion of the clock fixed cell (step 76), it is determined whether or not the retention target flip-flop extracted in step 73 is connected to the extracted clock line. If they are connected, an appropriate clock fixed cell is inserted in accordance with the clock phase obtained by the clock phase analysis in step 75 for each clock. If the positive phase clock is connected to the retention target flip-flop extracted in step 73, the normal phase clock fixed cell 20 is inserted, and if the reverse phase clock is connected, the negative phase clock fixed cell 30 is inserted.

  Finally, the completed netlist 4 is output (step 77).

[Embodiment 2] Cell Circuit Example FIG. 2 is a circuit diagram showing an example of a retention flip-flop cell 10 included in the cell library 1, and FIG. 3 shows a normal phase clock fixed cell 20 and a reverse phase clock fixed. 3 is a circuit diagram showing an example of a cell 30. FIG.

  The retention flip-flop cell 10 shown in FIG. 2 includes a clock input terminal 11, a data input terminal 12, and a data output terminal 13, and includes a master latch 14 and a slave latch 15. Data input from the data input terminal 12 is taken into the master latch 14 when the clock input terminal 11 is at a low level and is held at a high level. The output of the master latch 14 is taken into the slave latch 15 when the clock input terminal 11 is at a high level, held during a low level period, and output to the data output terminal 13 of the cell. In the normal operation mode, it functions as a rising edge sensitive flip-flop for the input clock.

  The master latch is connected to the power supply line 42 that is cut off in the low power consumption mode, and the slave latch is connected to the power supply line 41 that is maintained in the low power consumption mode. The master latch 14 is not able to hold data because the power supply is cut off in the low power consumption mode, but the slave latch 15 can hold data because the power supply is maintained. The slave latch 15 maintains power supply even in the low power consumption mode. However, if the clock is at a high level, the power supply is cut off, and the data output from the master latch 14 in which data to be retained is lost is captured. The clock must be fixed at a low level.

  The slave latch is preferably configured using a transistor having a higher threshold value than that of the master latch. In the low power consumption mode, the master latch does not generate a leakage current because the power supply is cut off, but the slave latch generates a leakage current because the power is maintained. By using a high-threshold transistor, leakage current can be kept low even when power supply is maintained. In general, when a circuit is configured using transistors having a high threshold value, the cell area becomes large. Therefore, it should be kept to a minimum. With respect to the retention flip-flop cell, it is preferable that only a slave latch whose power is maintained even in the low power consumption mode is configured using a high threshold transistor.

  A positive phase clock fixed cell 20 shown in FIG. 3A includes a clock input terminal 21, a retention control signal input terminal 22, and a clock output terminal 23. The negative latch 24 holds data when the clock is at a high level. An AND gate 26 is used. While the retention control signal input terminal 22 is at a high level, the clock input to the clock input terminal 21 is output to the clock output terminal 23 as it is. After the retention control signal input terminal 22 changes to low level, the clock output terminal 23 is fixed to low level at the timing when the clock input to the clock input terminal 21 becomes high level. The negative latch 24 and the AND gate 26 are connected to a power supply 41 that maintains power supply even in the low power consumption mode. During the low power consumption mode, the negative latch 24 holds data and sets the clock output terminal 23 to the low power consumption mode. Fix to level.

  3B includes a clock input terminal 31, a retention control signal input terminal 32, and a clock output terminal 33. The positive latch 34 holds data when the clock is at a low level. A flip-flop 35 and an AND gate 36 are included. While the retention control signal input terminal 32 is at the high level, the clock input to the clock input terminal 31 is output to the clock output terminal 33 as it is. After the retention control signal input terminal 32 changes to the low level, the clock output terminal 33 is set to the low level with a delay of a half cycle (1/2 clock period) from the timing when the clock input to the clock input terminal 31 becomes the low level. Fix to level. The positive latch 34, the flip-flop 35, and the AND gate 36 are connected to a power supply 41 that maintains power supply even in the low power consumption mode. During the low power consumption mode, the positive latch 34 holds data and outputs a clock. The terminal 33 is fixed at a low level.

  In this embodiment mode, the case where the retention flip-flop holds data only by the slave latch in the low power consumption mode and the clock needs to be fixed at a low level in order to hold the data has been described. Is not limited. In the case of using a retention flip-flop that holds data only by the master latch instead of the slave latch, other combinations may be used, such as when the clock needs to be fixed at a high level for holding. By appropriately matching the logic level of the clock that the retention flip-flop should fix to hold data in the low power consumption mode and the logic level that the clock fixing cell for the positive phase and the reverse phase should fix the clock , Can be implemented in any combination.

[Third Embodiment] Circuit Example 1 of a Designed LSI (Mixed Normal Phase and Reverse Phase Flip-Flops)
Next, an example of an LSI circuit designed by the design method described above will be described.

  FIG. 4 is an example of an LSI circuit including retention flip-flops of positive and negative phases.

  The clock clk1 (46) supplied to the retention flip-flops 10-1 and 10-2 is a so-called positive phase clock in phase with the clock clk44, and is supplied to the retention flip-flops 10-3 and 10-4. The clock clk2 (47) is a so-called opposite phase clock having the same phase as the clock clkb45 obtained by inverting the clock clk44. In the retention flip-flops 10-1, 10-2, 10-3, and 10-4, the retention flip-flop cells 10 are uniformly mapped regardless of whether the clock to be driven is in the normal phase or the reverse phase. . The retention flip-flop cell 10 includes a master latch and a slave latch. The master latch is connected to a power supply line 42 that is cut off in power supply during the low power consumption mode, and the slave latch is in the low power consumption mode. Are also connected to a power line 41 that maintains power supply.

  The clock signal lines supplied to the positive-phase retention flip-flops 10-1 and 10-2 are inserted with the positive-phase clock fixed cell 20-1, and the reverse-phase retention flip-flops 10-3 and 10-2 are inserted. The clock fixed line 30-1 for reverse phase is inserted in the clock signal line supplied to -4. Retention control signal retb43, which is a control signal for causing the retention flip-flop to retain data to be retained during the low power consumption mode, is provided in the positive-phase and reverse-phase clock fixed cells 20-1 and 30-1. It is connected. The positive-phase and negative-phase clock fixed cells 20-1 and 30-1 are connected to a power supply line 41 that maintains power supply even during the low power consumption mode.

  FIG. 5 is a timing chart for explaining the operation of the LSI shown in FIG.

  The retention control signal retb is a control signal for causing the retention flip-flop to hold data to be held during the low power consumption mode. It is high level in normal operation mode, changes to low level before power supply is cut off in low power consumption mode, and returns to normal operation mode, after power supply is restored, it changes from low level to high level. Change.

  The clock clk is a so-called positive phase clock common to the entire LSI, and the clock clkb is an inverted clock thereof. Since the inverter to be inverted is connected to the power supply line 42 from which power supply is cut off during the low power consumption mode, the voltage level is indefinite during the period T5 to T8 in the low power consumption mode.

  The positive-phase clock fixed cell 20-1 outputs the clock clk as it is as the clock clk1 in the normal operation mode. When transitioning from the normal operation mode to the low power consumption mode, in response to the retention control signal retb changing to a low level at a time between T2 and T3, the clock clk1 starts from the next rising edge (time T3) of the clock clk. Is output at a fixed low level. When returning to the normal operation mode, in response to the retention control signal retb changing to a high level at a time between T8 and T9, the clock clk1 is the same as clk from the next rising edge of the clock clk (time T9). Output the clock.

  The reverse-phase clock fixed cell 30-1 outputs the inverted clock clkb as it is as the clock clk2 in the normal operation mode. When transitioning from the normal operation mode to the low power consumption mode, a half cycle delay from the next rising edge (time T3) of the clock clk in response to the retention control signal retb changing to a low level at a time between T2 and T3 From the time T4, the clock clk2 is fixed to the low level and output. When returning to the normal operation mode, in response to the retention control signal retb changing to a high level at a time between T8 and T9, a time T10 delayed by a half cycle from the next rising edge (time T9) of the clock clk. To output the same clock as clkb to the clock clk2. By delaying the half cycle, the low level can be fixed and released while the inverted clock clkb is at the low level. Therefore, no hazard pulse is generated in clk2.

  In the normal operation mode, the clocks clk1 and clk2 are the same clocks as the normal phase clock clk and the reverse phase clock clkb, respectively. Therefore, the retention flip-flops 10-1 and 10-2 driven by the clock clk1 are the positive phase flip-flops. The retention flip-flops 10-3 and 10-4 that function and are driven by the clock clk2 function as reverse-phase flip-flops. In the low power consumption mode, the clocks clk1 and clk2 are both fixed at a low level, so that the retention flip-flops 10-1, 10-2, 10-3, and 10-4 are slaves whose power supply is maintained. Data can be held on the latch side.

  As described above, the same retention flip-flop cell can be used as a normal-phase flip-flop by properly inserting the positive-phase clock fixed cell or the reverse-phase clock fixed cell according to the phase of the clock that drives the retention flip-flop. It can also be mapped as a reverse phase flip-flop. In addition, since the clock clk1 and clk2 are fixed at low level in the low power consumption mode, the same retention flip-flop cell is only on the slave latch side. However, it can be constituted by a cell having a relatively small area in which power supply is maintained.

[Embodiment 4] Circuit Example 2 of Designed LSI (Phase Variable Flip-Flop)
Next, another example of an LSI circuit designed by the design method described above will be described.

  FIG. 6 is a circuit example of an LSI including a so-called variable phase retention flip-flop in which the normal phase and the reverse phase are switched depending on the operation mode.

  The positive-phase retention flip-flops 10-1 and 10-2 and the positive-phase clock fixed cell 20-1 are the same as the LSI shown in FIG. The retention flip-flops 10-5 and 10-6 are so-called variable phase retention flip-flops that can be switched between the normal phase and the reverse phase depending on the operation mode. Based on the operation mode control signal mode 61, the phase of the clock that drives the retention flip-flops 10-5 and 10-6 is varied. Due to the function of the exclusive OR gate 62, the clock 63 is in the positive phase when the operation mode control signal mode 61 is at the low level, and the clock 63 is in the reverse phase when the operation mode control signal mode 61 is at the high level.

  A phase variable clock fixed cell 50 is inserted in the clock inputs of the retention flip-flops 10-5 and 10-6. The phase variable clock fixed cell 50 includes a clock input terminal 51, a retention signal input terminal 52, an operation mode control signal input terminal 53, and a clock output terminal 54. The phase variable clock fixed cell 50 includes a normal phase clock fixed cell 20-2, a reverse phase clock fixed cell 30-2, and a selector 55. One of the clock fixed cells functions according to the operation mode given by the mode 61. Let In an operation mode in which the mode 61 is at a low level and the input clock 63 is in the positive phase, the selector 55 selects the output of the positive phase clock fixed cell 20-2, passes through the clock output terminal 54, and passes through the retention flip-flop 10. The clock clk3 (64) for driving -5 and 10-6 is output. A normal phase clock is output to the clock clk3 (64) in the normal operation, and is fixed to a low level during the low power consumption mode. In this operation mode, the retention flip-flops 10-5 and 10-6 operate as positive-phase flip-flops, so that the positive-phase clock fixed cell 20 is selected in order to match it.

  In the operation mode in which the mode 61 is at a high level and the input clock 63 is in the opposite phase, the selector 55 selects the output of the opposite phase clock fixed cell 30-2 and passes through the clock output terminal 54 to the retention flip-flop 10-. The clock clk3 (64) for driving 5 and 10-6 is output. The clock clk3 (64) outputs a reverse phase clock in normal operation, and is fixed at a low level with a delay of a half cycle during the low power consumption mode. In this operation mode, since the retention flip-flops 10-5 and 10-6 operate as reverse-phase flip-flops, the reverse-phase clock fixed cell 30 is selected to match it.

  As described above, for phase variable retention flip-flops, a positive phase clock fixed cell and a negative phase clock fixed cell are combined to form a phase variable clock fixed cell and inserted. Alternatively, the same retention flip-flop cell as that for reverse phase can be mapped for phase variable.

  The phase variable clock fixed cell can be provided in the same cell library as a library cell independent of the normal phase clock fixed cell and the reverse phase clock fixed cell, or reverse to the normal phase clock fixed cell. It can also be defined as a macro cell that instantiates a phase clock fixed cell.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the description of the above embodiment, each signal has been described on the assumption that it is positive logic or negative logic. However, changes such as replacing a signal described as negative logic with a positive logic signal can be made as appropriate. Is.

  In the description of the above embodiment, only a simple circuit is illustrated for the retention flip-flop and the flip-flop and latch in the clock fixed cell, but it can be configured by another circuit having a logically equivalent function. . Further, it can be replaced with a flip-flop or a latch to which a reset function, a scan function, etc. are appropriately added.

  The “high level”, “low level”, “first voltage level”, and “second voltage level” used as the signal level need only be logic levels having information such as data and state, The voltage level can be arbitrarily determined in the design.

1 Cell library 2 RTL
3 Power supply specifications 4 Netlist 10 Retention flip-flop cell 10-1, 10-2 Positive phase retention flip-flop 10-3, 10-4 Reverse phase retention flip-flop 10-5, 10-6 Phase variable retention flip-flop 14 Master latch DESCRIPTION OF SYMBOLS 15 Slave latch 20 Positive phase clock fixed cell 24 Latch 30 Reverse phase clock fixed cell 34 Latch 35 Flip-flop 41 Power supply line 42 in which power supply is maintained in the low power consumption mode 42 Power supply is cut off in the low power consumption mode Power line 43 Retention control signal 44 Normal phase clock 45 Reverse phase clock 70 LSI design method 74 Technology mapping 75 Clock phase analysis 76 Insertion of clock fixed cell

Claims (5)

An LSI design method for generating an LSI netlist for stopping power supply to some circuits in a low power consumption mode and retaining data by a retention flip-flop,
With cell library,
The cell library includes a retention flip-flop cell, a first clock fixed cell, and a second clock fixed cell,
The retention flip-flop cell includes a clock input terminal, a data input terminal, and a data output terminal, and includes a master latch and a slave latch. The slave latch has a first clock input terminal during the low power consumption mode. Holds data to be output to the data output terminal when at a voltage level,
The first clock fixed circuit cell includes a clock input terminal and a clock output terminal to the retention flip-flop, and when the clock input terminal is in the first voltage level when transitioning to the low power consumption mode. A circuit that fixes the clock output terminal to the first voltage level and holds the clock output terminal at the first voltage level during the low power consumption mode;
The second clock fixed circuit cell includes a clock input terminal and a clock output terminal to the retention flip-flop. When the second clock fixed circuit cell transitions to the low power consumption mode, the clock input terminal is at a second voltage level. A circuit for fixing the clock output terminal to the first voltage level after a ½ clock period and holding the clock output terminal at the first voltage level during the low power consumption mode;
LSI design method. An LSI design method according to claim 1, wherein
In the retention flip-flop cell, the master latch is connected to a power line in which power supply is interrupted during the low power consumption mode.
In the retention flip-flop cell, the slave latch is connected to a power supply line that maintains power supply during the low power consumption mode, and when the clock input terminal is at the first voltage level, the slave output is connected to the data output terminal. Holds output data, and captures the output of the master latch when the clock input terminal is at the second voltage level;
LSI design method. An LSI design method according to claim 1, wherein
The first clock fixed circuit cell further includes a retention control signal input terminal, and includes a latch that holds data during the low power consumption mode, and the clock input terminal is at a first voltage level. Transferring the logic level input from the retention control signal input terminal to the latch;
The second clock fixed circuit cell further includes a retention control signal input terminal, and includes a latch for holding data during the low power consumption mode and a flip-flop, and the clock input terminal is at a second voltage level. The logic level input to the retention control signal input terminal is transferred to the latch when the clock input terminal transitions from the first voltage level to the second voltage level. Forward to
LSI design method. An LSI design method according to claim 1, wherein
The LSI design method includes:
Generate a logic circuit containing multiple flip-flops from the high-level logic description,
The retention flip-flop cell is mapped to all or a part of the plurality of flip-flops to form a retention flip-flop,
Analyzing the clock phase of the clock connected to the clock input terminal of the retention flip-flop,
When the clock phase is positive phase, the first clock fixed circuit cell is inserted into the input part of the clock input terminal of the retention flip-flop of the logic circuit,
When the clock phase is reversed, the second clock fixed circuit cell is inserted into the input part of the clock input terminal of the retention flip-flop of the logic circuit,
Generating the logic circuit as the netlist;
LSI design method. An LSI design method according to claim 4, comprising:
Enter more power specifications,
Based on the power supply specification, among the plurality of flip-flops, a retention flip-flop that should hold data in the low power consumption mode is specified.
LSI design method.

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