JP2019110247A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress local generation of excessive stress in an electrode having a laminated structure. A semiconductor device disclosed in the present specification includes a semiconductor substrate and an electrode provided on the surface of the semiconductor substrate and having a first metal layer, a second metal layer, and a third metal layer. In this semiconductor device, the first metal layer and the third metal layer are made of the same metal material. The second metal layer is located between the first metal layer and the third metal layer, and is composed of a metal material having a Young's modulus smaller than that of the metal materials of the first metal layer and the third metal layer. [Selection diagram] Fig. 2

Description

  The technology disclosed herein relates to a semiconductor device.

  Patent Document 1 discloses a semiconductor device. The semiconductor device includes a semiconductor substrate, and an electrode provided on the surface of the semiconductor substrate and having a first metal layer, a second metal layer, and a third metal layer. The first metal layer and the third metal layer are made of the same metal material. The second metal layer is located between the first metal layer and the third metal layer, and is made of a metal material different from the first metal layer and the third metal layer.

JP, 2011-249491, A

  When the second metal layer made of different metal materials is interposed between the first metal layer and the third metal layer made of the same metal material as in the electrode of the semiconductor device described above, The crystal grain size is smaller than that of a thick metal layer in which the first metal layer and the third metal layer are integrated. Thus, the fact that the grain size inside the metal layer is small, it has become apparent from Hall-Petch's law, to increase the yield strength (or yield stress) of the electrode.

  However, in the above-described configuration of the metal layer, the thermal expansion between the first metal layer and the third metal layer and the second metal layer is performed when heat treatment such as a sintering process is performed in the manufacturing process of the semiconductor device. The difference in coefficients may cause large local stresses. In particular, when a metal material such as titanium nitride (TiN) is used for the second metal layer, the difference in thermal expansion coefficient becomes large, and therefore, local excessive stress may occur. Furthermore, since titanium nitride is a high-strength material, formation of hillocks (concave and convex shapes) in the adjacent first metal layer and third metal layer is suppressed. Therefore, the release of stress due to the formation of hillocks is limited, and a higher stress is generated in the metal layer, and a cavity may be formed inside the first metal layer or the third metal layer.

  The present specification provides a technique for suppressing the occurrence of excessive stress locally in an electrode having the above-described laminated structure.

  The semiconductor device disclosed in this specification includes a semiconductor substrate, and an electrode provided on the surface of the semiconductor substrate and having a first metal layer, a second metal layer, and a third metal layer. In this semiconductor device, the first metal layer and the third metal layer are made of the same metal material. The second metal layer is located between the first metal layer and the third metal layer, and is made of a metal material having a smaller Young's modulus than the metal material of the first metal layer and the third metal layer.

  In the above-described semiconductor device, as the metal material of the second metal layer, one having a Young's modulus smaller than that of the metal materials of the first metal layer and the third metal layer is employed. According to such a configuration, it is possible to avoid that the formation of hillocks in the first metal layer and the third metal layer is suppressed by the second metal layer, for example, in the heat treatment in the sintering step or the like. Thereby, even if the thermal expansion coefficient is uneven due to the difference in the thermal expansion coefficient between the metal material forming the first metal layer and the third metal layer and the metal material forming the second metal layer, The formation of hillocks in each metal layer can suppress the stress generated in the electrode. As a result, the occurrence of excessive stress locally inside the metal layer is suppressed.

The top view of the semiconductor device 10 of an Example is shown. The internal structure of the sectional view in the II-II line in FIG. 1 is shown.

  The semiconductor device 10 of the embodiment will be described with reference to the drawings. Although the semiconductor device 10 is an example, it is a power semiconductor device which has repeatedly the unit structure of IGBT (Insulated Gate Bipolar Transistor). However, the technology disclosed in the present specification is not limited to the IGBT, and can be adopted to other semiconductor devices having electrodes of a laminated structure, such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

  As shown in FIGS. 1 and 2, the semiconductor device 10 includes a semiconductor substrate 12. The upper surface electrode 20 of the main electrode and the plurality of signal electrodes 26 are located on the upper surface 12 a of the semiconductor substrate 12, and the lower surface electrode 22 of the main electrode is located on the lower surface 12 b of the semiconductor substrate 12. The material used for the semiconductor substrate 12 is not particularly limited, and may be, for example, a nitride semiconductor such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). A protective film 28 is provided on the upper surface 12 a of the semiconductor substrate 12. The protective film 28 is provided mainly along the periphery of the semiconductor device 10 and surrounds the upper surface electrode 20 and the plurality of signal electrodes 26. The protective film 28 can be made of, for example, an insulating material such as polyimide resin.

  The semiconductor substrate 12 comprises a collector layer 34, a drift layer 36, a body layer 38 and a plurality of emitter regions 40. The collector layer 34 is a p-type semiconductor region doped with p-type (for example, aluminum) impurities. The collector layer 34 is located along the lower surface 12 b of the semiconductor substrate 12. The concentration of the p-type impurity in the collector layer 34 is sufficiently high, and the lower electrode 22 is in ohmic contact with the collector layer 34. The drift layer 36 is an n-type semiconductor region doped with n-type impurities (for example, phosphorus). The drift layer 36 is stacked on the collector layer 34 and is in direct contact with the collector layer 34.

  The body layer 38 is a p-type semiconductor region doped with p-type impurities. The body layer 38 is stacked on the drift layer 36 and is in direct contact with the drift layer 36. Furthermore, the body layer 38 has a body contact region 38a. Body contact region 38 a is in contact with upper surface electrode 20 at upper surface 12 a of semiconductor substrate 12. In the body contact region 38a, the concentration of the p-type impurity is increased, whereby the upper surface electrode 20 is in ohmic contact with the body layer 38. Emitter region 40 is an n-type semiconductor region doped with n-type impurities. Emitter region 40 is in contact with upper surface electrode 20 at upper surface 12 a of semiconductor substrate 12. Emitter region 40 is isolated from drift layer 36 via body layer 38. The concentration of the n-type impurity in the emitter region 40 is sufficiently high, and the top electrode 20 is in ohmic contact with the emitter region 40.

  As understood from FIG. 2, the semiconductor substrate 12 adopts a trench gate structure. A trench extends from the top surface 12 a of the semiconductor substrate 12 through the emitter region 40 and the body layer 38 to the drift layer 36. Emitter regions 40 are located on both sides of the trench and are adjacent to the trench. A gate electrode 24 is formed in the trench and can be made of, for example, a conductive material such as polysilicon. The gate electrode 24 is insulated from the upper surface electrode 20 by the interlayer insulating film 32, and is opposed to the emitter region 40, the body layer 38, and the drift layer 36 via the gate insulating film 30. Thereby, when a positive voltage is applied to gate electrode 24 with respect to upper surface electrode 20, the region adjacent to the trench of body layer 38 is inverted to n-type, and n extending between emitter region 40 and drift layer 36 A mold channel is formed along the trench. In this state, the semiconductor device 10 is turned on, and the upper surface electrode 20 and the lower surface electrode 22 are electrically connected.

  Furthermore, the top electrode 20 in the present embodiment is formed in a three-layer structure having the first metal layer 14, the second metal layer 16 and the third metal layer 18. The upper surface electrode 20 is not limited to the three-layer structure, and may have a four or more layer laminated structure including other metal layers. The first metal layer 14 and the third metal layer 18 are made of the same metal material, and for example, an aluminum-based or other metal material can be employed. The second metal layer 16 is interposed between the first metal layer 14 and the second metal layer 16, and is made of a metal material different from the first metal layer 14 and the second metal layer 16. In the electrode having such a configuration, the crystal grain size of the metal layer is formed relatively smaller than in the electrode in which the thickness of the metal layer in which the first metal layer 14 and the third metal layer 18 are integrated is large. . As a result, the yield strength (or yield stress) of the top electrode 20 is increased.

  However, in the configuration of the top electrode 20 described above, the first metal layer 14 and the third metal layer 18 and the second metal layer 16 are formed when heat treatment such as a sintering process is performed in the manufacturing process of the semiconductor device 10. The difference in coefficient of thermal expansion between can cause large local stresses. In particular, when a metal material such as titanium nitride is used for the second metal layer 16, for example, the difference in thermal expansion coefficient becomes large, so local excessive stress may occur. Furthermore, since titanium nitride is a high strength (for example, high Young's modulus) material, formation of hillocks (concave and convex shapes) in the adjacent first metal layer 14 and third metal layer 18 is suppressed. Therefore, the release of the stress due to the formation of hillocks is limited, and a higher stress is generated in the upper surface electrode 20, and a cavity may be formed inside the first metal layer 14 or the third metal layer 18.

  In view of the above problems, in the present embodiment, the metal material of the second metal layer 16 in the upper surface electrode 20 having the above-described laminated structure has a Young's modulus higher than that of the metal materials of the first metal layer 14 and the third metal layer 18 It is good to adopt a small one. As described above, for example, an aluminum-based or other metal material can be adopted for the first metal layer 14 and the third metal layer 18. In this case, as the second metal layer 16, one having a Young's modulus smaller than that of the first metal layer 14 and the third metal layer 18 such as, for example, a magnesium-based or other metal material can be employed. Here, the Young's modulus of aluminum is about 70 GPa, and the Young's modulus of magnesium is about 46 GPa. These aluminum and magnesium are an example of the combination which can obtain the effect of the present embodiment well in the metal material of the first metal layer 14 and the third metal layer 18 and the metal material of the second metal layer 16. . However, the combination of the metal materials in the first metal layer 14 and the third metal layer 18 and the second metal layer 16 is not particularly limited to the above combination.

  According to such a configuration, it is avoided that the formation of hillocks in the first metal layer 14 and the third metal layer 18 is suppressed by the second metal layer 16 in the heat treatment in the above-described sintering process or the like. it can. Thereby, the non-uniform thermal expansion occurred due to the difference in thermal expansion coefficient between the metal material forming the first metal layer 14 and the third metal layer 18 and the metal material forming the second metal layer 16. Even if the metal layers 14, 16 and 18 form hillocks, it is possible to suppress the stress generated in the upper surface electrode 20. As a result, the local occurrence of excessive stress in the metal layers 14, 16, 18 is suppressed.

  The problems described above can also be solved by, for example, relaxing the heating conditions of the heat treatment in the sintering step or the like. However, by relaxing the heating conditions, there is a possibility that the efficiency of hydrogen termination of the dangling bonds of atoms generated at the interface between the gate insulating film 30 inside the trench gate and the inner surface of the trench of the semiconductor substrate 12 may be reduced. If the hydrogen bonding of the unbonded hand is not sufficiently performed, it can also be a factor of increasing the on-resistance of the semiconductor device and reducing the life of the gate insulating film. Therefore, it can be said that adopting this technology is better as a solution method.

  Although some specific examples have been described above in detail, these are merely examples and do not limit the scope of the claims. The art set forth in the claims includes various variations and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness singly or in various combinations.

10: semiconductor device 12: semiconductor substrate 14: first metal layer 16: second metal layer 18: third metal layer 20: upper surface electrode 22: lower surface electrode 24: gate electrode 26: signal electrode 28: protective film 30: gate Insulating film 32: interlayer insulating film 34: collector layer 36: drift layer 38: body layer 38a: body contact region 40: emitter region

Claims (1)

A semiconductor substrate,
An electrode provided on the surface of the semiconductor substrate and having a first metal layer, a second metal layer, and a third metal layer;
Equipped with
The first metal layer and the third metal layer are made of the same metal material,
The second metal layer is a metal material located between the first metal layer and the third metal layer and having a smaller Young's modulus than the metal material of the first metal layer and the third metal layer. It is configured,
Semiconductor device.

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