JP2019036940A - Transmitter, receiver, ldpc encoder and ldpc decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmitter, a receiver, an LDPC encoder and an LDPC decoder for transmitting digital data via a nonlinear transmission line. SOLUTION: The transmission device 10 of the present invention is an error correction coding unit including an LDPC code having an overall average coding rate of 96/120 (that is, 4/5) with respect to 64 APSK based on the set division method. 12. It is provided with a mapping unit 13 having an optimized signal point arrangement of 64 APSK, and an orthogonal modulation unit 15 that orthogonally modulates a signal point sequence by the modified set division method. The receiving device 20 of the present invention demodulates the modulated wave signal transmitted by the transmitting device 10 of the present invention, performs adaptive equalization processing, and decodes it. The LDPC encoder and LDPC decoder of the present invention are 57/120, 61/120, 63/120, 64/120, 101/120, 105/120, 113/120, 115/120, 116/120, 117. It has a check matrix initial value table for one or more coding rates of / 120. [Selection diagram] Fig. 1

Description

  The present invention relates to the technical fields of satellite broadcasting, terrestrial broadcasting, fixed communication, and mobile communication, and more particularly, to a digital data transmitting device, receiving device, LDPC encoder, and LDPC decoder.

  As a technique to improve transmission performance under white noise, a coding modulation technique that can improve transmission performance by combining error correction code strength and modulation mapping bits appropriately in digital modulation has been proposed. (For example, refer nonpatent literature 1).

  The coded modulation technique described in Non-Patent Document 1 and the like is also adopted in the Japanese satellite digital broadcasting standard ISDB-S (for example, see Non-Patent Document 2), and has been proven as a technique that contributes to improving transmission performance. There is.

  The basic principle of the technique described in Non-Patent Document 1 is that among the bits constituting the symbol (hereinafter referred to as symbol constituent bits) in consideration of the Euclidean distance between signal points after the bit is mapped to the symbol. In addition, a strong error correction is applied to a bit in which 1/0 is inverted between signal points having a short Euclidean distance, and a bit is weak to a bit in which 1/0 is inverted between signal points having a long Euclidean distance. By performing error correction or not performing encoding processing, noise tolerance is improved while maintaining overall information efficiency.

  Non-Patent Document 1 proposes a method of assigning symbols to signal points called a set division method using 8PSK (phase-shift keying) as an example. The set division method uses a plurality of code sequences that can be divided for each bit as an input symbol sequence, and divides the symbol constituent bits of the input symbol sequence uniformly so that the minimum Euclidean distance between signal points is expanded, This is a transmission method for assigning symbols to signal points used for modulation. As an example, an example of a method of assigning symbols to 8PSK signal points by the set division method will be described with reference to FIG.

  In FIG. 26, symbols (000, 001,..., 111) configured by 3 bits to be assigned to each signal point of 8PSK are already described. This is performed by using the following division procedure. This is obtained as a result of assigning symbols to and has not yet been determined at the time of performing set partitioning.

  In the first division, the eight signal points are divided into two signal point groups including four signal points so that the Euclidean distance (minimum Euclidean distance) between adjacent signal points is maximized. Here, of the two signal point groups, one signal point group is assigned a1 = 0 to the first bit (most significant bit) of the symbol configuration bits, and a1 = 1 is assigned to the other.

  Next, the two signal point groups composed of the four signal points obtained in the first division are each divided into four signal point groups composed of two signal points so that the minimum Euclidean distance is maximized. . Here, when a signal point group composed of four signal points is divided into two signal point groups, one signal point group is assigned a2 = 0 to the second bit of the symbol constituent bits and the other is assigned to the other signal point group. Assigns a2 = 1.

  Furthermore, although omitted in FIG. 26, the four signal point groups composed of the two signal points obtained by the second division are each divided into eight signal point groups each consisting of one signal point. Here, when a signal point group composed of two signal points is divided into one signal point, one signal point group has a3 = 0 in the third bit (least significant bit) of the symbol constituent bits. Assign a3 = 1 to the other.

  As a result of the above three-stage set division, a unique symbol of 3 bits is assigned to each of the eight signal points.

  By assigning symbols to these signal points, in the case of 8PSK, the first bit (corresponding to a1 in FIG. 26) is the minimum Euclidean distance in 8PSK, and the second bit (corresponding to a2 in FIG. 26) is QPSK. (Quadrature Phase Shift Keying) minimum Euclidean distance, the third bit (corresponding to a3 in FIG. 26) can be decoded for each bit under the condition of BPSK (Binary Phase-Shift Keying) minimum Euclidean distance. It becomes.

  Examples of symbol allocation methods when the set division method is applied to 16QAM (Quadrature Amplitude Modulation) and 32QAM are shown in FIGS. As in the case of 8PSK, it can be confirmed that the minimum Euclidean distance increases by proceeding with the division. 27 and 28 show examples of division up to the first bit (a1: most significant bit) and the second bit (a2), the minimum Euclidean distance is similarly applied to the third bit (a3) and thereafter. Division is possible to enlarge.

  According to such a transmission method of the set division method, the symbol allocation to the signal points obtained by the set division method is shared between transmission and reception in advance, and on the transmission side, data transmitted with each bit constituting the symbol is transmitted. , Coding with an error correction code with a correction capability suitable for the minimum Euclidean distance between the corresponding signal points, and modulating on the receiving side, and performing decoding corresponding to the coding on the transmitting side after demodulation, resulting in high noise resistance A transmission system can be realized.

  On the other hand, when the set partitioning method is applied to multilevel modulation, the minimum Euclidean distance is widened for each divided bit and the error correction capability is also different for each bit, so that transmission performance is improved at a predetermined coding rate. Therefore, it is necessary to optimize the error correction code according to the error correction capability for each bit.

  By the way, the transmission system of the advanced broadband satellite digital broadcasting described in DVB-S2 (see Non-Patent Document 3), DVB-S2X (see Non-Patent Document 4) and ARIB STD-B44 which are European satellite digital broadcasting systems (hereinafter referred to as the following). In the advanced satellite broadcasting system (see Non-Patent Document 5, for example), a gray code is adopted as a technique for assigning symbols to signal points.

  Gray code has uniform correction capability for each bit in BPSK and QPSK, but error correction capability between bits included in a symbol becomes uneven in multi-level modulation of 8PSK or more. This is an obstacle to improving transmission performance in coding rate.

  For this reason, a technique for further improving the transmission method based on the set partitioning method and improving the transmission performance when the correction ability of each bit is different is disclosed (for example, patent Reference 1).

  In addition, a new signal point arrangement for 64APSK encoding modulation in a transmission method using the Gray code or the set division method is proposed, and in particular, a new bit allocation in the transmission method using the set division method is proposed, and the new signal point arrangement is also proposed. In addition, the performance improvement of error correction codes based on bit allocation is disclosed (for example, see Non-Patent Documents 6 to 9).

  More specifically, in the technique of Non-Patent Document 9 as a representative, as the new signal point arrangement of 64APSK, the arrangement number of each signal point on the four concentric circles is optimized from the viewpoint of expanding the Euclidean distance, and the four It is assumed that the amplitude value of each signal point substantially coincides with one of the concentric circles, and the phase value of each signal point is adjusted.

  In the technique of Non-Patent Document 9, as a bit allocation by the set partitioning method using the new signal point arrangement of 64APSK, a predetermined signal power to noise power ratio is changed from a bit allocation optimized based on a predetermined calculation method. It is assumed that bits have been exchanged to satisfy

  Furthermore, in the technique of Non-Patent Document 9, a slot configuration of 6 slots as a concatenated code of LDPC code and BCH code as an error correction code based on the new signal point arrangement of 64APSK and bit allocation by a new set partitioning method. The average coding rate of the entire LDPC code is 4/5, the LDPC coding rate of each slot in the 6 slots is defined, and the parity check matrix initial value table of the LDPC code in the set partitioning method is Optimized.

JP 2014-155195 A

G. Ungerboeck, “Channel coding with multilevel / phase signals”, IEEE Transaction Information Theory, Vol.IT-28, No.1, January 1982, p.55−67 “Satellite Digital Broadcasting Transmission System Standard ARIB STD-B20 Version 3.0”, revised on May 31, 2001, ARIB Digital Video Broadcasting (DVB), “Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2)”, Final draft ETSI EN 302 307 V1.2.1 (2009- 04) Digital Video Broadcasting (DVB), “Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications; Part2: DVB-S2 Extensions (DVB-S2X)”, Draft ETSI EN 302 307 -2 V1.1.1 (2014-10) "Transmission system of advanced broadband satellite digital broadcasting standard ARIB STD-B44 version 2.1", revised on March 25, 2016, ARIB Yuki Koizumi, Yoichi Suzuki, Masaaki Kojima, Junichi Saito, Shoji Tanaka, “Examination of 64APSK Coded Modulation (Part 1) -Examination of 64APSK Signal Point Arrangement-”, IEICE, 2016 Society Conference Proceedings, B-5-21, 2016, p291, announced on September 20, 2016 Yuki Koizumi, Yoichi Suzuki, Masaaki Kojima, Junichi Saito, Shoji Tanaka, “Examination of 64APSK Coded Modulation—Examination of Bit Allocation for 64APSK Coded Modulation”, Video Information Media Society, Annual Conference Proceedings, 32C- 1, 2016, announced on September 2, 2016 Yoichi Suzuki, Yuki Koizumi, Masaaki Kojima, Junichi Saito, Shoji Tanaka, “Examination of 64APSK Coded Modulation (Part 2) -Performance Improvement by Optimizing LDPC Coding Rate-”, IEICE, 2016 Society Conference Lecture Proceedings, B-5-22, 2016, p292, published on September 20, 2016 Yuki Koizumi, Yoichi Suzuki, Masaaki Kojima, Kyoichi Saito, Shoji Tanaka, “A study on 64APSK Coded Modulation”, [online], IEICE Tech. Rep., Vol. 116, no. 243, SAT2016- 55, pp. 51-56, published on October 6, 2016, [Search on August 1, 2017], Internet <URL: http://www.ieice.org/ken/paper/20161013cblh/eng/>

  As described above, in the set partitioning method, the correction capability varies from bit to bit. To improve the transmission performance at a predetermined coding rate, the error correction code is optimized according to the error correction capability for each bit. Is required.

  For this reason, Patent Document 1 discloses a technique for improving the transmission performance when the correction capability of each bit differs depending on the transmission method based on the set division method. However, a specific example is disclosed only for 8PSK. . On the other hand, what value should be adopted for the LDPC (Low Density Parity Check) coding rate and LDPC code check matrix in 64 APSK (Amplitude and Phase Shift Keying) to improve frequency utilization efficiency and improve the transmission performance? Is not disclosed. Therefore, when adopting the transmission method based on the set partitioning method, there is a possibility that the broadcaster may use an LDPC coding rate (or an LDPC code check matrix) in which transmission performance is not improved in some cases.

  Therefore, transmission by a set division method in which a plurality of code sequences that can be divided for each bit is used as an input symbol sequence, and the symbol constituent bits of the input symbol sequence are uniformly divided so that the minimum Euclidean distance between signal points is increased. In the system, a specific numerical value about a specific LDPC coding rate in 64APSK and a value related to a check matrix of the LDPC code has been desired.

Furthermore, in order to meet the need for higher image quality for ultra-high definition video such as 4K and 8K, it is necessary to improve the information bit rate. For this purpose, the modulation multi-value number is increased and the parity of the error correction code is increased. It is necessary to reduce the number of bits and increase the average coding rate, and at the same time, increase the C / N with which the error correction code satisfies pseudo error free. Usually, a bit error rate of 1.0 × 10 ⁻¹¹ is often used as a pseudo error-free evaluation point at the required C / N.

  FIG. 29 shows an example of bit allocation to symbols applied to coding rates 7/9, 4/5, and 5/6 in the DVB-S2X standard (see Non-Patent Document 4), which is a 64APSK conventional technique. The 6 bits are assigned in order from the left to the first bit (a1), the second bit (a2),..., The sixth bit (a6), and in octal notation every 3 bits from the left (example 64 = 110: 100). In DVB-S2X, a Gray code is adopted as a bit allocation technique to symbols. Gray code becomes an obstacle in improving transmission performance at a predetermined coding rate because error correction capability between bits included in a symbol becomes non-uniform in multi-level modulation of 8PSK or more.

  In particular, digital data is transmitted using 64APSK while satisfying 34.5 MHz, which is a bandwidth that can be used for one satellite repeater in 12 GHz band satellite broadcasting, for example, in accordance with higher resolution of video to be transmitted in the future. Therefore, a transmission system having a transmission bit rate of 150 Mbps or higher is required, and a technique for improving the performance over DVAP-S2X 64APSK is desired. More preferably, a technique for improving the problems of the Gray code described above is desired. desired.

  On the other hand, Non-Patent Documents 6 to 9 disclose a technique for improving the problem of the Gray code as a technique for improving the performance of an error correction code based on a new signal point arrangement and bit allocation. There is room for further performance improvement in the non-linear transmission line via the repeater. Non-Patent Documents 6 to 9 are techniques for improving the required C / N of 64APSK coded modulation under white noise. On the other hand, in satellite transmission, non-linear distortion generated in the satellite repeater becomes a factor that degrades required C / N. In addition, it is effective to perform an adaptive equalization process based on the least square error criterion on the signal subjected to the nonlinear distortion.

  For example, as a target device of a nonlinear transmission path in satellite broadcasting of 12 GHz band, for example, an input filter (IMUX filter), a power amplifier (TWTA), and an output filter (provided in a satellite repeater mounted on a broadcasting satellite) OMUX filter).

  The IMUX filter is a band-pass filter corresponding to each channel frequency, and extracts only one channel band component from a plurality of channels of modulated wave signals received from the terrestrial broadcasting station, and outputs the extracted band component to each TWTA. In the terrestrial broadcasting station, the modulated wave signal from the transmitter is amplified by a high power amplifier (HPA) and is uplinked to the satellite repeater.

  The TWTA performs power amplification on the extracted modulated wave signal for one channel and outputs it to the OMUX filter.

  The OMUX filter is a band pass filter corresponding to each channel frequency, and extracts a band component for one channel from a modulated wave signal amplified by TWTA and broadcasts a modulated wave signal in which an unnecessary frequency component is suppressed. It generates as a signal and outputs it to the receiving device on the ground.

  Originally, TWTA desirably performs power amplification processing with input / output characteristics in which the relationship between the amplitude and phase between the input signal and the output signal is proportional. However, this input / output characteristic actually has non-linearity (AM-AM characteristic) in which the gain of the output signal decreases as the gain of the input signal increases. At the same time, the phase of the output signal with respect to the input signal also rotates, resulting in non-linearity. (AM-PM characteristics). Therefore, if the gain of the input signal is within a certain level, the gain of the output signal also becomes a substantially linear output level. However, if the gain of the input signal exceeds a certain level, a phenomenon occurs in which the output level decreases conversely. . The operating point immediately before such a decrease in the output level is generally called an output saturation point. The case where the operation is performed with the input level lowered from the output saturation point is called input back-off (IBO). Similarly, the case where the operation is performed with the input level reduced and the output level lowered is output back-off (OBO). ). In particular, in the case of APSK, since there are signal points having a plurality of amplitudes in the signal point arrangement of amplitude and phase, the required C / N is likely to be deteriorated due to the nonlinearity of TWTA as compared with PSK modulation.

  Further, the IMUX filter and the OMUX filter have an amplitude difference (frequency-amplitude characteristic) and a group delay difference (frequency-group delay characteristic) in the frequency within the modulation wave band from the viewpoint of extracting band components and generating waveforms. . Since these differences are uneven in the in-band frequency, when viewed on the time axis, the delays differ depending on the symbol transition. For this reason, interference (ISI) between symbols is caused and spread as signal points, so that the required C / N is deteriorated.

  An adaptive equalization process is performed on the received signal in order to compensate for the non-linear distortion generated in the non-linear transmission path. In adaptive equalization, an ideal signal point arrangement determined by a known modulation method and an error vector of a received signal subjected to nonlinear distortion are calculated, and a filter coefficient of the adaptive equalizer is updated by an LMS (Least Mean Square) method. Perform nonlinear distortion compensation.

  However, when adaptive equalization processing is performed on 64APSK encoded modulation subjected to nonlinear distortion, the equalization performance varies depending on the amplitude of the signal point. Therefore, in a satellite transmission system that adaptively equalizes a received signal affected by nonlinear distortion, the 64APSK coded modulation of Non-Patent Documents 6 to 9 designed under white noise is an optimal transmission method for a satellite transmission system. is not.

  Therefore, in a transmission apparatus that transmits digital data via a nonlinear transmission path, optimization of signal point arrangement and bit allocation related to mapping at the time of modulation, and a coding rate for each bit constituting a symbol according to this (particularly, It is also necessary to optimize the parity check matrix related to the error correction by the LDPC code and the optimization of the coding rate of the LDPC code. Similarly, a receiving apparatus that receives digital data via a nonlinear transmission path demodulates according to the signal point arrangement and bit allocation related to the optimized mapping, performs an adaptive equalization process, and performs the optimization of the optimized symbol. It is necessary to determine the likelihood using the optimized parity check matrix and decode it according to the coding rate of each bit constituting the coding rate (particularly, the coding rate of the LDPC code).

  In view of the above problems, an object of the present invention is to provide a transmission apparatus, a reception apparatus, and an LDPC code that enable a transmission bit rate of 150 Mbps or higher when transmitting digital data using 64APSK through a nonlinear transmission path. And providing an LDPC decoder.

  In the transmitting apparatus and the receiving apparatus according to the present invention, when digital data is transmitted using 64APSK, the overall coding rate of the LDPC code is set to 4/5 (= 96/120) in order to set the transmission bit rate to 150 Mbps or more. For the symbols encoded by the LDPC code, an IQ signal with 64 APSK signal point arrangement taking into account nonlinear distortion in the nonlinear transmission path and adaptive equalization performance on the receiving side, and further, bit allocation to each signal point ( It is configured to include mapping means for performing mapping of a complex signal including in-phase component I and quadrature component Q. In the transmission apparatus and the reception apparatus according to the present invention, the LDPC code parameters related to the parity check matrix of the LDPC coding rate for each bit are also optimized. In the present invention, the LDPC code parameter for each bit having a steep error correction capability is optimized at C / N = 16 dB.

  In particular, in the transmission apparatus and the reception apparatus according to the present invention, the multi-value modulation is applied to the mapping scheme based on the set partitioning method that can improve the above-described problem of the mapping scheme of the Gray code (also referred to as “Gray coding” in the specification) As the signal point division proceeds, the minimum Euclidean distance increases, and error correction can be performed with less parity. In the case of 64APSK, error correction of the first bit (a1) is performed by LDPC decoding using an a1 LDPC code using 64 signal points. The error correction of the second bit (a2) is performed in the same way using the 32 signal points divided by the decoding result of a1 and the LDPC code for a2. Thereafter, signal point division and LDPC decoding based on the previous decoding result are repeated for the third bit (a3) to the sixth bit (a6) (multistage decoding). Further, in order to correct residual bit errors after LDPC decoding, a BCH outer code is connected to all bits.

  Hereinafter, features of the transmission device and the reception device according to the present invention will be listed.

The first feature is
In a transmission apparatus that transmits digital data, symbols after encoding by an LDPC code with an overall average encoding rate of 4/5 are arranged as signal points in the 64APSK modulation scheme, as will be described later in Tables 11 and 12, Alternatively, a mapping unit that performs IQ signal mapping shown in Table 15 and Table 16 is provided. This signal point arrangement takes into account nonlinear distortion in the nonlinear transmission path and adaptive equalization performance on the receiving side. Thereby, compared with 64APSK of nonpatent literature 9, the tolerance with respect to the nonlinear distortion by a nonlinear transmission line can be improved.

The second feature is
The bit allocation of each bit constituting the symbol with respect to the signal point arrangement is configured as shown in Table 13 based on Table 11 and Table 12 described later, or Table 17 based on Table 15 and Table 16.

The third feature is
In a transmission apparatus that transmits digital data that constitutes the bit allocation of each bit that constitutes the signal point arrangement and the symbol, the modulation scheme is 96/120 (ie, the average coding rate of the entire LDPC code with respect to 64 APSK) 4/5) is applied, and a concatenated code that includes an LDPC code and includes a BCH code, and assigns a symbol to a signal point used for modulation, and the concatenated code is a bit constituting each symbol. The first bit (the most significant bit) is used to encode the LDPC code for each bit of the symbol component bits in the set partitioning method. ) To 6th bit (least significant bit), the first bit, the second bit, the third bit, the fourth bit, and the sixth bit. Is encoded with an LDPC code having a coding rate corresponding to the BER characteristic of each bit, and the fifth bit is encoded with a predetermined BCH code without applying the LDPC code, or the first bit ( For the first bit, the second bit, the third bit, the fourth bit, and the fifth bit in order from the most significant bit) to the sixth bit (least significant bit), the coding rate according to the BER characteristic of each bit The sixth bit is configured to be encoded with a predetermined BCH code without applying the LDPC code. Thereby, it is possible to increase the frequency use efficiency in the set division method.

The fourth feature is
In the LDPC code, the code length of the LDPC code is 44880 bits. Thereby, transmission with high consistency with MPEG-2 TS (Motion Pictures Expert Group 2 Transport Stream) becomes possible.

The fifth feature is
In the concatenated code, the BCH code is a BCH (65535, 65343) shortened code or a BCH (65535, 65167) shortened code. As a result, sufficient error tolerance can be obtained even when the inner code parity is not added to improve the frequency utilization efficiency.

The sixth feature is
When the BCH code is a BCH (65535, 65343) shortened code, all the information bits constituting the code sequence are configured in units of bytes. As a result, even in the information bit area of the code sequence, it is possible to divide the breaks of variable-length packets configured in byte units such as TLV in byte units.

The seventh feature is
The LDPC code has 57/120 for the first bit, 64/120 for the second bit, and 3rd bit for 6 bits constituting a 64APSK modulation symbol with an average coding rate of 96/120 (ie, 4/5). 105/120, fourth bit 117/120, fifth bit 120/120 (no LDPC parity), sixth bit 113/120 coding rate, or first bit 61/120, The coding rate is 63/120 for the second bit, 101/120 for the third bit, 115/120 for the fourth bit, 116/120 for the fifth bit, and 120/120 for the sixth bit (no LDPC parity). There is. Thus, by having a coding rate determined according to the required correction capability for each bit, it becomes possible to improve the frequency utilization efficiency in the set partitioning method.

The eighth feature is
In the transmission apparatus configured by the third to seventh characteristics, information on one or more coding rates of the LDPC code and the BCH code used on the transmission apparatus side is transmitted by a transmission multiplex control signal. Accordingly, it is possible to provide a transmission device and a reception device in which matching between encoding and decoding is achieved according to the encoding rate to be used.

The ninth feature is
In a receiver that receives a signal transmitted by a transmitter configured by the third to seventh features, when each bit constituting the symbol is subjected to LDPC decoding, the first bit, the second bit, The LDPC decoding process is performed in the order of 3 bits, 4th bit, 5th bit, and 6th bit by using a check matrix used for the LDPC code corresponding to the correction capability for each bit.

The tenth feature is
In the receiving device that receives the signal transmitted by the transmitting device configured by the third to seventh features, the transmitting side performs decoding corresponding to the LDPC code and BCH code of the coding rate used for encoding. There is. This enables efficient error correction decoding.

The eleventh feature is
In a receiving apparatus that receives a signal transmitted by a transmitting apparatus configured according to the eighth feature, one or more coding rate information of an LDPC code and a BCH code is determined based on a transmission multiplexing control signal. is there. Accordingly, it is possible to provide a transmission device and a reception device in which matching between encoding and decoding is achieved according to the encoding rate to be used.

  The transmission performance in 64 APSK can be improved by adopting the above technique to configure the transmission device and the reception device.

That is, the transmission device according to the first aspect of the present invention is a transmission device that transmits digital data,
Error correction coding means for generating a symbol with an overall average coding rate of 4/5 by applying a concatenated code comprising an LDPC code in part to the digital data and comprising a BCH code;
As a signal point arrangement in the 64APSK modulation system for symbols encoded by the error correction encoding means, four concentric circles are defined as a first circle, a second circle, a third circle, and a fourth circle in order from the smallest radius. And set division with 12 signal points on the first circle, 16 signal points on the second circle, 16 signal points on the third circle, and 20 signal points on the fourth circle. A mapping means for mapping a legal IQ signal;
A quadrature modulation unit that modulates the symbol mapped by the mapping unit by a 64APSK modulation method and transmits a modulated wave signal to a receiving device that performs adaptive equalization processing through a nonlinear transmission path;
The mapping means sets the phase angle in the signal point arrangement as the phase angle for the first circle, 30 degrees from the position of 22 degrees counterclockwise from the reference phase of 0 degrees for the I axis, and the I axis for the second circle. 22.5 degrees from the position of 22.55 degrees counterclockwise with respect to the reference phase of 0 degrees, and the third circle is 22 from the position of 11.45 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis. .5 degree intervals, and the fourth circle is 18 degrees apart from a position of 11.3 degrees counterclockwise with respect to the reference phase of the I axis, and the first circle, as the radius ratio in the signal point arrangement, The radii of the second circle, the third circle, and the fourth circle are defined as r1, r2, r3, and r4, respectively, and the radius ratio with respect to r1 is γ1 = r2 / r1, γ2 = r3 / r1, and γ3 = r4. When defined as / r1, γ1 = 2.02, γ2 = 2.98, γ3 = 4. Mapping of the IQ signal configured to be 14,
The error correction coding means performs LDPC code encoding for each bit of the symbol constituting bits in the set division method at a predetermined number of coding rates determined according to the required correction capability of each bit constituting the symbol. For encoding, the 6 bits of the 64APSK symbol configuration bits having an average coding rate of 4/5, the most significant bit is 57/120 in the first bit, the second bit is 64/120, the third bit 105/120, the fourth bit is 117/120, the fifth bit is 120/120 (no LDPC parity), and the fifth bit, which is the least significant bit, has a coding rate of 113/120.

Further, in the transmission apparatus according to the first aspect of the present invention, bit allocation of each bit constituting the symbol with respect to the signal point arrangement is
About the first circle, “001100 (14 in octal notation)” is located at a position of 22 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis.
“011100 (34 in octal notation)” at the 52 ° position,
"101100 (54 in octal notation)" at a position of 82 degrees,
“111100 (74 in octal notation)” at a position of 112 degrees,
“000101 (05 in octal notation)” at a position of 142 degrees,
"010100 (24 in octal notation)" at 172 degrees,
“100101 (45 in octal notation)” at the position of 202 degrees,
“110101 (65 in octal notation)” at the position of 232 degrees,
"001101 (15 in octal notation)" at 262 degrees,
"011001 (31 in octal notation)" at a position of 292 degrees,
“101001 (51 in octal notation)” at the position of 322 degrees,
“111001 (71 in octal notation)” at the position of 352 degrees,
For the second circle, “111000 (70 in octal notation)” at a position of 22.55 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"000001 (01 in octal notation)" at the 45.05 degree position,
"010000 (20 in octal notation)" at a position of 67.55 degrees,
"100001 (41 in octal notation)" at the 90.05 degree position,
“110001 (61 in octal)” at the position of 112.55 degrees,
“001001 (11 in octal notation)” at a position of 135.05 degrees,
"011101 (35 in octal notation)" at a position of 157.55 degrees,
“101101 (55 in octal notation)” at 180.05 degrees,
“111101 (75 in octal notation)” at the position of 202.55 degrees,
"000000 (00 in octal notation)" at a position of 222.05 degrees,
"010001 (21 in octal notation)" at a position of 247.55 degrees,
"100,000 (40 in octal notation)" at 270.05 degrees,
"110000 (60 octal notation)" at 292.55 degrees,
“001000 (10 in octal notation)” at a position of 315.05 degrees,
"011000 (30 in octal notation)" at a position of 337.55 degrees,
"101000 (50 in octal notation)" at a position of 360.05 degrees,
Regarding the third circle, “001111 (17 in octal notation)” at the position of 11.45 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
“011111 (37 in octal notation)” at the position of 33.95 degrees,
“101111 (57 in octal notation)” at the position of 56.45 degrees,
"111111 (77 in octal notation)" at the 78.95 degree position,
"000100 (04 in octal notation)" at the 101.45 degree position,
“010101 (25 in octal notation)” at the position of 123.95 degrees,
“100100 (44 in octal notation)” at the position of 146.45 degrees,
“110100 (64 in octal notation)” at the position of 168.95 degrees,
"001110 (16 in octal notation)" at the position of 191.45 degrees,
“011110 (36 in octal notation)” at the position of 213.95 degrees,
"101110 (56 in octal notation)" at a position of 236.45 degrees,
“111110 (76 in octal notation)” at the position of 258.95 degrees,
"000111 (07 in octal notation)" at the position of 281.45 degrees,
“010110 (26 in octal notation)” at a position of 303.95 degrees,
“100111 (47 in octal notation)” at the position of 326.45 degrees,
"110111 (67 in octal notation)" at a position of 348.95 degrees,
For the fourth circle, “000010 (02 in octal notation)” at a position of 11.3 degrees counterclockwise with respect to the reference phase of the I axis is 0 degrees.
"010011 (23 in octal notation)" at the position of 29.3 degrees,
"100010 (42 in octal notation)" at a position of 47.3 degrees,
"110010 (62 in octal notation)" at a position of 65.3 degrees,
“001010 (12 in octal notation)” at the position of 83.3 degrees,
"011010 (32 in octal notation)" at a position of 101.3 degrees,
"101010 (52 in octal notation)" at the 119.3 degree position,
"1111010 (72 in octal notation)" at the position of 137.3 degrees,
“000011 (03 in octal notation)” at 155.3 degrees,
"010010 (22 in octal notation)" at 173.3 degrees,
"100011 (43 in octal notation)" at 191.3 degrees,
"110011 (63 in octal notation)" at the position of 209.3 degrees,
"001011 (13 in octal notation)" at 227.3 degrees,
“011011 (33 in octal notation)” at the position of 245.3 degrees,
“101011 (53 in octal notation)” at the position of 263.3 degrees,
“111011 (73 in octal notation)” at a position of 281.3 degrees,
“000110 (06 in octal notation)” at the position of 299.3 degrees,
“010111 (27 in octal notation)” at the position of 317.3 degrees,
"100110 (46 in octal notation)" at 335.3 degrees,
“110110 (66 in octal notation)” at the position of 353.3 degrees,
It is comprised so that it may become.

  In the transmission apparatus according to the first aspect of the present invention, the error correction coding means includes an encoder that performs LDPC coding of the digital data using a check matrix unique to each coding rate, and The initial value is a parity check matrix initial value table predetermined for each coding rate with a code length of 48880 bits, and 1 element of a submatrix corresponding to the information length according to the coding rate 57/120 is The parity check matrix initial value table (Table 1) having the coding rate 57/120 has a means for performing LDPC encoding using a parity check matrix arranged and arranged in a column direction with a period of every 374 columns. It consists of a table.

  In the transmission apparatus according to the first aspect of the present invention, the error correction coding means includes an encoder that performs LDPC coding of the digital data using a check matrix unique to each coding rate, and The initial value is a parity check matrix initial value table predetermined for each coding rate with a code length of 48880 bits, and 1 element of a submatrix corresponding to the information length according to the coding rate 64/120 is The parity check matrix initial value table (Table 2) having the coding rate of 64/120 has a means for performing LDPC encoding using a parity check matrix arranged and arranged at a period of 374 columns in the column direction. It consists of a table.

  In the transmission apparatus according to the first aspect of the present invention, the error correction coding means includes an encoder that performs LDPC coding of the digital data using a check matrix unique to each coding rate, and The initial value is a parity check matrix initial value table predetermined for each coding rate with a code length of 48880 bits, and 1 element of a submatrix corresponding to the information length corresponding to the coding rate 105/120 is The parity check matrix initial value table (Table 3) having the coding rate of 105/120 has a means for performing LDPC encoding using a parity check matrix arranged and arranged at a period of 374 columns in the column direction. It consists of a table.

  In the transmission apparatus according to the first aspect of the present invention, the error correction coding means includes an encoder that performs LDPC coding of the digital data using a check matrix unique to each coding rate, and The initial value is a parity check matrix initial value table predetermined for each coding rate with a code length of 48880 bits, and one element of a submatrix corresponding to the information length according to the coding rate 113/120 is The parity check matrix initial value table (Table 9) having the coding rate 113/120 has a means for performing LDPC encoding using a parity check matrix arranged and arranged with a period of every 374 columns in the column direction. It consists of a table.

  In the transmission apparatus according to the first aspect of the present invention, the error correction coding means includes an encoder that performs LDPC coding of the digital data using a check matrix unique to each coding rate, and The initial value is a parity check matrix initial value table predetermined for each coding rate with a code length of 48880 bits, and 1 element of the submatrix corresponding to the information length according to the coding rate 117/120 The parity check matrix initial value table (Table 5) having the coding rate 117/120 has a means for performing LDPC coding using a parity check matrix arranged and arranged at a period of 374 columns in the column direction. It consists of a table.

On the other hand, the transmission device according to the second aspect of the present invention is a transmission device for transmitting digital data,
Error correction coding means for generating a symbol with an overall average coding rate of 4/5 by applying a concatenated code comprising an LDPC code in part to the digital data and comprising a BCH code;
As a signal point arrangement in the 64APSK modulation system for symbols encoded by the error correction encoding means, four concentric circles are defined as a first circle, a second circle, a third circle, and a fourth circle in order from the smallest radius. And set division with 8 signal points on the first circle, 16 signal points on the second circle, 20 signal points on the third circle, and 20 signal points on the fourth circle. A mapping means for mapping a legal IQ signal;
A quadrature modulation unit that modulates the symbol mapped by the mapping unit by a 64APSK modulation method and transmits a modulated wave signal to a receiving device that performs adaptive equalization processing through a nonlinear transmission path;
The mapping means sets the phase angle in the signal point arrangement as 45 degrees from the position of 58.4 degrees counterclockwise to the reference phase of the I axis for the first circle, and 45 degrees from the left. An interval of 22.5 degrees from a position of 14.55 degrees counterclockwise with respect to the reference phase of 0 degrees on the I-axis, and the third circle is 18 degrees from a position of 18 degrees counterclockwise with respect to the reference phase of 0 degrees on the I-axis. The fourth circle has an interval of 18 degrees from the position of 9 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis, and the radius ratio in the signal point arrangement is the first circle, the second circle, The radii of the third circle and the fourth circle are defined as r1, r2, r3, r4, respectively, and the radius ratio is defined as γ1 = r2 / r1, γ2 = r3 / r1, and γ3 = r4 / r1 with respect to r1. Γ1 = 2.10, γ2 = 3.16, γ3 = 4.49 Mapping of configured IQ signals,
In the LDPC code, the 6 bits of the 64APSK symbol configuration bits having an average coding rate of 4/5 are 61/120 in the first bit, 63/120 in the second bit, and 63/120 in the second bit. The coding rate is 101/120, 115/120 in the fourth bit, 116/120 in the fifth bit, and 120/120 (no LDPC parity) in the sixth bit which is the least significant bit.

Further, in the transmission apparatus according to the second aspect of the present invention, the bit allocation of each bit constituting the symbol with respect to the signal point arrangement is:
Regarding the first circle, “101000 (50 in octal notation)” at a position of 58.4 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"1111010 (72 in octal notation)" at the position of 103.4 degrees,
“000010 (02 in octal notation)” at the position of 148.4 degrees,
“010010 (22 in octal notation)” at a position of 193.4 degrees,
“100010 (42 in octal notation)” at 238.4 degrees,
"111100 (74 in octal notation)" at a position of 283.4 degrees,
“001000 (10 octal notation)” at 328.4 degrees,
"011100 (34 in octal notation)" at a position of 373.4 degrees,
For the second circle, “100100 (44 in octal notation)” at a position of 14.55 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
“010100 (24 in octal notation)” at the position of 37.05 degrees,
“000110 (06 in octal notation)” at the position of 59.55 degrees,
"110110 (66 in octal notation)" at the 82.05 degree position,
"101110 (56 in octal notation)" at a position of 104.55 degrees,
“011110 (36 in octal notation)” at the position of 127.05 degrees,
“001100 (14 in octal notation)” at the position of 149.55 degrees,
“111000 (70 in octal notation)” at a position of 172.05 degrees,
"101100 (54 in octal notation)" at a position of 194.55 degrees,
"011000 (30 in octal notation)" at a position of 217.05 degrees,
“001110 (16 in octal)” at a position of 239.55 degrees,
“111110 (76 in octal notation)” at the position of 262.05 degrees,
"100110 (46 in octal notation)" at a position of 284.55 degrees,
“010110 (26 in octal notation)” at the position of 307.05 degrees,
“000000 (00 in octal notation)” at the position of 329.55 degrees,
“110000 (60 in octal notation)” at the position of 352.05 degrees,
For the third circle, “101010 (52 in octal notation)” at a position of 18 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"110010 (62 in octal notation)" at 36 degrees,
“001111 (17 in octal notation)” at 54 °,
“011010 (32 in octal notation)” at the position of 72 degrees,
"101101 (55 in octal notation)" at the 90 degree position,
“111101 (75 in octal notation)” at the position of 108 degrees,
"000100 (04 in octal notation)" at 126 degrees,
“010000 (20 in octal notation)” at the position of 144 degrees,
"100111 (47 in octal notation)" at a position of 162 degrees,
“111111 (77 in octal notation)” at a position of 180 degrees,
“000111 (07 in octal notation)” at 198 degrees,
"010111 (27 in octal notation)" at the position of 216 degrees,
“100,000 (40 in octal)” at 234 degrees,
“110100 (64 in octal notation)” at the position of 252 degrees,
“001101 (15 in octal notation)” at a position of 270 degrees,
“011101 (35 in octal notation)” at the position of 288 degrees,
“101111 (57 in octal notation)” at a position of 306 degrees,
"110111 (67 in octal notation)" at a position of 324 degrees,
“001010 (12 in octal notation)” at 342 degrees,
“011111 (37 in octal notation)” at a position of 360 degrees,
Regarding the fourth circle, “000001 (01 in octal notation)” at a position of 9 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
“010001 (21 in octal notation)” at a position of 27 degrees,
"100001 (41 in octal notation)" at 45 degrees,
"110001 (61 in octal notation)" at a position of 63 degrees,
"0000011" (03 in octal notation)
"010011 (23 in octal notation)" at the 99-degree position,
"1000011 (43 in octal notation)" at a position of 117 degrees,
“110011 (63 in octal notation)” at a position of 135 degrees,
“001001 (11 in octal notation)” at the position of 153 degrees,
“011001 (31 in octal notation)” at a position of 171 degrees,
“101001 (51 in octal notation)” at the position of 189 degrees,
“111001 (71 in octal notation)” at a position of 207 degrees,
"001011 (13 in octal notation)" at a position of 225 degrees,
“011011 (33 in octal notation)” at the position of 243 degrees,
“101101 (53 in octal notation)” at the position of 261 degrees,
"1111011 (73 in octal notation)" at a position of 279 degrees,
“000101 (05 in octal notation)” at a position of 297 degrees,
“010101 (25 in octal notation)” at the position of 315 degrees,
"100101 (45 in octal notation)" at the position of 333 degrees,
"110101 (65 in octal notation)" at the position of 351 degrees,
It is comprised so that it may become.

  In the transmission apparatus according to the second aspect of the present invention, the error correction coding means includes an encoder that performs LDPC coding of the digital data using a check matrix unique to each coding rate, and The initial value is a parity check matrix initial value table predetermined for each coding rate with a code length of 48880 bits, and 1 element of a submatrix corresponding to the information length according to the coding rate 61/120 is The parity check matrix initial value table (Table 6) having the coding rate 61/120 has a means for performing LDPC encoding using a parity check matrix arranged and arranged at a period of 374 columns in the column direction. It consists of a table.

  In the transmission apparatus according to the second aspect of the present invention, the error correction coding means includes an encoder that performs LDPC coding of the digital data using a check matrix unique to each coding rate, and The initial value is a parity check matrix initial value table predetermined for each coding rate with a code length of 48880 bits, and one element of a submatrix corresponding to the information length according to the coding rate 63/120 is The parity check matrix initial value table (Table 7) having the coding rate 63/120 has a means for performing LDPC encoding using a parity check matrix arranged and arranged at a period of 374 columns in the column direction. It consists of a table.

  In the transmission apparatus according to the second aspect of the present invention, the error correction coding means includes an encoder that performs LDPC coding of the digital data using a check matrix unique to each coding rate, and The initial value is a parity check matrix initial value table predetermined for each coding rate with a code length of 48880 bits, and 1 element of a sub-matrix corresponding to the information length according to the coding rate 101/120 is The parity check matrix initial value table (Table 8) having the coding rate 101/120 has a means for performing LDPC encoding using a parity check matrix arranged and arranged with a period of 374 columns in the column direction. It consists of a table.

  In the transmission apparatus according to the second aspect of the present invention, the error correction coding means includes an encoder that performs LDPC coding of the digital data using a check matrix unique to each coding rate, and The initial value is a parity check matrix initial value table predetermined for each coding rate with a code length of 48880 bits, and 1 element of a submatrix corresponding to the information length according to the coding rate 115/120 The parity check matrix initial value table (Table 9) having the coding rate of 115/120 has a means for performing LDPC coding using a parity check matrix arranged and arranged at a period of 374 columns in the column direction. It consists of a table.

  In the transmission apparatus according to the second aspect of the present invention, the error correction coding means includes an encoder that performs LDPC coding of the digital data using a check matrix unique to each coding rate, and The initial value is a parity check matrix initial value table predetermined for each coding rate with a code length of 48880 bits, and 1 element of a submatrix corresponding to the information length corresponding to the coding rate 116/120 The parity check matrix initial value table (Table 10) having the coding rate 116/120 has a means for performing LDPC encoding using a parity check matrix arranged and arranged at a period of 374 columns in the column direction. It consists of a table.

  In the transmission apparatus according to the first or second aspect of the present invention, the BCH code is a BCH (65535, 65167) shortened code or a BCH (65535, 65167) shortened code.

  In the transmission apparatus according to the first or second aspect of the present invention, when the BCH code is a BCH (65535, 65343) shortened code, all the information bits constituting the code sequence are configured in units of bytes. Features.

  Furthermore, the receiving apparatus of the present invention receives a modulated wave signal based on the 64APSK IQ signal transmitted from the transmitting apparatus of the first or second aspect according to the present invention via a nonlinear transmission path, and receives the modulated wave signal from the modulated wave signal. Orthogonal demodulation means for generating a demodulated signal by performing orthogonal demodulation processing corresponding to the 64APSK signal point arrangement and adaptive equalization processing for the demodulated signal compensated for distortion caused by the nonlinear transmission path An adaptive equalization means for outputting a received signal point sequence; and a symbol component bit comprising a plurality of code sequences that can be divided by 6 bits constituting the 64APSK is obtained from the received signal point sequence, and an LDPC defined for each bit An LDPC decoding process using an encoding rate of the code, and a decoding unit for performing a BCH decoding process, and the code of the LDPC code defined for each bit The rate is determined for each bit according to the required correction capability of the symbol divided by the set division method in the bit order from the most significant bit to the least significant bit of the symbol constituent bits, and is determined for each bit. The entire average coding rate of the LDPC code is configured to be 4/5, and the decoding unit performs the first bit, the second bit, the third bit, when performing LDPC decoding on each bit constituting the symbol, The LDPC decoding process is performed using the parity check matrix used for the LDPC code corresponding to the correction capability for each bit in the order of the fourth bit, the fifth bit, and the sixth bit, and one or more coding rates of the LDPC code and the BCH code are used. It is characterized by comprising coding rate discrimination means for discriminating information based on a transmission multiplex control signal.

  Further, in the receiving apparatus of the present invention, the decoding means performs decoding based on the coding rate of the LDPC code and the parity check matrix individually set for each bit of the symbol constituent bits in the set partitioning method. It is characterized by.

  An LDPC encoder according to an aspect of the present invention is an LDPC encoder that performs LDPC encoding of digital data using a check matrix unique to each encoding rate, and encodes with a code length of 44880 bits. Coding rates 57/120, 61/120, 63 / of LDPC codes individually set for each bit of the symbol constituent bits in the set partitioning method using a parity check matrix initial value table predetermined for each rate as an initial value One element of the submatrix corresponding to the information length for one or more coding rates of 120, 64/120, 101/120, 105/120, 113/120, 115/120, 116/120, 117/120 Is provided with means for performing LDPC encoding using a parity check matrix that is arranged in a column direction at intervals of 374 columns.

  In the LDPC encoder according to one aspect of the present invention, the encoding rate 57/120, 61/120, 63/120, 64/120, 101/120, 105/120, 113/120, 115/120, 116/120, 117/120, the parity check matrix initial value table includes Table 1, Table 6, Table 7, Table 2, Table 8, Table 3, Table 4, Table 9, Table 10, and Table 5, respectively. It is characterized by.

  In addition, an LDPC decoder according to an aspect of the present invention is configured to perform, with respect to each bit of symbol configuration bits in the set division method, digital data to which an LDPC code parity is added by the LDPC encoder according to an aspect of the present invention. And decoding based on the coding rate of the LDPC code set individually and the parity check matrix.

  According to the present invention, for example, when transmitting digital data using 64 APSK while satisfying 34.5 MHz which is a bandwidth available for one satellite repeater in 12 GHz band satellite broadcasting, the transmission bit rate is 150 Mbps or more. A transmission system can be realized. Furthermore, according to the present invention, it is possible to improve the performance of coded modulation in a combination of an error correction code and multilevel modulation (64APSK), and improve the transmission performance in a nonlinear transmission path.

It is a figure which shows the structural example of the transmitter of 1st Embodiment by this invention, and a receiver. (A) is a figure which shows the constellation of the transmission signal point which concerns on the technique of a nonpatent literature 9, and the reception signal point via a nonlinear transmission path, (b) is a transmission signal point which concerns on 1st Embodiment by this invention, and It is a figure which shows the constellation of the received signal point through a nonlinear transmission path. It is a figure which shows the outline | summary of the signal point arrangement | positioning design of 64APSK which concerns on 1st Embodiment by this invention. It is a figure which shows the bit allocation result from the 1st bit-the 6th bit on the basis of the transmission line capacity of 64APSK which concerns on 1st Embodiment by this invention. It is a figure which shows the C / N versus bit error rate characteristic before the error correction for every 64 APSK bit which concerns on 1st Embodiment by this invention. It is a figure which shows the bit allocation result from the 1st bit-the 6th bit after the bit replacement of 64APSK which concerns on 1st Embodiment by this invention. It is a figure which shows the C / N versus bit error rate characteristic before the error correction for every bit after the bit replacement of 64APSK which concerns on 1st Embodiment by this invention. It is a figure which shows the division | segmentation process from the 1st bit to the 6th bit after the 64 APSK bit replacement according to the first embodiment of the present invention. As Example 1 according to the first embodiment of the present invention, the first bit LDPC coding rate 57/120, the second bit LDPC coding rate 64/120, the third bit LDPC coding rate 105/120, the fourth bit Slot configuration example for LDPC coding rate 117/120, 5th bit LDPC coding rate 120/120 (no LDPC parity), 6th bit LDPC coding rate 113/120, and BCH (65535, 65343) shortened code FIG. As Example 2 according to the first embodiment of the present invention, information bits are configured in byte units in all code sequences, and the first bit LDPC coding rate 57/120, the second bit LDPC coding rate 64/120, 3rd bit LDPC coding rate 105/120, 4th bit LDPC coding rate 117/120, 5th bit LDPC coding rate 120/120 (no LDPC parity), 6th bit LDPC coding rate 113/120, and It is a figure which shows the example of a slot structure in the case of BCH (65535, 65343) shortened code. As Example 3 according to the first embodiment of the present invention, first bit LDPC coding rate 57/120, second bit LDPC coding rate 64/120, third bit LDPC coding rate 105/120, fourth bit Slot configuration example for LDPC coding rate 117/120, 5th bit LDPC coding rate 120/120 (no LDPC parity), 6th bit LDPC coding rate 113/120, and BCH (65535, 65167) shortened code FIG. It is a figure which shows the C / N vs. bit error rate characteristic which compares Example 3 which concerns on 1st Embodiment by this invention, and the technique of a nonpatent literature 9. FIG. It is a figure which shows the required C / N comparison result which compares Example 3 which concerns on 1st Embodiment by this invention, and the technique of a nonpatent literature 9. FIG. It is a figure which shows the structural example of the transmitter of 2nd Embodiment by this invention, and a receiver. (A) is a figure which shows the constellation of the transmission signal point which concerns on the technique of a nonpatent literature 9, and the reception signal point via a nonlinear transmission path, (b) is the transmission signal point which concerns on 2nd Embodiment by this invention, and It is a figure which shows the constellation of the received signal point through a nonlinear transmission path. It is a figure which shows the bit allocation result from the 1st bit-the 6th bit on the basis of the transmission line capacity of 64APSK which concerns on 2nd Embodiment by this invention. It is a figure which shows the C / N versus bit error rate characteristic before the error correction for every 64 APSK bit which concerns on 2nd Embodiment by this invention. It is a figure which shows the bit allocation result from the 1st bit-the 6th bit after the bit replacement of 64APSK which concerns on 2nd Embodiment by this invention. It is a figure which shows the C / N versus bit error rate characteristic before the error correction for every bit after the bit replacement of 64APSK which concerns on 2nd Embodiment by this invention. It is a figure which shows the division | segmentation process from the 1st bit to the 6th bit after the 64 APSK bit replacement according to the second embodiment of the present invention. As Example 1 according to the second embodiment of the present invention, the first bit LDPC coding rate 61/120, the second bit LDPC coding rate 63/120, the third bit LDPC coding rate 101/120, the fourth bit Example of slot configuration for LDPC coding rate 115/120, 5th bit LDPC coding rate 116/120, 6th bit LDPC coding rate 120/120 (no LDPC parity), and BCH (65535, 65343) shortened code FIG. As Example 2 according to the second embodiment of the present invention, information bits are configured in units of bytes in all code sequences, and a first bit LDPC coding rate 61/120, a second bit LDPC coding rate 63/120, 3rd bit LDPC coding rate 101/120, 4th bit LDPC coding rate 115/120, 5th bit LDPC coding rate 116/120, 6th bit LDPC coding rate 120/120 (no LDPC parity), and It is a figure which shows the example of a slot structure in the case of BCH (65535, 65343) shortened code. As Example 3 according to the second embodiment of the present invention, the first bit LDPC coding rate 61/120, the second bit LDPC coding rate 63/120, the third bit LDPC coding rate 101/120, the fourth bit Example of slot configuration for LDPC coding rate 115/120, 5th bit LDPC coding rate 116/120, 6th bit LDPC coding rate 120/120 (no LDPC parity), and BCH (65535, 65167) shortened code FIG. It is a figure which shows the C / N vs. bit error rate characteristic which compares Example 3 which concerns on 2nd Embodiment by this invention, and the technique of a nonpatent literature 9. FIG. It is a figure which shows the required C / N comparison result which compares Example 3 which concerns on 2nd Embodiment by this invention, and the technique of a nonpatent literature 9. FIG. It is a figure which shows the example of a division | segmentation of the set division | segmentation method in conventional 8PSK. It is a figure which shows the example of a division | segmentation of the set division | segmentation method in conventional 16QAM. It is a figure which shows the example of a division | segmentation of the set division | segmentation method in conventional 32QAM. It is a figure which shows bit allocation of DVB-S2X of a prior art.

  Hereinafter, the transmission system of the first embodiment will be described with reference to FIGS. 1 to 13, and the transmission system of the second embodiment will be described with reference to FIGS. 14 to 25.

[First Embodiment]
First, the transmission device 10 and the reception device 20 in the transmission system of the first embodiment will be described. FIG. 1 is a block diagram of a transmission device 10 and a reception device 20 according to the first embodiment of the present invention. Note that the actual transmission device 10 provides the receiver with information such as the function of multiplexing the synchronization signal with the modulated wave signal in order to identify the head of the error correction code, the setting of the transmission method employed in ISDB-S, etc. It has a function of multiplexing a transmission multiplex control signal (also referred to as a TMCC signal) for notification to a modulated wave signal. In addition, the actual receiving device 20 detects information such as a synchronization detection function that detects a synchronization signal multiplexed with a modulated wave signal and detects the head of an error correction code, and a transmission method setting from a transmission multiplexing control signal. However, the detailed illustration of the control function for setting the modulation system and coding rate is omitted.

(Device configuration)
[Transmitter]
Referring to FIG. 1, a transmission apparatus 10 according to the first embodiment is a forward error correction transmission apparatus, and includes a serial / parallel conversion unit 11, an error correction coding unit 12, and a coding rate setting unit 13. A mapping unit 14, an orthogonal modulation unit 15, and a coding rate determination signal multiplexing unit 16. That is, the functional block configuration of the transmission device 10 is the same as that of the coded modulation transmission device based on the set division method, but the processing of the error correction coding unit 12, the coding rate setting unit 13, and the accompanying mapping unit 14 are the conventional techniques. And different.

The serial / parallel converter 11 is configured such that a 1-bit transmission data sequence is M = log ₂ L-bit data sequence (in the case of 64-value modulation, M = log ₂ 64 = 6-bit series) and sent to the error correction coding unit 12.

  The error correction encoding unit 12 includes a first error correction encoding unit 12-1 to a sixth error correction encoding unit 12-6, and encodes with a predetermined error correction code (for example, a BCH code and an LDPC code). The six code sequences are generated.

  Each of the first error correction encoding unit 12-1 to the sixth error correction encoding unit 12-6 uses an outer code as a BCH (65535, 65343) shortened code, for example, as Example 1 described later, and an inner code as a code length. This is a 44880 LDPC code. Further, when the coding rate applied to the LDPC code described later is 120/120, no LDPC parity is added, and error correction coding is performed using only a BCH (65535, 65343) shortened code as Example 1 described later. .

  The coding rate setting unit 13 individually sets the coding rate of the LDPC code for each bit of the symbol constituent bits in the set division method. In particular, the LDPC code according to the present invention has an average coding rate of 96/120 (i.e., 4/5), and each bit of 64APSK modulation based on the set division method has the coding rate setting unit of the first embodiment. 13 will be described later in detail with reference to FIGS. 9 to 11. In Examples 1 to 3 according to the first embodiment, the coding rate is 57/120 for the first bit and the coding rate for the second bit. 64/120, 105/120 for the 3rd bit, 117/120 for the 4th bit, 120/120 for the 5th bit (no LDPC parity), and 6 for the 6th bit An encoding rate of 113/120 is set.

  Thereby, the error correction encoding unit 12 is set with a coding rate in consideration of the correction capability of the symbol constituent bits by the set division method, and can perform LDPC encoding having sufficient correction capability. Accordingly, it is possible to increase the frequency use efficiency in the set division method.

  In the example of the first embodiment, the LDPC code length is 44880, which is the same code length as that of the advanced satellite broadcasting system (see Non-Patent Document 5). In the slot configuration of each embodiment described later, the same assignment can be applied starting with the slot header. In addition, the mapping unit 14 to be described later can perform mapping that does not cause excessive or insufficient bit allocation when 64 APSK is applied.

  The mapping unit 14 uses the six code sequences as input symbol sequences, and outputs the I-axis and Q-axis amplitude values of the signal points corresponding to the symbols to the orthogonal modulation unit 15 as IQ signal point sequences. Here, the signal point arrangement of 64APSK by the mapping unit 14 of the first embodiment is the signal of Non-Patent Document 9 in consideration of nonlinear distortion and the adaptive equalization performance of the receiving apparatus, as will be described later with reference to FIG. This is a signal point arrangement in which the signal points of the third circle are distributed to two points and the fourth circle from the point arrangement. As an example of bit allocation based on this signal point arrangement, FIG. 6 shows an example of bit allocation to symbols when the set division method in 64APSK according to the first embodiment of the present invention is applied. FIG. 8 shows a 64APSK set partitioning process when the set partitioning method based on mapping shown in FIG. 6 is applied. In other words, the correspondence between the symbols and signal points used in the mapping according to the present invention is set division assigned in the order shown in FIGS. 8 (a) to 8 (f) while the division of each bit in the symbol constituent bits is advanced. Use the law.

  Therefore, the mapping unit 14 functions as a symbol / signal point conversion unit that converts an input symbol sequence composed of a plurality of code sequences into a signal point sequence based on the correspondence.

  The quadrature modulation unit 15 performs a roll-off filter process on the IQ signal generated by the mapping unit 14, generates a modulated wave signal subjected to quadrature modulation, and transmits the modulated wave signal to an external transmission path. The transmission line in this case is, for example, a non-linear transmission line via a 12 GHz band satellite repeater.

  The coding rate determination signal multiplexing unit 16 receives from the coding rate setting unit 13 coding rate information for each bit of the symbol configuration bits set for the error correction coding unit 12 by the coding rate setting unit 13. It has a function of multiplexing the modulated wave signal in the quadrature modulation unit 15 so as to transmit by a transmission multiplexing control signal (that is, TMCC signal).

[Receiver]
The receiving device 20 of the first embodiment is a receiving device of a forward error correction method, and includes an orthogonal demodulator 21, first to sixth bit log likelihood ratio calculating units 22-1 to 22-6, To sixth bit error correction decoding units 23-1 to 23-6, a parallel / serial conversion unit 24, a coding rate determination unit 25, and an adaptive equalization unit 26. That is, the functional block configuration of the receiving device 20 is the same as that of the coded modulation receiving device by the set division method, but the processing of the orthogonal demodulating unit 21 and the first to sixth bit error correction decoding units 23-1 to 23-6. Is different from the conventional technique.

  The orthogonal demodulator 21 transmits a 64APSK modulated wave signal obtained by modulating the signal point sequence of the IQ signal based on the correspondence relationship between the symbol and the signal point obtained by the set division method according to the present invention, via a nonlinear transmission path. Then, the signal is received from the transmitting apparatus 10 and subjected to orthogonal demodulation processing corresponding to the 64 APSK signal point arrangement for the modulated wave signal to generate a demodulated signal and output it to the adaptive equalization unit 26. The received signal point series corresponding to the main signal symbol is output to each of first to sixth bit log likelihood ratio calculation units 22-1 to 22-6. Accordingly, the orthogonal demodulation unit 21 recovers and outputs the signal point sequence of the IQ signal modulated based on the correspondence between the symbol and the signal point obtained by the set division method according to the present invention by orthogonal demodulation, and outputs the orthogonal signal. Functions as a means.

  The adaptive equalization unit 26 performs adaptive equalization processing on the demodulated signal, thereby converting the received signal point series compensated for distortion caused by the nonlinear transmission path into first to sixth bit log likelihood ratio calculation units 22. -1 to 22-6.

  The first bit log likelihood ratio calculation unit 22-1 uses 1 and 0 for the first bit constituting the symbol based on the correspondence between the symbol and the signal point obtained by the set division method according to the present invention. Are calculated, and the natural logarithm (LLR: log likelihood ratio) of the ratio P11 / P10 is calculated and sent to the first bit error correction decoding unit 23-1.

  The first bit error correction decoding unit 23-1 encodes the first bit constituting the symbol using the log likelihood ratio of the first bit by the first bit log likelihood ratio calculation unit 22-1. The inner code error correction is performed in accordance with the LDPC code check matrix corresponding to the coding rate 57/120 which is the coding rate information for the first bit obtained from the rate discriminating unit 25, and the LDPC decoding result is used as an input. In the first embodiment, outer code error correction is performed according to a BCH (65535, 65343) shortened code generation polynomial, and the decoding result of the first bit is converted into a second bit log likelihood ratio calculation unit 22-2 and a parallel / serial conversion unit. 24.

  The second bit log likelihood ratio calculation unit 22-2 uses the log likelihood of the second bit constituting the symbol in the same manner as the first bit based on the correspondence between the symbol and the signal point obtained by the set division method according to the present invention. The degree ratio is calculated and sent to the second bit error correction decoding unit 23-2.

  The second bit error correction decoding unit 23-2 encodes the second bit constituting the symbol using the log likelihood ratio of the second bit by the second bit log likelihood ratio calculation unit 22-2. The inner code error correction is performed according to the LDPC code check matrix corresponding to the coding rate 64/120, which is the second bit coding rate information obtained from the rate discriminating unit 25, and the LDPC decoding result is used as an input. In the first embodiment, outer code error correction is performed according to a BCH (65535, 65343) shortened code generation polynomial, and the decoding result of the second bit is converted into a third bit log likelihood ratio calculation unit 22-3 and a parallel / serial conversion unit. 24.

  The third bit log likelihood ratio calculation unit 22-3 is similar to the first and second bits for the third bit constituting the symbol based on the correspondence between the symbol and the signal point obtained by the set division method according to the present invention. And the log likelihood ratio is calculated and sent to the third bit error correction decoding unit 23-3.

  The third bit error correction decoding unit 23-3 encodes the third bit constituting the symbol using the log likelihood ratio of the third bit by the third bit log likelihood ratio calculation unit 22-3. The inner code error correction is performed according to the LDPC code check matrix corresponding to the coding rate 105/120, which is the third bit coding rate information obtained from the rate discriminating unit 25, and the LDPC decoding result is used as an input. In the first embodiment, outer code error correction is performed according to the BCH (65535, 65343) shortened code generation polynomial, and the third bit decoding result is converted into a fourth bit log likelihood ratio calculation unit 22-4 and a parallel / serial conversion unit. 24.

  The fourth bit log likelihood ratio calculation unit 22-4 performs the first, second, and second operations on the fourth bit constituting the symbol based on the correspondence between the symbol and the signal point obtained by the set division method according to the present invention. The log likelihood ratio is calculated in the same manner as for 3 bits and sent to the fourth bit error correction decoding unit 23-4.

  The fourth bit error correction decoding unit 23-4 uses the fourth bit log likelihood ratio calculation unit 22-4 to encode the fourth bit constituting the symbol with respect to the fourth bit log likelihood ratio calculation unit 22-4. The inner code error correction is performed according to the LDPC code check matrix corresponding to the coding rate 117/120, which is the fourth bit coding rate information obtained from the rate discriminating unit 25, and the LDPC decoding result is used as an input. The outer code error correction is executed according to the BCH (65535, 65343) shortened code generation polynomial of the first embodiment, and the decoding result of the fourth bit is sent to the parallel / serial converter 24.

  The fifth bit log likelihood ratio calculation unit 22-5 performs the first, second, and second operations on the fifth bit constituting the symbol based on the correspondence between the symbol and the signal point obtained by the set division method according to the present invention. 3. Similarly to the fourth and fourth bits, the log likelihood ratio is calculated and sent to the fifth bit error correction decoding unit 23-5.

  The fifth bit error correction decoding unit 23-5 uses the fifth bit log likelihood ratio calculation unit 22-5 to encode the fifth bit constituting the symbol, using the fifth bit log likelihood ratio calculation unit 22-5. The outer code error correction according to the BCH (65535, 65343) shortened code generation polynomial of Example 1 described later, for example, corresponding to the coding rate 120/120, which is the fifth bit coding rate information obtained from the rate discriminating unit 25 And the decoding result of the fifth bit is sent to the parallel / serial converter 24.

  The sixth bit log-likelihood ratio calculation unit 22-6 first, second, and second for the sixth bit constituting the symbol based on the correspondence between the symbol and the signal point obtained by the set partitioning method according to the present invention. Similarly to the third, fourth and fifth bits, the log likelihood ratio is calculated and sent to the sixth bit error correction decoding unit 23-6.

  The sixth bit error correction decoding unit 23-6 encodes the sixth bit constituting the symbol using the sixth bit log likelihood ratio calculation unit 22-6 by using the sixth bit log likelihood ratio calculation unit 22-6. The inner code error correction is performed according to the LDPC code check matrix corresponding to the coding rate 113/120, which is the sixth bit coding rate information obtained from the rate discriminating unit 25, and the LDPC decoding result is input, The outer code error correction is executed according to the BCH (65535, 65343) shortened code generation polynomial of the first embodiment, and the sixth bit decoding result is sent to the parallel / serial converter 24.

  In this way, the first to sixth bit log likelihood ratio calculation units 22-1 to 22-6 and the first to sixth bit error correction decoding units 23-1 to 23-6 are obtained by the set partition method. Based on the correspondence relationship between the symbols and signal points, successive decoding is performed using the decoding result obtained for each bit and the log likelihood ratio. Accordingly, the first to sixth bit log likelihood ratio calculation units 22-1 to 22-6 and the first to sixth bit error correction decoding units 23-1 to 23-6 perform the above set division to perform signal division. It functions as a decoding unit that decodes each symbol constituent bit based on the correspondence between the symbol assigned signal points and the symbols.

  The parallel / serial conversion unit 24 performs parallel / serial conversion on the decoding result of the data series corresponding to the bits constituting the symbols obtained from the first to sixth bit error correction decoding units 23-1 to 23-6, and outputs 1 bit. The received data series is sent to the outside.

  The code rate discriminating unit 25 informs the receiving device 20 of information obtained from the orthogonal demodulating unit 21 such as a function of multiplexing a synchronization signal with a modulated wave signal and a transmission method setting in order to identify the head of the error correction code. The transmission multiplexing control signal is input, and the first to sixth bit error correction decoding units 23-1 to 23-6 are used to determine the first to sixth bit coding rate information from the transmission multiplexing control signal. Are sent to the first to sixth bit error correction decoding units 23-1 to 23-6, respectively.

(64APSK signal point arrangement and bit allocation)
Here, the 64APSK signal point arrangement and bit allocation in the mapping unit 14 will be described in detail. As described above as a problem to be solved, in the satellite transmission system, as shown in Non-Patent Document 9, by designing the signal point arrangement in consideration of the nonlinear distortion generated in the satellite repeater and the adaptive equalization performance of the receiver. The transmission performance can be improved as compared with the case where the signal point arrangement optimized under white noise is applied.

  Therefore, in order to improve the performance of 64APSK coded modulation in the satellite transmission system, it was decided to study the design of the signal point arrangement in consideration of the nonlinear distortion and the adaptive equalization performance of the receiving apparatus. FIG. 2A shows reception signal points and transmission signal points shown in Non-Patent Document 9 when passing through a nonlinear transmission path. This received signal point is subjected to adaptive equalization processing after being influenced by nonlinear distortion. Here, when the four concentric circles are defined as the first circle, the second circle, the third circle, and the fourth circle in order from the smallest radius, if the received signal points of the second circle and the third circle are focused, the transmission Many received signal points that are out of the vicinity of the signal point are confirmed. It can be seen that the signal points of the second circle and the third circle are affected by an equalization error, which deteriorates MER, which is one of the indexes for evaluating the reception performance. Therefore, in the first embodiment of the present invention, as shown in FIG. 2B, the signal points of the third circle of Non-Patent Document 9 are distributed to the fourth circle with a small equalization error. Thereafter, the phase and the radius ratio were designed so that the transmission path capacity described later is maximized. As described above, the performance improvement in the nonlinear transmission path is possible by applying the signal point arrangement considering the nonlinear distortion and the adaptive equalization performance of the receiving apparatus.

A transmission path capacity T (equation (1)), which is a Shannon limit that limits the modulation method, is used as a design standard for the phase and radius ratio. The transmission line capacity T is defined by the equation (1) when the transmission symbol x and the reception symbol y are used in the AWGN transmission line. M is the number of signal points, p (y | x) is the transition probability density function determined from the C / N and the minimum Euclidean distance between the signal points shown in Equation (2), and σ ² is the white noise power. The first term of equation (1) is the average information amount of the received symbol y and is determined from the number of signal points M. The second term of Equation (1) indicates the average amount of information in which the received symbol is y when a certain transmission symbol x is transmitted.

  Here, considering that the transmission line capacity T is maximized, when the number of signal points M and C / N are fixed, the value of the second term of Equation (1) may be minimized. At this time, the second term of Equation (1) is a function of the minimum Euclidean distance between signal points, and the second term becomes smaller as the minimum Euclidean distance increases. Therefore, maximizing the transmission line capacity T in Equation (1) is equivalent to increasing the minimum Euclidean distance between signal points. By expanding the minimum Euclidean distance between signal points, it is possible to reduce the possibility that a certain received symbol is erroneously received as another adjacent symbol, leading to an improvement in the error rate after reception.

  As described above, by designing the signal point arrangement in consideration of the nonlinear distortion and the adaptive equalization performance of the receiving apparatus, the number of signal points in the third circle, which is likely to cause an equalization error, can be reduced. Leads to improved transmission performance. As a specific signal point arrangement design method, the number of signal points arranged on the circumference is divided into 2 points and 4 circles in the signal point arrangement of Non-Patent Document 9, and the phase of the signal points As for the radius ratio between the circumferences, the respective values were designed so that the transmission line capacity shown in the equation (1) is maximized.

  More specifically, in the 64APSK signal point arrangement design of the present invention, the number of signal points arranged on the circumference is designed in consideration of nonlinear distortion and the adaptive equalization performance of the receiving apparatus, and the phase and radius ratio are determined. Is designed so that the transmission line capacity calculated by the equation (1) is maximized with the number of signal points M = 64 and the design C / N = 16 dB. The design C / N is C / N = 16 dB with a performance target of a gap of about 1 dB against the theoretical limit C / N = 14.9 dB of 64APSK (LDPC coding rate 4/5).

As shown in FIG. 3, the design parameters include (a) the number of signal points on the signal point arrangement of each of the first circle to the fourth circle, and (b) the phase of each signal point of the first circle to the fourth circle ( The first phase θ ₀ 1 to θ ₀ 4 and the phase interval θ1 to θ4 in each circle counterclockwise with respect to the reference phase of 0 degree on the I axis), (c) Radius ratio between the circumferences regarding the first circle to the fourth circle (Γ1 to γ3), and the respective design parameters were determined so as to maximize the transmission path capacity. The radii of the first circle to the fourth circle were defined as r1 to r4, and the radius ratios were defined as γ1 = r2 / r1, γ2 = r3 / r1, and γ3 = r4 / r1 with reference to r1.

  Table 11 shows the designed signal point arrangement of 64APSK. Table 11 shows the signal point coordinates of the IQ signal normalized by the transmission power 1 generated by this design. Further, Table 12 shows each design parameter and transmission path capacity optimized corresponding to the signal point arrangement in Table 11 so that they can be compared with DVB-S2X.

  Next, the bit allocation to the 64 APSK signal point arrangement is also optimized. In the multilevel coding modulation to which the set division method, which is a conventional technique, is applied, signal points are divided according to the decoding result of the previous bit based on the set division method, and each bit is demodulated. For example, the demodulation of the second bit (a2) is demodulated after being divided into signal points of a1 = 0 and a1 = 1 according to the demodulation result of the first bit (a1), and the second and subsequent bits are also subjected to the same procedure. The signal points are divided and demodulated. In this way, each time the signal points are divided, the minimum Euclidean distance between the signal points can be increased, and the BER characteristic of each bit becomes higher as it goes to the upper bit (the first bit is the least significant bit). It is possible to improve and improve the transmission characteristics as a whole.

  In order to apply the set division method in this way, it is necessary to assign bits to each signal point so that the minimum Euclidean distance of the signal points after division is as large as possible. For QAM and other signal points having a grid arrangement, bit allocation that expands the minimum Euclidean distance between geometrically adjacent signal points is possible, but the signal point arrangement is not uniquely determined as in APSK. For a simple modulation scheme, it is difficult to increase the minimum Euclidean distance geometrically.

  Therefore, in the 64APSK mapping according to the present invention, bit allocation to each signal point is performed based on the transmission path capacity T (Equation (1)). As described above, maximizing the transmission line capacity is equivalent to increasing the minimum Euclidean distance. Therefore, by performing bit allocation that maximizes the transmission path capacity after signal point division, when the set division method is applied to 64 APSK, it is possible to increase the minimum Euclidean distance after signal point division.

  Specifically, the transmission path capacity equation (1) is applied as an evaluation function when assigning bits to the 64APSK signal point arrangement based on the set division method, and the transmission path capacity after signal division at C / N = 16 dB. Bit allocation is performed so that becomes the maximum. As a result of assigning the first to sixth bits to the signal point based on the transmission path capacity, the result shown in FIG. 4 is obtained. In FIG. 4, the 6 bits assigned to the signal points are defined in order from the left as the first bit (a1), the second bit (a2),..., The sixth bit (a6). It is written in. FIG. 5 shows the BER characteristic before error correction for each bit, which corresponds to the output of the orthogonal demodulation unit 21 on the receiving device 20 side.

However, as a 64APSK error correction code based on the set division method, a current standard (ISDB-S3: Non-Patent Document) is used to apply a concatenated code consisting of an LDPC code (inner code) and a BCH code (outer code) for each bit. The LDPC code adopted in 5) can be designed with the randomness of the code maintained within the range of BER before error correction from 1.5 × 10 ⁻¹ to 2.0 × 10 ⁻³ . Further, when a BCH (65535, 65167, t = 23) code is applied as an outer code, the BER before error correction in which pseudo error free (1 × 10 ⁻¹¹ ) can be expected is 1.2 × 10 ⁻⁴ or less. . Here, focusing on C / N = 16 ^dB in FIG. 5, the BER of the first bit is 1.96 × 10 ^−1, which is outside the LDPC code design range.

  Therefore, by performing bit replacement from the bit allocation of FIG. 4, bit allocation is performed such that the BER of the first bit to the sixth bit can be error-corrected within the LDPC code application range or only with the BCH code. FIG. 6 shows the bit allocation result at that time, and FIG. 7 shows the BER characteristics before error correction for each bit. In addition, FIG. 8 shows the result of division by the set division method up to the first to sixth bits after this bit replacement. For simplicity, FIG. 8 shows a case where a1 = 0, a2 = 0, a3 = 0, a4 = 0, and a5 = 0, and the other division results are omitted.

  That is, the mapping unit 14 according to the first embodiment performs mapping as shown in Table 13 as bit allocation of each bit constituting a symbol with respect to the 64APSK signal point arrangement as shown in FIG.

(Code parameters of LDPC codes of Examples 1 to 3)
Here, from the BER characteristics of FIG. 7, the BER of the fifth bit (a5) at C / N = 16 dB is 1.17 × 10 ⁻⁴ , and error-free can be achieved with only the BCH outer code. Finally, in the present invention, the LDPC coding rate applied to the first bit (a1) to the fourth bit (a4) and the sixth bit (a6) while satisfying the overall average coding rate 4/5 of the LDPC code. And an LDPC code that minimizes the required C / N (defined as BER = 1 × 10 ⁻¹¹ equivalent C / N) under white noise.

  At this time, the structure of the LDPC check matrix was the same as ISDB-S3. That is, the error correction encoding unit 12 is configured to include an encoder that performs LDPC encoding of the digital data using a unique check matrix for each encoding rate, and this encoder is a code of 44880 bits. Using a parity check matrix initial value table predetermined for each coding rate as an initial value as an initial value, one element of a submatrix corresponding to the information length according to the coding rate is arranged in a column direction at intervals of 374 columns. LDPC encoding is performed using the check matrix configured as described above.

  As the specifications of the designed LDPC code, the coding rate for each bit shown in Table 14 satisfies the average coding rate 4/5 of the entire LDPC code, and Examples 1 to 3 shown in FIGS. 9 to 11 respectively. Slot configuration. The initial value table of the check matrix in the LDPC code for each bit shown in Table 14 is as shown in Tables 1 to 5 described above.

  In the slot configuration of the first embodiment shown in FIG. 9, it is assumed that a variable length packet configured in units of bytes such as a TLV packet is accommodated by utilizing the slot header area. In this slot configuration, when viewed for each code sequence constituting the slot, the information bits are not configured in units of bytes, and it becomes difficult to write byte information indicating breaks in the variable-length packet in the slot header area. It is expected that.

  Therefore, as in the second embodiment shown in FIG. 10, by using a slot configuration in which information bits are configured in units of bytes for each code sequence of bits, information indicating the breaks in variable-length packets configured in units of bytes. Can be accommodated while ensuring the function of writing to the slot header area.

  Further, in order to apply a BCH code having a higher correction capability as an outer code, a slot having a code length of 44880 bits is replaced with the slot of the third embodiment as shown in FIG. 11 using a BCH (65535, 65167) shortened code. It can be configured.

  That is, the slot configuration of the first embodiment shown in FIG. 9 is provided with a 176-bit slot header and 6-bit stuff bits, as in the conventional slot configuration of the advanced satellite broadcasting system. However, in the target required C / N, the bit error of the fifth bit (a5) out of each bit of the symbol constituent bits becomes so large that it cannot be sufficiently corrected only by the BCH (65535, 65343) shortened code. In addition, it is desirable to enhance the correction capability without changing the code length of 44880 bits. Also, by applying the BCH (65535, 65167) shortened code to each bit from the first bit to the fourth bit and the sixth bit (a6), the influence of error propagation when sequentially decoding from the first bit is reduced. It becomes possible to do.

  Therefore, as shown in FIG. 11, in the slot configuration of the third embodiment, the slot header area is deleted, the deleted 176 bits are allocated to the parity of the BCH code, and the BCH (65535, 65343) shortening with a correction capability of 12 bits is performed. The code is strengthened to a BCH (65535, 65167) shortened code having a correction capability of 23 bits. Even if the slot header is deleted in this way, there is no problem in signal identification by providing information capable of identifying both of them in the transmission multiplex control signal.

  Thereby, when the target required C / N is sufficiently high (that is, when the target value is higher than the required C / N determined by the BCH (65535, 65343) shortened code), the slot configuration of the third embodiment (FIG. 11) can be employed, and therefore the slot configuration of the first or second embodiment (FIGS. 9 and 10) and the slot configuration of the third embodiment (FIG. 11) according to the target required C / N. ) Can be switched and adopted.

  A generator polynomial for the BCH (65535, 65167) shortened code is as disclosed in Patent Document 1. Further, the generator polynomial for the BCH (65535, 65343) shortened code is as disclosed in Non-Patent Document 5.

  As an effect of the present invention, the transmission performance (simulation result) when the slot configuration of FIG. 11 is used in the transmission device 10 and the reception device 20 of FIG. 1 will be described. The transmission model assumes white noise, the BCH outer code is a BCH (65535, 65167, t = 23) code, and the number of decoding iterations of the LDPC code is set to a maximum of 50 times per stage.

In accordance with Table 14, FIG. 12 shows C / N vs. BER characteristics by computer simulation in a non-linear transmission path that is assumed to be via a 12 GHz band satellite repeater in this example. In FIG. 12, the simulation result of Non-Patent Document 9 when the nonlinear transmission model is propagated is also plotted. The computer simulation was performed up to BER = 10 ⁻⁸ order, and extrapolated to BER = 1 × 10 ⁻¹¹ by linear interpolation. The results obtained from FIG. 12 are shown in FIG. From FIG. 13, in the nonlinear transmission path that is assumed to be via a 12 GHz band satellite repeater, the required C / N of the technology of the present invention is 17.18 dB, which can be improved by 0.34 dB from Non-Patent Document 9. .

  In particular, in the technique of Non-Patent Document 9, as a new signal point arrangement of 64APSK, the number of signal points arranged on four concentric circles is optimized from the viewpoint of expanding the Euclidean distance, and each of the four concentric circles is optimized. It is assumed that the amplitude values of the signal points are substantially matched and the phase value of each signal point is adjusted. On the other hand, in the newer signal point arrangement of 64APSK according to the first embodiment of the present invention, non-patent document 9 describes the equalization from the signal point arrangement as a signal point arrangement taking into account nonlinear distortion and the adaptive equalization performance of the receiving apparatus. The signal points of the third circle, which are likely to cause errors, are distributed to two points and the fourth circle.

  Further, in the bit allocation by the set division method using the 64APSK further new signal point arrangement according to the present invention, the predetermined signal power vs. noise described above from the bit allocation optimized based on the calculation method based on the equation (1). The bit error rate can be further suppressed by performing bit replacement so as to satisfy the power ratio.

  Further, the error correction code based on the new 64APSK signal constellation and bit allocation by the new set partitioning method according to the present invention, the entire slot configuration of 6 slots as a concatenated code by the LDPC code and the BCH code. The average coding rate of the LDPC code is 4/5, the LDPC coding rate of each slot in the 6 slots is defined as shown in Table 14, and the parity check matrix initial value of the LDPC code in the set partitioning method is defined. The transmission performance can be further improved by optimizing the table.

  As a result, in the configuration of the transmission device 10 and the reception device 20 according to an embodiment of the present invention, for example, a performance improvement of 0.34 dB is achieved with respect to the technique of Non-Patent Document 9 in a nonlinear transmission path via a 12 GHz band satellite repeater. It is possible.

[Second Embodiment]
Next, the transmission device 10 and the reception device 20 in the transmission system of the second embodiment will be described. In addition, the same reference number is attached | subjected to the component similar to 1st Embodiment. FIG. 1 is a block diagram of a transmission device 10 and a reception device 20 according to the first embodiment of the present invention. Note that the actual transmission device 10 provides the receiver with information such as the function of multiplexing the synchronization signal with the modulated wave signal in order to identify the head of the error correction code, the setting of the transmission method employed in ISDB-S, etc. It has a function of multiplexing a transmission multiplex control signal (also referred to as a TMCC signal) for notification to a modulated wave signal. In addition, the actual receiving device 20 detects information such as a synchronization detection function that detects a synchronization signal multiplexed with a modulated wave signal and detects the head of an error correction code, and a transmission method setting from a transmission multiplexing control signal. However, the detailed illustration of the control function for setting the modulation system and coding rate is omitted.

(Device configuration)
[Transmitter]
Referring to FIG. 14, a transmission apparatus 10 according to the second embodiment is a forward error correction transmission apparatus, and includes a serial / parallel conversion unit 11, an error correction coding unit 12, and a coding rate setting unit 13. A mapping unit 14, an orthogonal modulation unit 15, and a coding rate determination signal multiplexing unit 16. That is, the functional block configuration of the transmission device 10 is the same as that of the coded modulation transmission device based on the set division method, but the processing of the error correction coding unit 12, the coding rate setting unit 13, and the accompanying mapping unit 14 are the conventional techniques. And different.

The serial / parallel converter 11 is configured such that a 1-bit transmission data sequence is M = log ₂ L-bit data sequence (in the case of 64-value modulation, M = log ₂ 64 = 6-bit series) and sent to the error correction coding unit 12.

  The error correction encoding unit 12 includes a first error correction encoding unit 12-1 to a sixth error correction encoding unit 12-6, and encodes with a predetermined error correction code (for example, a BCH code and an LDPC code). The six code sequences are generated.

  Each of the first error correction encoding unit 12-1 to the sixth error correction encoding unit 12-6 uses an outer code as a BCH (65535, 65343) shortened code, for example, as Example 1 described later, and an inner code as a code length. This is a 44880 LDPC code. Further, when the coding rate applied to the LDPC code described later is 120/120, no LDPC parity is added, and error correction coding is performed using only a BCH (65535, 65343) shortened code as Example 1 described later. .

  The coding rate setting unit 13 individually sets the coding rate of the LDPC code for each bit of the symbol constituent bits in the set division method. In particular, the LDPC code according to the present invention has an average coding rate of 96/120 (that is, 4/5), and each bit of 64APSK modulation based on the set partitioning method has the coding rate setting unit of the second embodiment. 13 will be described in detail later with reference to FIGS. 21 to 23. In Examples 1 to 3 according to the second embodiment, the coding rate is 61/120 for the first bit and the coding rate for the second bit. 63/120, 101/120 for the third bit, 115/120 for the fourth bit, 116/120 for the fifth bit, 120/120 for the sixth bit (LDPC) Set the coding rate (no parity).

  Thereby, the error correction encoding unit 12 is set with a coding rate in consideration of the correction capability of the symbol constituent bits by the set division method, and can perform LDPC encoding having sufficient correction capability. Accordingly, it is possible to increase the frequency use efficiency in the set division method.

  In the example of the second embodiment, the LDPC code length is 44880, which is the same code length as that of the advanced satellite broadcasting system (see Non-Patent Document 5). In the slot configuration of each embodiment described later, the same assignment can be applied starting with the slot header. In addition, the mapping unit 14 to be described later can perform mapping that does not cause excessive or insufficient bit allocation when 64 APSK is applied.

  The mapping unit 14 uses the six code sequences as input symbol sequences, and outputs the I-axis and Q-axis amplitude values of the signal points corresponding to the symbols to the orthogonal modulation unit 15 as IQ signal point sequences. Here, the 64APSK signal point arrangement by the mapping unit 14 of the second embodiment is different from that of the first embodiment, and the transmission performance in the nonlinear transmission path is considered in consideration of the nonlinear distortion and the adaptive equalization performance of the receiving apparatus. This is a signal point arrangement in which the phase and radius ratio of signal points are designed to be improved. As an example of bit allocation based on this signal point arrangement, FIG. 18 shows a set division method in 64APSK according to the second embodiment of the present invention. An example of bit allocation to symbols when applied is shown. FIG. 20 shows a 64APSK set partitioning process when the set partitioning method by mapping shown in FIG. 18 is applied. In other words, the correspondence between the symbols and signal points used for the mapping according to the present invention is set division assigned in the order shown in FIGS. 20 (a) to 20 (f) while the division of each bit in the symbol constituent bits is advanced. Use the law.

  Therefore, the mapping unit 14 functions as a symbol / signal point conversion unit that converts an input symbol sequence composed of a plurality of code sequences into a signal point sequence based on the correspondence.

  The quadrature modulation unit 15 performs a roll-off filter process on the IQ signal generated by the mapping unit 14, generates a modulated wave signal subjected to quadrature modulation, and transmits the modulated wave signal to an external transmission path. The transmission line in this case is, for example, a non-linear transmission line via a 12 GHz band satellite repeater.

  The coding rate determination signal multiplexing unit 16 receives from the coding rate setting unit 13 coding rate information for each bit of the symbol configuration bits set for the error correction coding unit 12 by the coding rate setting unit 13. It has a function of multiplexing the modulated wave signal in the quadrature modulation unit 15 so as to transmit by a transmission multiplexing control signal (that is, TMCC signal).

[Receiver]
The receiver 20 of the second embodiment is a forward error correction receiver, and includes an orthogonal demodulator 21, first to sixth bit log likelihood ratio calculators 22-1 to 22-6, To sixth bit error correction decoding units 23-1 to 23-6, a parallel / serial conversion unit 24, a coding rate determination unit 25, and an adaptive equalization unit 26. That is, the functional block configuration of the receiving device 20 is the same as that of the coded modulation receiving device by the set division method, but the processing of the orthogonal demodulating unit 21 and the first to sixth bit error correction decoding units 23-1 to 23-6. Is different from the conventional technique.

  The orthogonal demodulator 21 transmits a 64APSK modulated wave signal obtained by modulating the signal point sequence of the IQ signal based on the correspondence relationship between the symbol and the signal point obtained by the set division method according to the present invention, via a nonlinear transmission path. Then, the signal is received from the transmitting apparatus 10 and subjected to orthogonal demodulation processing corresponding to the 64 APSK signal point arrangement for the modulated wave signal to generate a demodulated signal and output it to the adaptive equalization unit 26. The received signal point series corresponding to the main signal symbol is output to each of first to sixth bit log likelihood ratio calculation units 22-1 to 22-6. Accordingly, the orthogonal demodulation unit 21 recovers and outputs the signal point sequence of the IQ signal modulated based on the correspondence between the symbol and the signal point obtained by the set division method according to the present invention by orthogonal demodulation, and outputs the orthogonal signal. Functions as a means.

  The adaptive equalization unit 26 performs adaptive equalization processing on the demodulated signal, thereby converting the received signal point series compensated for distortion caused by the nonlinear transmission path into first to sixth bit log likelihood ratio calculation units 22. -1 to 22-6.

  The first bit log likelihood ratio calculation unit 22-1 uses 1 and 0 for the first bit constituting the symbol based on the correspondence between the symbol and the signal point obtained by the set division method according to the present invention. Are calculated, and the natural logarithm (LLR: log likelihood ratio) of the ratio P11 / P10 is calculated and sent to the first bit error correction decoding unit 23-1.

  The first bit error correction decoding unit 23-1 encodes the first bit constituting the symbol using the log likelihood ratio of the first bit by the first bit log likelihood ratio calculation unit 22-1. The inner code error correction is performed in accordance with the LDPC code check matrix corresponding to the coding rate 61/120 which is the coding rate information for the first bit obtained from the rate discriminating unit 25, and the LDPC decoding result is used as an input. In the first embodiment, outer code error correction is performed according to a BCH (65535, 65343) shortened code generation polynomial, and the decoding result of the first bit is converted into a second bit log likelihood ratio calculation unit 22-2 and a parallel / serial conversion unit. 24.

  The second bit log likelihood ratio calculation unit 22-2 uses the log likelihood of the second bit constituting the symbol in the same manner as the first bit based on the correspondence between the symbol and the signal point obtained by the set division method according to the present invention. The degree ratio is calculated and sent to the second bit error correction decoding unit 23-2.

  The second bit error correction decoding unit 23-2 encodes the second bit constituting the symbol using the log likelihood ratio of the second bit by the second bit log likelihood ratio calculation unit 22-2. The inner code error correction is performed in accordance with the LDPC code check matrix corresponding to the coding rate 63/120 which is the second bit coding rate information obtained from the rate discriminating unit 25, and the LDPC decoding result is used as an input. In the first embodiment, outer code error correction is performed according to a BCH (65535, 65343) shortened code generation polynomial, and the decoding result of the second bit is converted into a third bit log likelihood ratio calculation unit 22-3 and a parallel / serial conversion unit. 24.

  The third bit log likelihood ratio calculation unit 22-3 is similar to the first and second bits for the third bit constituting the symbol based on the correspondence between the symbol and the signal point obtained by the set division method according to the present invention. And the log likelihood ratio is calculated and sent to the third bit error correction decoding unit 23-3.

  The third bit error correction decoding unit 23-3 encodes the third bit constituting the symbol using the log likelihood ratio of the third bit by the third bit log likelihood ratio calculation unit 22-3. The inner code error correction is performed according to the LDPC code check matrix corresponding to the coding rate 101/120 which is the third bit coding rate information obtained from the rate discriminating unit 25, and the LDPC decoding result is input, for example, as described later. In the first embodiment, outer code error correction is performed according to the BCH (65535, 65343) shortened code generation polynomial, and the third bit decoding result is converted into a fourth bit log likelihood ratio calculation unit 22-4 and a parallel / serial conversion unit. 24.

  The fourth bit log likelihood ratio calculation unit 22-4 performs the first, second, and second operations on the fourth bit constituting the symbol based on the correspondence between the symbol and the signal point obtained by the set division method according to the present invention. The log likelihood ratio is calculated in the same manner as for 3 bits and sent to the fourth bit error correction decoding unit 23-4.

  The fourth bit error correction decoding unit 23-4 uses the fourth bit log likelihood ratio calculation unit 22-4 to encode the fourth bit constituting the symbol with respect to the fourth bit log likelihood ratio calculation unit 22-4. The inner code error correction is performed according to the LDPC code check matrix corresponding to the coding rate 115/120, which is the fourth bit coding rate information obtained from the rate discriminating unit 25, and the LDPC decoding result is used as an input. The outer code error correction is executed according to the BCH (65535, 65343) shortened code generation polynomial of the first embodiment, and the decoding result of the fourth bit is sent to the parallel / serial converter 24.

  The fifth bit log likelihood ratio calculation unit 22-5 performs the first, second, and second operations on the fifth bit constituting the symbol based on the correspondence between the symbol and the signal point obtained by the set division method according to the present invention. 3. Similarly to the fourth and fourth bits, the log likelihood ratio is calculated and sent to the fifth bit error correction decoding unit 23-5.

  The fifth bit error correction decoding unit 23-5 uses the fifth bit log likelihood ratio calculation unit 22-5 to encode the fifth bit constituting the symbol, using the fifth bit log likelihood ratio calculation unit 22-5. The inner code error correction is performed in accordance with the LDPC code check matrix corresponding to the coding rate 116/120 which is the fifth bit coding rate information obtained from the rate discriminating unit 25, and the LDPC decoding result is used as an input. The outer code error correction is executed according to the BCH (65535, 65343) shortened code generation polynomial of the first embodiment, and the fifth bit decoding result is sent to the parallel / serial converter 24.

  The sixth bit log-likelihood ratio calculation unit 22-6 first, second, and second for the sixth bit constituting the symbol based on the correspondence between the symbol and the signal point obtained by the set partitioning method according to the present invention. Similarly to the third, fourth and fifth bits, the log likelihood ratio is calculated and sent to the sixth bit error correction decoding unit 23-6.

  The sixth bit error correction decoding unit 23-6 encodes the sixth bit constituting the symbol using the sixth bit log likelihood ratio calculation unit 22-6 by using the sixth bit log likelihood ratio calculation unit 22-6. The outer code error correction according to the BCH (65535, 65343) shortened code generation polynomial of Example 1 described later, for example, corresponding to the coding rate 120/120, which is the fifth bit coding rate information obtained from the rate discriminating unit 25 And the sixth bit decoding result is sent to the parallel / serial converter 24.

  In this way, the first to sixth bit log likelihood ratio calculation units 22-1 to 22-6 and the first to sixth bit error correction decoding units 23-1 to 23-6 are obtained by the set partition method. Based on the correspondence relationship between the symbols and signal points, successive decoding is performed using the decoding result obtained for each bit and the log likelihood ratio. Accordingly, the first to sixth bit log likelihood ratio calculation units 22-1 to 22-6 and the first to sixth bit error correction decoding units 23-1 to 23-6 perform the above set division to perform signal division. It functions as a decoding unit that decodes each symbol constituent bit based on the correspondence between the symbol assigned signal points and the symbols.

  The parallel / serial conversion unit 24 performs parallel / serial conversion on the decoding result of the data series corresponding to the bits constituting the symbols obtained from the first to sixth bit error correction decoding units 23-1 to 23-6, and outputs 1 bit. The received data series is sent to the outside.

  The code rate discriminating unit 25 informs the receiving device 20 of information obtained from the orthogonal demodulating unit 21 such as a function of multiplexing a synchronization signal with a modulated wave signal and a transmission method setting in order to identify the head of the error correction code. The transmission multiplexing control signal is input, and the first to sixth bit error correction decoding units 23-1 to 23-6 are used to determine the first to sixth bit coding rate information from the transmission multiplexing control signal. Are sent to the first to sixth bit error correction decoding units 23-1 to 23-6, respectively.

(64APSK signal point arrangement and bit allocation)
Here, the 64APSK signal point arrangement and bit allocation in the mapping unit 14 will be described in detail. As described above as a problem to be solved, in the satellite transmission system, as shown in Non-Patent Document 9, by designing the signal point arrangement in consideration of the nonlinear distortion generated in the satellite repeater and the adaptive equalization performance of the receiver. The transmission performance can be improved as compared with the case where the signal point arrangement optimized under white noise is applied.

  Therefore, in order to improve the performance of 64APSK coded modulation in the satellite transmission system, it was decided to study the design of the signal point arrangement in consideration of the nonlinear distortion and the adaptive equalization performance of the receiving apparatus. In addition, Fig.11 (a) is the reception signal point and transmission signal point which are shown in the nonpatent literature 9 at the time of letting a non-linear transmission path pass. This received signal point is subjected to adaptive equalization processing after being influenced by nonlinear distortion. Here, when the four concentric circles are defined as the first circle, the second circle, the third circle, and the fourth circle in order from the smallest radius, if the received signal points of the second circle and the third circle are focused, the transmission Many received signal points that are out of the vicinity of the signal point are confirmed. It can be seen that the signal points of the second circle and the third circle are affected by an equalization error, which deteriorates MER, which is one of the indexes for evaluating the reception performance. Therefore, in the second embodiment of the present invention, as shown in FIG. 11B, the MER of the received signal after adaptive equalization is improved and a high transmission path capacity is achieved, as shown in FIG. Designed. As described above, the performance improvement in the nonlinear transmission path is possible by applying the signal point arrangement considering the nonlinear distortion and the adaptive equalization performance of the receiving apparatus.

  As described above, the transmission path capacity T (formula (1) and formula (2)), which is the Shannon limit that limits the modulation scheme as the design standard of the phase and radius ratio, the MER, and the output signal of the satellite repeater is downlinked Equation (3) using the required C / N (required C / Nsat) that takes into account the white noise received at, and the required C / N (required C / Nall) of the entire satellite transmission line finally input to the receiver Use.

  For each signal point arrangement pattern, the required C / Nsat is calculated by Equation (3), and the signal point arrangement that minimizes the required C / Nsat is the signal point arrangement that can improve the transmission performance in the linear transmission path. . The required C / Nall is the transmission path capacity of each signal point arrangement pattern with reference to the achievable transmission path capacity Ts = 5.0839 bps / Hz at which the transmission path capacity T becomes maximum when C / N = 16 dB. Td was converted into required C / Nall (required C / Nall = 16 × Ts / Td), and the value after adaptive equalization was used for MER.

  From the above, considering the nonlinear distortion, the performance of the adaptive equalizer, the transmission path capacity of the signal point arrangement, the value of the phase of the signal point arrangement and the radius ratio between the circumferences to improve the transmission performance in the nonlinear transmission line Designed.

  More specifically, in the 64APSK signal point arrangement design of the present invention, the number of signal points arranged on the circumference is designed in consideration of nonlinear distortion and the adaptive equalization performance of the receiving apparatus, and the phase and radius ratio are determined. Is designed so that the transmission line capacity calculated by the equation (1) is maximized with the number of signal points M = 64 and the design C / N = 16 dB. The design C / N is C / N = 16 dB with a performance target of a gap of about 1 dB against the theoretical limit C / N = 14.9 dB of 64APSK (LDPC coding rate 4/5).

As shown in FIG. 3 described above, the design parameters are (a) the number of signal points on the signal point arrangement of each of the first circle to the fourth circle, and (b) the signal points of each of the first circle to the fourth circle. Phase (first phase θ ₀ 1 to θ ₀ 4 and phase interval θ _{1 to} θ 4 in each circle counterclockwise with respect to the reference phase 0 degree of the I axis), (c) between the circumferences related to the first circle to the fourth circle The design parameters were determined so that the transmission line capacity was maximized with the radius ratio (γ1 to γ3). The radii of the first circle to the fourth circle were defined as r1 to r4, and the radius ratios were defined as γ1 = r2 / r1, γ2 = r3 / r1, and γ3 = r4 / r1 with reference to r1.

  Table 15 shows the designed signal point arrangement of 64APSK. Table 15 shows the signal point coordinates of the IQ signal normalized by the transmission power 1 generated by this design. In addition, Table 16 shows each design parameter and transmission path capacity optimized corresponding to the signal point arrangement in Table 15 so as to be comparable to DVB-S2X.

  Next, the bit allocation to the 64 APSK signal point arrangement is also optimized. In the multilevel coding modulation to which the set division method, which is a conventional technique, is applied, signal points are divided according to the decoding result of the previous bit based on the set division method, and each bit is demodulated. For example, the demodulation of the second bit (a2) is demodulated after being divided into signal points of a1 = 0 and a1 = 1 according to the demodulation result of the first bit (a1), and the second and subsequent bits are also subjected to the same procedure. The signal points are divided and demodulated. In this way, each time the signal points are divided, the minimum Euclidean distance between the signal points can be increased, and the BER characteristic of each bit becomes higher as it goes to the upper bit (the first bit is the least significant bit). It is possible to improve and improve the transmission characteristics as a whole.

  In order to apply the set division method in this way, it is necessary to assign bits to each signal point so that the minimum Euclidean distance of the signal points after division is as large as possible. For QAM and other signal points having a grid arrangement, bit allocation that expands the minimum Euclidean distance between geometrically adjacent signal points is possible, but the signal point arrangement is not uniquely determined as in APSK. For a simple modulation scheme, it is difficult to increase the minimum Euclidean distance geometrically.

  Therefore, in the 64APSK mapping according to the second embodiment of the present invention, the bit allocation to each signal point is performed based on the transmission line capacity T (formula (1)) as in the first embodiment. As described above, maximizing the transmission line capacity is equivalent to increasing the minimum Euclidean distance. Therefore, by performing bit allocation that maximizes the transmission path capacity after signal point division, when the set division method is applied to 64 APSK, it is possible to increase the minimum Euclidean distance after signal point division.

  Specifically, the transmission path capacity equation (1) is applied as an evaluation function when assigning bits to the 64APSK signal point arrangement based on the set division method, and the transmission path capacity after signal division at C / N = 16 dB. Bit allocation is performed so that becomes the maximum. As a result of assigning the first to sixth bits to the signal point based on the transmission path capacity, the result shown in FIG. 16 is obtained. In FIG. 16, the 6 bits assigned to the signal points are defined in order from the left as the first bit (a1), the second bit (a2),..., The sixth bit (a6). It is written in. FIG. 17 shows BER characteristics before error correction for each bit corresponding to the output of the orthogonal demodulator 21 on the receiving device 20 side.

However, as a 64APSK error correction code based on the set division method, a current standard (ISDB-S3: Non-Patent Document) is used to apply a concatenated code consisting of an LDPC code (inner code) and a BCH code (outer code) for each bit. The LDPC code adopted in 5) can be designed with the randomness of the code maintained within the range of BER before error correction from 1.5 × 10 ⁻¹ to 2.0 × 10 ⁻³ . Further, when a BCH (65535, 65167, t = 23) code is applied as an outer code, the BER before error correction in which pseudo error free (1 × 10 ⁻¹¹ ) can be expected is 1.2 × 10 ⁻⁴ or less. . Here, focusing on C / N = 16 ^dB in FIG. 17, the BER of the first bit is 1.97 × 10 ^−1, which is outside the LDPC code design range.

  Therefore, by performing bit replacement from the bit allocation in FIG. 16, bit allocation is performed so that the BER of the first bit to the sixth bit can be error-corrected within the LDPC code application range or only with the BCH code. FIG. 18 shows the bit allocation result at that time, and FIG. 19 shows the BER characteristics before error correction for each bit. In addition, FIG. 20 shows the result of division by the set division method up to the first to sixth bits after this bit replacement. In FIG. 20, for the sake of simplicity, a case where a1 = 0, a2 = 0, a3 = 0, a4 = 0, a5 = 0 is shown, and other division results are omitted.

  That is, the mapping unit 14 according to the second embodiment performs mapping as shown in Table 17 as the bit allocation of each bit constituting the symbol for the 64 APSK signal point arrangement as shown in FIG.

(Code parameters of LDPC codes of Examples 1 to 3)
Here, from the BER characteristics of FIG. 19, the BER of the sixth bit (a6) at C / N = 16 dB is 1.07 × 10 ⁻⁶ , and error-free can be achieved by using only the BCH outer code. Finally, in the present invention, the LDPC code rate applied to the first bit (a1) to the fifth bit (a5) is adjusted while satisfying the overall average code rate 4/5 of the LDPC code, and white noise Below, an LDPC code that minimizes the required C / N (defined as C / N corresponding to BER = 1 × 10 ⁻¹¹ ) was designed.

  At this time, the structure of the LDPC check matrix was the same as ISDB-S3. That is, the error correction encoding unit 12 is configured to include an encoder that performs LDPC encoding of the digital data using a unique check matrix for each encoding rate, and this encoder is a code of 44880 bits. Using a parity check matrix initial value table predetermined for each coding rate as an initial value as an initial value, one element of a submatrix corresponding to the information length according to the coding rate is arranged in a column direction at intervals of 374 columns. LDPC encoding is performed using the check matrix configured as described above.

  As the specifications of the designed LDPC code, the coding rate for each bit shown in Table 18 satisfies the average coding rate 4/5 of the entire LDPC code, and Examples 1 to 3 shown in FIGS. Slot configuration. The initial value table of the check matrix in the LDPC code for each bit shown in Table 18 is as shown in Tables 6 to 10 described above.

  In the slot configuration of the first embodiment shown in FIG. 21, it is assumed that a variable length packet configured in units of bytes such as a TLV packet is accommodated by utilizing the slot header area. In this slot configuration, when viewed for each code sequence constituting the slot, the information bits are not configured in units of bytes, and it becomes difficult to write byte information indicating breaks in the variable-length packet in the slot header area. It is expected that.

  Therefore, as in the second embodiment shown in FIG. 22, by using a slot configuration in which information bits are configured in units of bytes for each code sequence of each bit, information indicating breaks in variable-length packets configured in units of bytes. Can be accommodated while ensuring the function of writing to the slot header area.

  Further, in order to apply a BCH code having a higher correction capability as an outer code, a slot having a code length of 48880 bits is replaced with the slot of the third embodiment as shown in FIG. 23 using a BCH (65535, 65167) shortened code. It can be configured.

  That is, in the slot configuration of the first embodiment shown in FIG. 21, a slot header of 176 bits and 6 bits of stuff bits are provided as in the conventional slot configuration of the advanced satellite broadcasting system. However, in the target required C / N, the bit error of the sixth bit (a6) out of each bit of the symbol constituent bits becomes so large that it cannot be sufficiently corrected only by the BCH (65535, 65343) shortened code. In addition, it is desirable to enhance the correction capability without changing the code length of 44880 bits. Also, by applying the BCH (65535, 65167) shortened code to each bit from the first bit to the fifth bit, it becomes possible to reduce the influence of error propagation when decoding sequentially from the first bit.

  Therefore, as shown in FIG. 23, in the slot configuration of the third embodiment, the slot header area is deleted, the deleted 176 bits are allocated to the parity of the BCH code, and the BCH (65535, 65343) shortening with a correction capability of 12 bits is performed. The code is strengthened to a BCH (65535, 65167) shortened code having a correction capability of 23 bits. Even if the slot header is deleted in this way, there is no problem in signal identification by providing information capable of identifying both of them in the transmission multiplex control signal.

  Thereby, when the target required C / N is sufficiently high (that is, when the target value is higher than the required C / N determined by the BCH (65535, 65343) shortened code), the slot configuration of the third embodiment (FIG. 23) can be employed, and therefore the slot configuration of the first or second embodiment (FIGS. 21 and 22) and the slot configuration of the third embodiment (FIG. 23) according to the target required C / N. ) Can be switched and adopted.

  A generator polynomial for the BCH (65535, 65167) shortened code is as disclosed in Patent Document 1. Further, the generator polynomial for the BCH (65535, 65343) shortened code is as disclosed in Non-Patent Document 5.

  As an effect of the present invention, the transmission performance (simulation result) when the slot configuration of FIG. 23 is used in the transmission device 10 and the reception device 20 of FIG. 14 will be described. The transmission model assumes white noise, the BCH outer code is a BCH (65535, 65167, t = 23) code, and the number of decoding iterations of the LDPC code is set to a maximum of 50 times per stage.

In accordance with Table 14, FIG. 24 shows C / N vs. BER characteristics by computer simulation in a non-linear transmission path that is assumed to be via a 12 GHz band satellite repeater in this example. In FIG. 24, the simulation results of Non-Patent Document 9 when the nonlinear transmission model is propagated are also plotted. The computer simulation was performed up to BER = 10 ⁻⁸ order, and extrapolated to BER = 1 × 10 ⁻¹¹ by linear interpolation. The results obtained from FIG. 24 are shown in FIG. From FIG. 25, in the non-linear transmission path that is assumed to pass through a 12 GHz band satellite repeater, the required C / N of the present technology is 17.14 dB, which can be improved by 0.38 dB from Non-Patent Document 9. .

  In particular, in the technique of Non-Patent Document 9, as a new signal point arrangement of 64APSK, the number of signal points arranged on four concentric circles is optimized from the viewpoint of expanding the Euclidean distance, and each of the four concentric circles is optimized. It is assumed that the amplitude values of the signal points are substantially matched and the phase value of each signal point is adjusted. On the other hand, in the newer signal point arrangement of 64APSK according to the second embodiment of the present invention, the signal point arrangement considering the nonlinear distortion and the adaptive equalization performance of the receiving apparatus is used to improve the transmission performance in the nonlinear transmission path. The points are distributed.

  Further, in the bit allocation by the set division method using the 64APSK further new signal point arrangement according to the present invention, the predetermined signal power vs. noise described above from the bit allocation optimized based on the calculation method based on the equation (1). The bit error rate can be further suppressed by performing bit replacement so as to satisfy the power ratio.

  Further, the error correction code based on the new 64APSK signal constellation and bit allocation by the new set partitioning method according to the present invention, the entire slot configuration of 6 slots as a concatenated code by the LDPC code and the BCH code. The average coding rate of the LDPC code is 4/5, the LDPC coding rate of each slot in the 6 slots is defined as shown in Table 18, and the parity check matrix initial value of the LDPC code in the set partitioning method is defined. The transmission performance can be further improved by optimizing the table.

  As a result, in the configuration of the transmission device 10 and the reception device 20 of the second embodiment according to the present invention, for example, a performance improvement of 0.38 dB is achieved with respect to the technique of Non-Patent Document 9 in a nonlinear transmission path via a 12 GHz band satellite repeater. It is possible.

  Note that the parity check matrix initial value table used for generating the parity check matrix for each LDPC coding rate according to each embodiment of the present invention is not limited to the use of the above-described set partitioning method, but other set partitioning methods and gray code mappings. This is also effective when the LDPC code is applied to the bits constituting the symbol.

  The present invention has been described above with reference to specific embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the technical concept thereof. Accordingly, the transmission device and the reception device according to the present invention are not limited to the above-described embodiments, but are limited only by the description of the scope of claims.

  According to the present invention, for example, when transmitting digital data using 64 APSK while satisfying 34.5 MHz which is a bandwidth available for one satellite repeater in 12 GHz band satellite broadcasting, the transmission bit rate is 150 Mbps or more. In addition, the performance of coded modulation in the combination of error correction code and multilevel modulation (64APSK) can be improved, and for example, the transmission performance in a non-linear transmission path via a 12 GHz band satellite repeater can be improved. Therefore, it is useful for any application using an error correction code and multilevel modulation (64APSK).

DESCRIPTION OF SYMBOLS 10 Transmission apparatus 11 Serial / parallel conversion part 12 Error correction encoding part 12-1 1st error correction encoding part 12-2 2nd error correction encoding part 12-3 3rd error correction encoding part 12-4 4th Error correction coding unit 12-5 Fifth error correction coding unit 12-6 Sixth error correction coding unit 13 Coding rate setting unit 14 Mapping unit 15 Orthogonal modulation unit 16 Coding rate determination signal multiplexing unit 20 Receiver 21 Orthogonal demodulation unit 22-1 First bit log likelihood ratio calculation unit 22-2 Second bit log likelihood ratio calculation unit 22-3 Third bit log likelihood ratio calculation unit 22-4 Fourth bit log likelihood ratio calculation Unit 22-5 fifth bit log likelihood ratio calculation unit 22-6 sixth bit log likelihood ratio calculation unit 23-1 first bit error correction decoding unit 23-2 second bit error correction decoding unit 23-3 third Bit error correction decoder 23- The fourth bit error correction decoding unit 23-5 fifth bit error correction decoding unit 23-6 sixth bit error correction decoder 24 parallel / serial converter 25 coding rate determination unit 26 adaptive equalizer

Claims (15)

A transmission device for transmitting digital data,
Error correction coding means for generating a symbol with an overall average coding rate of 4/5 by applying a concatenated code comprising an LDPC code in part to the digital data and comprising a BCH code;
As a signal point arrangement in the 64APSK modulation system for symbols encoded by the error correction encoding means, four concentric circles are defined as a first circle, a second circle, a third circle, and a fourth circle in order from the smallest radius. And set division with 12 signal points on the first circle, 16 signal points on the second circle, 16 signal points on the third circle, and 20 signal points on the fourth circle. A mapping means for mapping a legal IQ signal;
A quadrature modulation unit that modulates the symbol mapped by the mapping unit by a 64APSK modulation method and transmits a modulated wave signal to a receiving device that performs adaptive equalization processing through a nonlinear transmission path;
The mapping means sets the phase angle in the signal point arrangement as the phase angle for the first circle, 30 degrees from the position of 22 degrees counterclockwise from the reference phase of 0 degrees for the I axis, and the I axis for the second circle. 22.5 degrees from the position of 22.55 degrees counterclockwise with respect to the reference phase of 0 degrees, and the third circle is 22 from the position of 11.45 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis. .5 degree intervals, and the fourth circle is 18 degrees apart from a position of 11.3 degrees counterclockwise with respect to the reference phase of the I axis, and the first circle, as the radius ratio in the signal point arrangement, The radii of the second circle, the third circle, and the fourth circle are defined as r1, r2, r3, and r4, respectively, and the radius ratio with respect to r1 is γ1 = r2 / r1, γ2 = r3 / r1, and γ3 = r4. When defined as / r1, γ1 = 2.02, γ2 = 2.98, γ3 = 4. Mapping of the IQ signal configured to be 14,
The error correction coding means performs LDPC code encoding for each bit of the symbol constituting bits in the set division method at a predetermined number of coding rates determined according to the required correction capability of each bit constituting the symbol. For encoding, the 6 bits of the 64APSK symbol configuration bits having an average coding rate of 4/5, the most significant bit is 57/120 in the first bit, the second bit is 64/120, the third bit 105/120, the fourth bit is 117/120, the fifth bit is 120/120 (no LDPC parity), and the fifth bit, which is the least significant bit, has a coding rate of 113/120. apparatus. A transmission device for transmitting digital data,
Error correction coding means for generating a symbol with an overall average coding rate of 4/5 by applying a concatenated code comprising an LDPC code in part to the digital data and comprising a BCH code;
As a signal point arrangement in the 64APSK modulation system for symbols encoded by the error correction encoding means, four concentric circles are defined as a first circle, a second circle, a third circle, and a fourth circle in order from the smallest radius. And set division with 8 signal points on the first circle, 16 signal points on the second circle, 20 signal points on the third circle, and 20 signal points on the fourth circle. A mapping means for mapping a legal IQ signal;
A quadrature modulation unit that modulates the symbol mapped by the mapping unit by a 64APSK modulation method and transmits a modulated wave signal to a receiving device that performs adaptive equalization processing through a nonlinear transmission path;
The mapping means sets the phase angle in the signal point arrangement as 45 degrees from the position of 58.4 degrees counterclockwise to the reference phase of the I axis for the first circle, and 45 degrees from the left. An interval of 22.5 degrees from a position of 14.55 degrees counterclockwise with respect to the reference phase of 0 degrees on the I-axis, and the third circle is 18 degrees from a position of 18 degrees counterclockwise with respect to the reference phase of 0 degrees on the I-axis. The fourth circle has an interval of 18 degrees from the position of 9 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis, and the radius ratio in the signal point arrangement is the first circle, the second circle, The radii of the third circle and the fourth circle are defined as r1, r2, r3, r4, respectively, and the radius ratio is defined as γ1 = r2 / r1, γ2 = r3 / r1, and γ3 = r4 / r1 with respect to r1. Γ1 = 2.10, γ2 = 3.16, γ3 = 4.49 Mapping of configured IQ signals,
In the LDPC code, the 6 bits of the 64APSK symbol configuration bits having an average coding rate of 4/5 are 61/120 in the first bit, 63/120 in the second bit, and 63/120 in the second bit. 101/120, 115/120 in the 4th bit, 116/120 in the 5th bit, and 120/120 (no LDPC parity) in the 6th bit which is the least significant bit. A transmission device characterized. A modulated wave signal based on a 64APSK IQ signal transmitted from the transmitter according to claim 1 or 2 is received via a non-linear transmission line, and the quadrature demodulation corresponding to the 64APSK signal point arrangement with respect to the modulated wave signal. Orthogonal demodulation means for generating a demodulated signal by performing processing;
Adaptive equalization means for outputting a received signal point sequence compensated for distortion caused by the nonlinear transmission path by performing adaptive equalization processing on the demodulated signal;
Symbol constituent bits comprising a plurality of code sequences that can be divided by 6 bits constituting the 64APSK are acquired from the received signal point sequence, and subjected to LDPC decoding processing using an LDPC code coding rate determined for each bit. And a decoding means for performing a BCH decoding process,
The coding rate of the LDPC code determined for each bit depends on the required correction capability of the symbol divided by the set division method in the bit order from the most significant bit to the least significant bit of the symbol constituting bits. And the average coding rate of the entire LDPC code defined for each bit is 4/5,
The decoding means corrects each bit in order of the first bit, the second bit, the third bit, the fourth bit, the fifth bit, and the sixth bit when performing LDPC decoding on each bit constituting the symbol. An LDPC decoding process is performed using a parity check matrix used for an LDPC code according to the above. An LDPC encoder that LDPC-encodes digital data using a unique check matrix for each coding rate,
The coding rate 57 of the LDPC code set individually for each bit of the symbol constituent bits in the set partitioning method using a parity check matrix initial value table predetermined for each coding rate with a code length of 44880 bits as an initial value. / 120, 61/120, 63/120, 64/120, 101/120, 105/120, 113/120, 115/120, 116/120, 117/120 for one or more coding rates, the information length An LDPC encoder comprising: means for performing LDPC encoding using a parity check matrix configured by arranging one element of a submatrix corresponding to 1 in a column direction with a period of 374 columns. The parity check matrix initial value table of the coding rate 57/120 is:
The LDPC encoder according to claim 4, comprising: The parity check matrix initial value table of the coding rate 64/120 is:
The LDPC encoder according to claim 4, comprising: The parity check matrix initial value table of the coding rate 105/120 is:
The LDPC encoder according to claim 4, comprising: The parity check matrix initial value table of the coding rate 113/120 is:
The LDPC encoder according to claim 4, comprising: The parity check matrix initial value table of the coding rate 117/120 is:
The LDPC encoder according to claim 4, comprising: The parity check matrix initial value table of the coding rate 61/120 is:
The LDPC encoder according to claim 4, comprising: The parity check matrix initial value table of the coding rate 63/120 is:
The LDPC encoder according to claim 4, comprising: The parity check matrix initial value table of the coding rate 101/120 is:
The LDPC encoder according to claim 4, comprising: The parity check matrix initial value table of the coding rate 115/120 is:
The LDPC encoder according to claim 4, comprising: The parity check matrix initial value table of the coding rate 116/120 is:
The LDPC encoder according to claim 4, comprising:   The digital data provided with the parity of the LDPC code by the LDPC encoder according to any one of claims 4 to 14, individually set for each bit of the symbol constituent bits in the set division method An LDPC decoder that performs decoding based on a coding rate of the LDPC code and the parity check matrix.