JP2018101859A - Transmitting apparatus and receiving apparatus - Google Patents

Abstract

A digital data transmitting device and a digital data receiving device are provided. Kind Code: A1 A transmission apparatus 10 according to the present invention performs error correction processing including an LDPC code on data to be transmitted, and an error correction encoder 11 for generating symbols conforming to a 64APSK modulation scheme, and a 64APSK modulation scheme. For the signal point arrangement that maximizes the transmission line capacity based on a predetermined calculation method as the signal point arrangement in the set division method, the bit allocation optimized based on the predetermined calculation method is a predetermined signal power A mapping unit 12 for mapping the IQ signal according to a predetermined bit allocation obtained by performing bit permutation so as to satisfy the power-to-noise ratio. The receiving apparatus 20 of the present invention receives the modulated wave signal transmitted from the transmitting apparatus 10 of the present invention, receives the modulated wave signal based on the 64APSK IQ signal, and quadrature demodulates corresponding to the 64APSK signal point arrangement. A means for applying a treatment is provided. [Selection drawing] Fig. 1

Description

  The present invention relates to the technical fields of satellite broadcasting and terrestrial broadcasting, fixed communication, and mobile communication, and more particularly, to a digital data transmitting apparatus and receiving apparatus.

  As a technique to improve transmission performance under white noise, a coding modulation technique that can improve transmission performance by combining error correction code strength and modulation mapping bits appropriately in digital modulation has been proposed. (For example, refer nonpatent literature 1).

  The coded modulation technique described in Non-Patent Document 1 and the like is also adopted in the Japanese satellite digital broadcasting standard ISDB-S (for example, see Non-Patent Document 2), and has been proven as a technique that contributes to improving transmission performance. There is.

  The basic principle of the technique described in Non-Patent Document 1 is that among the bits constituting the symbol (hereinafter referred to as symbol constituent bits) in consideration of the Euclidean distance between signal points after the bit is mapped to the symbol. In addition, a strong error correction is applied to a bit in which 1/0 is inverted between signal points having a short Euclidean distance, and a bit is weak to a bit in which 1/0 is inverted between signal points having a long Euclidean distance. By performing error correction or not performing encoding processing, noise tolerance is improved while maintaining overall information efficiency.

  Non-Patent Document 1 proposes a method of assigning symbols to signal points called a set division method using 8PSK (phase-shift keying) as an example. The set division method uses a plurality of code sequences that can be divided for each bit as an input symbol sequence, and divides the symbol constituent bits of the input symbol sequence uniformly so that the minimum Euclidean distance between signal points is expanded, This is a transmission method for assigning symbols to signal points used for modulation.

  By the way, the transmission system of the advanced broadband satellite digital broadcasting described in DVB-S2 (see Non-Patent Document 3), DVB-S2X (see Non-Patent Document 4) and ARIB STD-B44 which are European satellite digital broadcasting systems (hereinafter referred to as the following). In the advanced satellite broadcasting system (see Non-Patent Document 5, for example), a gray code is adopted as a technique for assigning symbols to signal points.

  In addition, in the DVB-S2X standard (see Non-Patent Document 4), which is a conventional technique of 64APSK, an example of bit allocation to symbols applied to coding rates 7/9, 4/5, and 5/6 is shown in FIG. Show. In FIG. 10, 6 bits are assigned in order from the left: first bit (a1), second bit (a2),..., Sixth bit (a6), and octal notation every 3 bits from the left (example 64 = 110: 100).

  However, the gray code has a uniform correction capability for each bit in BPSK and QPSK, but in multilevel modulation of 8PSK or more, the error correction capability between bits included in a symbol is non-uniform. This is an obstacle to improving transmission performance at a predetermined coding rate.

  For this reason, a technique for further improving the transmission method based on the set partitioning method and improving the transmission performance when the correction ability of each bit is different is disclosed (for example, patent Reference 1).

  In addition, a new signal point arrangement for 64APSK encoding modulation in a transmission method using the Gray code or the set division method is proposed, and in particular, a new bit allocation in the transmission method using the set division method is proposed, and the new signal point arrangement is also proposed. In addition, the performance improvement of error correction codes based on bit allocation is disclosed (for example, see Non-Patent Documents 6 to 9).

  More specifically, in the technique of Non-Patent Document 9 as a representative, as the new signal point arrangement of 64APSK, the arrangement number of each signal point on the four concentric circles is optimized from the viewpoint of expanding the Euclidean distance, and the four It is assumed that the amplitude value of each signal point substantially coincides with one of the concentric circles, and the phase value of each signal point is adjusted.

  In the technique of Non-Patent Document 9, as a bit allocation by the set partitioning method using the new signal point arrangement of 64APSK, a predetermined signal power to noise power ratio is changed from a bit allocation optimized based on a predetermined calculation method. It is assumed that bits have been exchanged to satisfy

  Furthermore, in the technique of Non-Patent Document 9, a slot configuration of 6 slots as a concatenated code of LDPC code and BCH code as an error correction code based on the new signal point arrangement of 64APSK and bit allocation by a new set partitioning method. The average coding rate of the entire LDPC code is 4/5, the LDPC coding rate of each slot in the 6 slots is defined, and the parity check matrix initial value table of the LDPC code in the set partitioning method is Optimized.

JP 2014-155195 A

G. Ungerboeck, “Channel coding with multilevel / phase signals”, IEEE Transaction Information Theory, Vol.IT-28, No.1, January 1982, p.55−67 "Satellite digital broadcasting transmission standard ARIB STD-B20 version 3.0", [online], revised on May 31, 2001, ARIB, [searched on November 29, 2016], Internet <URL: http: / /www.arib.or.jp/english/html/overview/doc/2-STD-B20v3_0.pdf> Digital Video Broadcasting (DVB), “Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2)”, [online], Final draft ETSI EN 302 307 V1. 2.1 (2009-04), [Searched on November 29, 2016], Internet <URL: http: //www.etsi.org/deliver/etsi_en/302300_302399/302307/01.02.01_40/en_302307v010201o.pdf> Digital Video Broadcasting (DVB), “Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications; Part 2: DVB-S2 Extensions (DVB-S2X)”, [online], Draft ETSI EN 302 307-2 V1.1.1 (2014-10), [Searched on November 29, 2016], Internet <URL: http://www.etsi.org/deliver/etsi_en/302300_302399/30230702/01.01. 01_20 / en_30230702v010101a.pdf> "Transmission method of advanced broadband satellite digital broadcasting standard ARIB STD-B44 2.1 version", [online], revised on March 25, 2016, ARIB, [searched on November 29, 2016], Internet <URL: http : //www.arib.or.jp/english/html/overview/doc/2-STD-B44v2_1.pdf> Yuki Koizumi, Yoichi Suzuki, Masaaki Kojima, Junichi Saito, Shoji Tanaka, “Examination of 64APSK Coded Modulation (Part 1) -Examination of 64APSK Signal Point Arrangement-”, IEICE, 2016 Society Conference Proceedings, B-5-21, 2016, p291, announced on September 20, 2016 Yuki Koizumi, Yoichi Suzuki, Masaaki Kojima, Junichi Saito, Shoji Tanaka, “Examination of 64APSK Coded Modulation—Examination of Bit Allocation for 64APSK Coded Modulation”, Video Information Media Society, Annual Conference Proceedings, 32C- 1, 2016, announced on September 2, 2016 Yoichi Suzuki, Yuki Koizumi, Masaaki Kojima, Junichi Saito, Shoji Tanaka, “Examination of 64APSK Coded Modulation (Part 2) -Performance Improvement by Optimizing LDPC Coding Rate-”, IEICE, 2016 Society Conference Lecture Proceedings, B-5-22, 2016, p292, published on September 20, 2016 Yuki Koizumi, Yoichi Suzuki, Masaaki Kojima, Hyoichi Daito, Shoji Tanaka, “A study on 64APSK Coded Modulation”, [online], IEICE Tech. Rep., Vol. 116, no. 243, SAT2016- 55, pp. 51-56, published on October 6, 2016, [Searched on November 29, 2016], Internet <URL: http://www.ieice.org/ken/paper/20161013cblh/eng/>

  As described above, the mapping technique at the time of modulation is roughly divided into the Gray code and the set division method. In any case, in order to improve the transmission performance, it is possible to apply a signal point arrangement that increases the transmission path capacity. It is valid.

  For example, it is necessary to improve the information bit rate in order to meet the need for high image quality for ultra-high-definition video such as 4K and 8K. For this purpose, not only the modulation multi-value number is increased, but also the transmission path It is more effective to apply a signal point arrangement that expands the capacity.

  However, as the number of modulation multi-levels increases, a high required C / N is required. Therefore, in increasing the bit rate by multi-level modulation, it is necessary to improve the required C / N, and in particular, 64 APSK coded modulation. Improvement of required C / N is required.

  In particular, digital data is transmitted using 64APSK while satisfying 34.5 MHz, which is a bandwidth that can be used for one satellite repeater in 12 GHz band satellite broadcasting, as the resolution of transmitted video increases. In some cases, a transmission system having a transmission bit rate of 150 Mbps or higher is required, and a technique for improving performance over DVAP-S2X 64APSK is desired.

  On the other hand, Non-Patent Documents 6 to 9 disclose a technique for improving the performance of error correction codes based on a new signal point arrangement and bit allocation as a technique for improving the problems of the Gray code. There is room to plan.

  In view of the above-described problems, an object of the present invention is to provide a transmission device and a reception device that can improve the required C / N over the conventional technique and can transmit digital data using 64APSK.

  The transmission apparatus of the present invention is a transmission apparatus for transmitting digital data, and performs error correction processing including LDPC code on the data to be transmitted, and generates error correction coding means for generating a symbol suitable for a 64APSK modulation scheme And the bit allocation of the set division method from the bit allocation optimized based on the predetermined calculation method to the signal point arrangement in which the transmission path capacity is maximized based on the predetermined calculation method as the signal point arrangement in the 64APSK modulation scheme Mapping means for mapping IQ signals by allocating bits constituting the symbol in accordance with bit allocation in which bit replacement is performed so as to satisfy a predetermined signal power to noise power ratio as allocation, and the mapping means includes 64 APSK Constellation and the bit assignment of each bit constituting the symbol As, characterized in that it is configured to perform each mapping shown in Table 1.

  Further, the receiving apparatus of the present invention receives means for receiving a modulated wave signal based on the 64APSK IQ signal transmitted by the transmitting apparatus of the present invention, and performs orthogonal demodulation processing corresponding to the 64APSK signal point arrangement and bit allocation. It is characterized by providing.

  According to the present invention, when transmitting digital data using 64APSK as compared with the existing technology, a signal point arrangement in which the transmission path capacity is expanded is applied, and bit allocation is performed based on the transmission path capacity. Thus, after signal point division by the set division method, the Euclidean distance can be further increased, and the overall transmission performance can be improved. Also, transmission performance can be improved by assigning bits to signal points for 64APSK encoding modulation by exchanging bits in consideration of LDPC code correction capability.

It is a figure which shows the structural example of the transmitter of one Embodiment in this invention, and a receiver. It is a figure which shows the C / N versus frequency utilization efficiency characteristic in 64APSK of 64APSK and DVB-S2X which concerns on this invention, and 64QAM. It is a figure which shows the bit allocation result from the 1st bit-the 6th bit on the basis of the transmission line capacity of 64APSK which concerns on this invention. It is a figure which shows the C / N versus bit error rate characteristic before the error correction for every 64 APSK bits according to the present invention. It is a figure which shows the bit allocation result from the 1st bit-the 6th bit after the bit replacement of 64APSK which concerns on this invention. It is a figure which shows the C / N versus bit error rate characteristic before the error correction for every bit after the bit substitution of 64APSK which concerns on this invention. (A) thru | or (f) is a figure which shows the division | segmentation process from the 1st bit to the 6th bit after the 64 APSK bit replacement according to the present invention. First bit LDPC coding rate 46/120, second bit LDPC coding rate 80/120, third bit LDPC coding rate 97/120, fourth bit LDPC coding rate 117/120, fifth It is a figure which shows the example of a slot structure in the case of bit LDPC coding rate 116/120, 6th bit LDPC coding rate 120/120 (no LDPC parity), and BCH (65535, 65167) shortened code. It is a figure which shows the C / N vs. bit error rate characteristic which contrasts the Example which concerns on this invention, and a prior art technique. It is a figure which shows bit allocation of DVB-S2X of a prior art.

  Hereinafter, a transmission device and a reception device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a transmission device 10 and a reception device 20 according to an embodiment of the present invention. Note that the actual transmission device 10 provides the receiver with information such as the function of multiplexing the synchronization signal with the modulated wave signal in order to identify the head of the error correction code, the setting of the transmission method employed in ISDB-S, etc. It has a function of multiplexing a transmission multiplex control signal (also referred to as a TMCC signal) for notification to a modulated wave signal. In addition, the actual receiving device 20 detects information such as a synchronization detection function that detects a synchronization signal multiplexed with a modulated wave signal and detects the head of an error correction code, and a transmission method setting from a transmission multiplexing control signal. However, the detailed illustration of the control function for setting the modulation system and coding rate is omitted.

(Device configuration)
[Transmitter]
Referring to FIG. 1, a transmission apparatus 10 according to the present embodiment is a forward error correction transmission apparatus, and includes an error correction encoding unit 11, a mapping unit 12, and an orthogonal modulation unit 13. That is, the functional block configuration of the transmission apparatus 10 is the same as that of the coded modulation transmission apparatus based on the Gray code or the set division method, but the mapping unit 12 is different from the conventional technique.

  The error correction coding unit 11 performs error correction processing composed of a concatenated code having an outer code as a BCH code and an inner code as an LDPC code on the data to be transmitted, forms a symbol, and outputs the symbol to the mapping unit 12.

  The mapping unit 12 uses the signal encoded by the error correction encoding unit 11 as an input symbol sequence, and converts the I-axis and Q-axis amplitude values of signal points corresponding to the symbols to IQ signals (in-phase component I and quadrature phase component Q). (Complex signal made up of) and output to the quadrature modulation unit 13. Here, the 64 APSK signal point arrangement by the mapping unit 12 is based on a predetermined signal power to noise power ratio (C / N = 16 dB in the embodiment) as described later with reference to FIG. 2. Is maximized, and bit allocation is also optimized. As an example of bit allocation based on this signal point arrangement, FIG. 5 shows an example of bit allocation to symbols when the set division method in 64APSK according to the present invention is applied. FIG. 7 shows a 64APSK set partitioning process when the set partitioning method by mapping shown in FIG. 5 is applied. That is, the correspondence between the symbols and signal points used in the mapping according to the present invention is set division assigned in the order shown in FIG. 7A to FIG. Use the law.

  Therefore, the mapping unit 12 functions as a symbol / signal point conversion means for converting an input symbol sequence composed of a plurality of code sequences into a signal point sequence based on the correspondence relationship.

  The quadrature modulation unit 13 performs a roll-off filter process on the IQ signal generated by the mapping unit 12, generates a modulated wave signal subjected to quadrature modulation, and transmits the modulated wave signal to an external transmission path.

[Receiver]
The receiving apparatus 20 of the present embodiment is a forward error correction type receiving apparatus, and includes a demodulating unit 21, a demapping unit 22, and an error correction decoding unit 23. That is, the functional block configuration of the receiving device 20 is the same as that of the coded modulation receiving device using the Gray code or the set division method, but the orthogonal demodulation processing in the demodulating unit 21 and the demapping unit 22 is different from the conventional technique.

  The demodulator 21 receives a 64APSK modulated wave signal obtained by modulating the signal point sequence of the IQ signal from the transmission device 10 via the transmission path, and performs a demodulation process corresponding to the modulation process in the modulator 13 on the transmission side. And output to the demapping unit 22.

  The demapping unit 22 performs a demapping process in the mapping unit 12 on the transmission side on the signal demodulated by the demodulating unit 21 to restore the signal encoded by the error correction encoding unit 11, and an error correction decoding unit To 23.

  The error correction decoding unit 23 performs error correction decoding processing corresponding to the error correction coding unit 11 on the transmission side on the signal before error correction restored by the demapping unit 22, restores the data, and outputs it to the outside To do.

(64 APSK signal point arrangement)
Here, the 64APSK signal point arrangement and bit allocation in the mapping unit 12 will be described in detail. As described above as a problem to be solved, with the increase in resolution of transmitted video in the future, 64APSK while satisfying 34.5 MHz which is a bandwidth that can be used per satellite repeater in 12 GHz band satellite broadcasting. From the viewpoint that a transmission system having a transmission bit rate of 150 Mbps or higher is required when transmitting using the network, a technique for improving performance over DVAP-S2X 64APSK is desired.

  Therefore, in order to improve the performance of the multi-level modulation system, it was decided to study from the design of an appropriate signal point arrangement. A transmission path capacity T (equation (1)), which is a Shannon limit that limits the modulation method, is used as the design standard. The transmission line capacity T is defined by the equation (1) when the transmission symbol x and the reception symbol y are used in the AWGN transmission line. M is the number of signal points, p (y | x) is a transition probability density function determined from the minimum Euclidean distance between C / N and the signal point expressed by Equation (2), and σ 2 is white noise power. The first term of equation (1) is the average information amount of the received symbol y and is determined from the number of signal points M. The second term of Equation (1) indicates the average amount of information in which the received symbol is y when a certain transmission symbol x is transmitted.

  Here, considering that the transmission line capacity T is maximized, when the number of signal points M and C / N are fixed, the value of the second term of Equation (1) may be minimized. At this time, the second term of Equation (1) is a function of the minimum Euclidean distance between signal points, and the second term becomes smaller as the minimum Euclidean distance increases. Therefore, maximizing the transmission line capacity T in Equation (1) is equivalent to increasing the minimum Euclidean distance between signal points. By expanding the minimum Euclidean distance between signal points, it is possible to reduce the possibility that a certain received symbol is erroneously received as another adjacent symbol, leading to an improvement in the error rate after reception.

  As described above, by designing the signal point arrangement that maximizes the transmission line capacity T, the minimum Euclidean distance between the signal points can be increased, which leads to improvement of the transmission performance of the multilevel modulation system. As a specific signal point arrangement design method, the number of signal points arranged on the circumference, the phase of the signal points, and the radius ratio between the circumferences were respectively designed as design parameters so as to maximize the transmission line capacity.

  For the 64 APSK signal point arrangement design based on the transmission line capacity, the signal point arrangement that maximizes the transmission line capacity calculated by Expression (1) was designed with the number of signal points M = 64 and the design C / N = 16 dB. The design C / N is C / N = 16 dB with a performance target of a gap of about 1 dB against the theoretical limit C / N = 14.9 dB of 64APSK (LDPC coding rate 4/5).

  The 64 APSK signal point arrangement shown in Table 1 above indicates an IQ signal standardized with a transmission power of 1. In addition, FIG. 2 shows the C / N versus frequency utilization efficiency (unit of transmission line capacity) characteristics of this design, DVB-S2X, 64QAM.

  By designing the signal point arrangement of 64APSK with reference to the transmission line capacity based on FIG. 2, it is possible to achieve a transmission line capacity of 5.10549 bps / Hz exceeding DVB-S2X at C / N = 16 dB.

(Example of bit allocation in the above signal point arrangement)
In the following, optimization was performed for bit allocation to the 64APSK signal point arrangement. In the multilevel coding modulation to which the set division method as a conventional technique is applied, signal points are divided according to the decoding result of the previous bit based on the set division method, and each bit is decoded. For example, for the decoding of the second bit (a2), the decoding is performed after dividing into signal points of a1 = 0 and a1 = 1 according to the decoding result of the first bit (a1), and the second and subsequent bits are also processed in the same procedure. The signal points are divided and decoded. In this way, each time the signal points are divided, the minimum Euclidean distance between the signal points can be increased, and the BER characteristic of each bit becomes higher as it goes to the upper bit (the first bit is the least significant bit). It is possible to improve and improve the transmission characteristics as a whole.

  In order to apply the set division method in this way, it is necessary to assign bits to each signal point so that the minimum Euclidean distance of the signal points after division is as large as possible. For QAM and other signal points having a grid arrangement, bit allocation that expands the minimum Euclidean distance between geometrically adjacent signal points is possible, but the signal point arrangement is not uniquely determined as in APSK. For a simple modulation scheme, it is difficult to increase the minimum Euclidean distance geometrically.

  Therefore, in the 64APSK mapping according to the present invention, bit allocation to each signal point is performed based on the transmission path capacity T (Equation (1)). As described above, maximizing the transmission line capacity is equivalent to increasing the minimum Euclidean distance. Therefore, by performing bit allocation that maximizes the transmission path capacity after signal point division, when the set division method is applied to 64 APSK, it is possible to increase the minimum Euclidean distance after signal point division.

  Specifically, the transmission path capacity equation (1) is applied as an evaluation function when assigning bits to the 64APSK signal point arrangement based on the set division method, and the transmission path capacity after signal division at C / N = 16 dB. As a result of performing the bit allocation so that becomes the maximum, the result shown in FIG. 3 is obtained. In FIG. 3, the 6 bits assigned to the signal points are defined in order from the left as the first bit (a1), the second bit (a2),..., The sixth bit (a6). It is written in. FIG. 4 shows BER characteristics before error correction for each bit corresponding to the output of the demodulator 21 on the receiving device 20 side.

However, as a 64APSK error correction code based on the set division method, a current standard (ISDB-S3: Non-Patent Document) is used to apply a concatenated code consisting of an LDPC code (inner code) and a BCH code (outer code) for each bit. When the BER before error correction is lower than the 10 ⁻³ order, the LDPC code adopted in 5) becomes difficult to design with the randomness of the code. Further, when a BCH (65535, 65167, t = 23) code is applied as an outer code, the BER before error correction in which pseudo error free (1 × 10 ⁻¹¹ ) can be expected is 1.2 × 10 ⁻⁴ or less. . That is, when the BER before error correction is in the range of 1.0 × 10 ⁻³ to 1.2 × 10 ⁻⁴ , error correction using the LDPC code and BCH code becomes difficult. Here, focusing on C / N = 16 dB in FIG. 4, the BER of the fifth bit is 8.97 × 10 ^−4, which is outside the applicable range of the LDPC code and the BCH code.

  Therefore, by performing bit replacement from the bit allocation of FIG. 3, bit allocation is performed such that the BER of the first bit to the fifth bit is within the LDPC code application range. FIG. 5 shows the bit allocation result at that time, and FIG. 6 shows the BER characteristics before error correction for each bit. Further, FIG. 7 shows the result of division by the set division method up to the first to sixth bits after this bit replacement. In FIG. 7, for the sake of simplicity, a case where a1 = 0, a2 = 0, a3 = 0, a4 = 0, a5 = 0 is shown, and other division results are omitted.

  That is, the mapping unit 12 performs mapping as shown in Table 1 above as bit allocation of each bit constituting a symbol for the 64 APSK signal point arrangement.

Here, from the BER characteristics of FIG. 6, the BER of the sixth bit (a6) at C / N = 16 dB is 2.54 × 10 ⁻⁷ , and error-free can be achieved by using only the BCH outer code. Finally, the present invention adjusts the LDPC coding rate applied to the first bit (a1) to the fifth bit (a5) while satisfying the LDPC average coding rate 4/5 of the entire signal, and reduces white noise. Thus, the LDPC code that minimizes the required C / N (defined as C / N corresponding to BER = 1 × 10 ⁻¹¹ ) was designed.

  At this time, the structure of the LDPC check matrix was the same as ISDB-S3. That is, the error correction encoding unit 11 is configured to include an encoder that performs LDPC encoding of the digital data using a check matrix unique to each encoding rate, and this encoder is a code of 44880 bits. Using a parity check matrix initial value table predetermined for each coding rate as an initial value as an initial value, one element of a submatrix corresponding to the information length according to the coding rate is arranged in a column direction at intervals of 374 columns. LDPC encoding is performed using the check matrix configured as described above.

  As the specifications of the designed LDPC code, the slot configuration satisfying the LDPC average coding rate 4/5 at the bit rate shown in Table 2 was adopted. Note that the initial value table of the parity check matrix for each coding rate in the bit-by-bit LDPC code shown in Table 2 is not directly related to the mapping processing according to the present invention, and thus the description thereof is omitted.

  The BCH code of the outer code is a BCH (65535, 65167) shortened code. However, a BCH (65535, 65343) shortened code may be used. The generator polynomial of the BCH (65535, 65167) shortened code is as disclosed in Patent Document 1. Further, the generator polynomial for the BCH (65535, 65343) shortened code is as disclosed in Non-Patent Document 5.

  The transmission performance (simulation result) in the case of using the transmission apparatus 10 and the reception apparatus 20 of FIG. 1 and the slot configuration according to Table 2 will be described. A slot configuration diagram according to Table 2 is shown in FIG. The transmission model assumes white noise, the BCH outer code is a BCH (65535, 65167, t = 23) code, and the number of decoding iterations of the LDPC code is set to a maximum of 50 times per stage.

FIG. 9 shows C / N vs. BER characteristics by computer simulation under white noise according to Table 2. FIG. 9 also plots the case where the LDPC code is applied to DVAP-S2X 64APSK (coding rate 4/5) and gray coded 64QAM having equivalent frequency utilization efficiency. The computer simulation was performed up to BER = 1 × 10 ⁻¹⁰ order, and extrapolated to BER = 1 × 10 ⁻¹¹ by linear interpolation. From FIG. 9, it can be seen that the required C / N of the technology of the present invention is 15.6 dB, and that it is possible to improve the performance by 0.42 dB from DVB-S2X and 1.07 dB from gray coded 64QAM. In addition, the technique of the present invention can improve the performance by 0.11 dB compared to the technique of Non-Patent Document 9.

  In particular, in the technique of Non-Patent Document 9, as a new signal point arrangement of 64APSK, the number of signal points arranged on four concentric circles is optimized from the viewpoint of expanding the Euclidean distance, and each of the four concentric circles is optimized. It is assumed that the amplitude values of the signal points are substantially matched and the phase value of each signal point is adjusted. On the other hand, in the newer signal point arrangement of 64APSK according to the present invention, from the viewpoint of increasing the Euclidean distance without constraining the amplitude value of each signal point on the five concentric circles with reference to the five concentric circles. It is assumed that the arrangement of each signal point is optimized while the maximum amplitude value is equivalent to the existing 64APSK.

  Further, in the bit allocation by the set division method using the 64APSK further new signal point arrangement according to the present invention, the predetermined signal power vs. noise described above from the bit allocation optimized based on the calculation method based on the equation (1). The bit error rate can be further suppressed by performing bit replacement so as to satisfy the power ratio.

  Further, the error correction code based on the new 64APSK signal constellation and bit allocation by the new set partitioning method according to the present invention, the entire slot configuration of 6 slots as a concatenated code by the LDPC code and the BCH code. The average coding rate of the LDPC code is 4/5, the LDPC coding rate of each slot in the 6 slots is defined as shown in Table 2, and the parity check matrix initial value of the LDPC code in the set partitioning method is defined. The transmission performance can be further improved by optimizing the table.

  Thereby, in the configuration of the transmission device 10 and the reception device 20 according to an embodiment of the present invention, the performance improvement of 0.11 dB is possible even for the technique of Non-Patent Document 9.

  The present invention has been described above with reference to specific embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the technical concept thereof. For example, in the above description, the transmission performance is verified for a specific LDPC coding rate, but it is also effective for other coding rates. Accordingly, the transmission device and the reception device according to the present invention are not limited to the above-described embodiments, but are limited only by the description of the scope of claims.

  According to the present invention, when digital data is transmitted using 64APSK, a signal point arrangement in which the transmission path capacity is expanded is applied, and bit allocation is performed based on the transmission path capacity. After signal point division, the Euclidean distance can be further increased, and the overall transmission performance can be improved, which is useful for applications of digital data transmission apparatuses and reception apparatuses.

DESCRIPTION OF SYMBOLS 10 Transmission apparatus 11 Error correction encoding part 12 Mapping part 13 Orthogonal modulation part 20 Reception apparatus 21 Orthogonal demodulation part 22 Demapping part 23 Error correction decoding part

Claims (2)

A transmission device for transmitting digital data,
Error correction coding means for performing error correction processing including an LDPC code on data to be transmitted and generating a symbol conforming to a 64APSK modulation scheme;
As a signal point arrangement in the 64APSK modulation scheme, the bit allocation of the set division method is changed from the bit allocation optimized based on the predetermined calculation method to the signal point arrangement in which the transmission path capacity is maximized based on the predetermined calculation method. Mapping means for mapping an IQ signal by allocating bits constituting the symbol according to bit allocation in which bit replacement is performed so as to satisfy a predetermined signal power to noise power ratio;
The mapping means includes 64 APSK signal point arrangements and bit assignments for each bit constituting the symbol.
A transmission apparatus configured to perform mapping shown in FIG.   A means for receiving a modulated wave signal based on a 64APSK IQ signal transmitted by the transmitter according to claim 1 and performing orthogonal demodulation processing corresponding to the 64APSK signal point arrangement and bit allocation is provided. Receiver device.