JP2019028169A - Display panel and display device - Google Patents

Abstract

To provide a display device capable of being upsized, to provide a display device with high visibility, to reduce the number of components of a display device, or to provide a large display device with excellent portability.SOLUTION: A display panel comprises a display unit, a first circuit unit which outputs a gradation signal, a second circuit unit which outputs a signal for selecting a plurality of pixels, and a first region transmitting visible light. The first circuit unit and the second circuit unit are respectively provided along a contour of the display unit. The first region is provided in the position facing the first circuit unit and in the position facing the second circuit unit across the display unit. The first circuit unit includes a first transistor, and the second circuit unit includes a second transistor. A first gate insulation layer of the first transistor is formed thinner than a second gate insulation layer of the second transistor. A channel length of the first transistor is set shorter than a channel length of the second transistor.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a display panel and a display device including the display panel.

  Note that one embodiment of the present invention is not limited to the above technical field. Technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, and driving methods thereof , Or a method for producing them, can be mentioned as an example.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, an arithmetic device, a memory device, or the like is one embodiment of a semiconductor device. In addition, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.

  In recent years, an increase in the size of a display device has been demanded. For example, a home television device (also referred to as a television or a television receiver), a digital signage (Digital Signage), a PID (Public Information Display), and the like can be given. In addition, as digital signage, PID, and the like are larger, the amount of information that can be provided can be increased. In particular, when used for advertising, the larger the size, the easier it is to catch the eye, and the advertising effectiveness of the advertisement can be enhanced.

  As a display device, typically, a liquid crystal display device, a light emitting device including a light emitting element such as an organic EL (Electro Luminescence) element or a light emitting diode (LED), an electronic paper that performs display by an electrophoresis method, or the like Is mentioned.

  For example, the basic configuration of the organic EL element is such that a layer containing a light-emitting organic compound is sandwiched between a pair of electrodes. Light emission can be obtained from the light-emitting organic compound by applying a voltage to this element. Since a display device to which such an organic EL element is applied does not require a backlight that is necessary for a liquid crystal display device or the like, a thin, lightweight, high-contrast display device with low power consumption can be realized. For example, Patent Document 1 describes an example of a display device using an organic EL element.

  Patent Document 2 discloses a flexible active matrix light emitting device including a transistor or an organic EL element as a switching element on a film substrate.

JP 2002-324673 A JP 2003-174153 A

  As one of large display devices, there is a multi-display device in which a plurality of display panels are arranged. However, in the conventional multi-display device, since each display panel has a frame portion, there is a problem that if a plurality of display panels are arranged, a grid-like non-display area is formed.

  In addition, since it is necessary to arrange a driving circuit for driving each display panel, a printed circuit board having many wirings, terminals, and driving circuits is arranged on the back side of one display panel. become. Therefore, there are problems that the number of parts of the entire multi-display becomes enormous and the weight becomes extremely heavy.

  An object of one embodiment of the present invention is to provide a display device that can be increased in size. Another object is to provide a display device with high visibility. Another object is to reduce the number of parts of a display device. Another object is to provide a large display device with high portability.

  Another object of one embodiment of the present invention is to provide a novel display panel, a display device, or the like. Another object is to provide a highly reliable display panel, a display device, or the like.

  Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these can be extracted from the description, drawings, claims, and the like.

  One embodiment of the present invention is a display device including a display portion, a first circuit portion, a second circuit portion, and a first region. The display unit has a plurality of pixels. The first circuit unit and the second circuit unit are provided along the outline of the display unit, respectively. The first region includes a portion provided at a position facing the first circuit portion with the display portion interposed therebetween, and a portion provided at a position facing the second circuit portion sandwiching the display portion. The first region has a function of transmitting visible light. The first circuit portion has a function of outputting gradation signals to a plurality of pixels, and the second circuit portion has a function of outputting signals for selecting the plurality of pixels. The first circuit portion includes a first transistor, and the second circuit portion includes a second transistor. The first transistor includes a first semiconductor layer, a first gate electrode, and a first gate insulating layer. The second transistor includes a second semiconductor layer, a second gate electrode, and a second gate insulating layer. The first gate insulating layer is thinner than the second gate insulating layer.

  In the above, it is preferable that the width of the first gate electrode in the channel length direction is smaller than that of the second gate electrode.

  In the above, it is preferable that the first semiconductor layer and the second semiconductor layer each include a metal oxide.

  Another embodiment of the present invention is a display device including a first display panel and a second display panel. Each of the first display panel and the second display panel is the display panel described in any one of the above. The first region of the first display panel has a portion that overlaps with the display portion of the second display panel and transmits light emitted from the display portion of the second display panel.

  In the above, it is preferable that the first circuit portion or the second circuit portion of the second display panel has a portion overlapping with the display portion of the first display panel.

  According to one embodiment of the present invention, a display device that can be increased in size can be provided. Alternatively, a display device with high visibility can be provided. Alternatively, the number of parts of the display device can be reduced. Alternatively, a large display device with high portability can be provided.

  Alternatively, according to one embodiment of the present invention, a novel display panel, a display device, or the like can be provided. Alternatively, a highly reliable display panel, display device, or the like can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description, drawings, claims, and the like.

A configuration example of a display panel. 2 shows a configuration example of a display device. A configuration example of a drive circuit and the like. 2 shows a configuration example of a drive circuit. 2 is a configuration example of a pixel portion. 2 shows a structure example of a transistor. 2 shows a structure example of a transistor. 10A and 10B illustrate an example of a method for manufacturing a transistor. 10A and 10B illustrate an example of a method for manufacturing a transistor. 10A and 10B illustrate an example of a method for manufacturing a transistor. The cross-sectional structural example of a display panel. The cross-sectional structural example of a display panel. FIG. 14 illustrates an example of an electronic device. The figure which shows an example of a vehicle. 2 shows a configuration example of a television device.

  Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

  Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.

  Note that in each drawing described in this specification, the size, the layer thickness, or the region of each component is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale.

  In the present specification and the like, ordinal numbers such as “first” and “second” are used for avoiding confusion between components, and are not limited numerically.

  A transistor is a kind of semiconductor element, and can realize amplification of current and voltage, switching operation for controlling conduction or non-conduction, and the like. The transistor in this specification includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT: Thin Film Transistor).

  In addition, the functions of “source” and “drain” may be switched when transistors having different polarities are employed or when the direction of current changes in circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

  In this specification and the like, either the source or the drain of the transistor may be referred to as a “first electrode”, and the other of the source or the drain may be referred to as a “second electrode”. The gate is also referred to as “gate” or “gate electrode”.

  In addition, in this specification and the like, “electrically connected” includes a case of being connected via “thing having some electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. For example, “something having an electric action” includes electrodes, wirings, switching elements such as transistors, resistance elements, coils, capacitive elements, and other elements having various functions.

  Note that in this specification and the like, “the top surface shape is approximately the same” means that at least a part of the contour overlaps between the stacked layers. For example, the case where the upper layer and the lower layer are processed by the same mask pattern or a part thereof by the same mask pattern is included. However, strictly speaking, the contours do not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer.

  In the following, expressions indicating the direction such as “up” and “down” are basically used in combination with the direction of the drawing. However, for the purpose of facilitating the description and the like, the direction indicated by “upper” or “lower” in the specification may not match the drawing. As an example, when explaining the stacking order (or forming order) of a laminated body or the like, the surface (formation surface, support surface, adhesive surface, flat surface, etc.) on the side where the laminated body is provided in the drawing Even if it is positioned above the laminated body, the direction may be expressed as “down”, the opposite direction may be expressed as “up”, and the like.

  Note that in this specification, an EL layer refers to a layer including at least a light-emitting substance (also referred to as a light-emitting layer) or a stacked body including a light-emitting layer, which is provided between a pair of electrodes of a light-emitting element.

  In this specification and the like, a display panel which is one embodiment of a display device has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is one mode of the output device.

  Further, in this specification and the like, a display panel substrate, for example, a connector such as a FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package) is attached, or the substrate is integrated with a COG (Chip On Glass) method or the like. In some cases, is mounted a display panel module, a display module, or simply a display panel.

  In this specification and the like, the touch sensor has a function of detecting that a detection target such as a finger or a stylus touches, presses, or approaches. Moreover, you may have the function to detect the positional information. Therefore, the touch sensor is an aspect of the input device. For example, the touch sensor can be configured to have one or more sensor elements.

  In this specification and the like, a substrate having a touch sensor may be referred to as a touch sensor panel or simply a touch sensor. In addition, in this specification and the like, a touch sensor panel substrate, for example, a connector such as an FPC or TCP attached, or a substrate in which an IC is mounted by a COG method, a touch sensor panel module, a touch sensor It may be called a module, a sensor module, or simply a touch sensor.

  Note that in this specification and the like, a touch panel which is one embodiment of a display device has a function of displaying (outputting) an image or the like on a display surface, and a detection target such as a finger or a stylus touches, presses, or approaches the display surface. And a function as a touch sensor for detecting the above. Accordingly, the touch panel is an embodiment of an input / output device.

  The touch panel can also be referred to as, for example, a display panel with a touch sensor (or display device) or a display panel with a touch sensor function (or display device).

  The touch panel can be configured to include a display panel and a touch sensor panel. Alternatively, the display panel may have a function as a touch sensor inside or on the surface.

  In this specification and the like, a touch panel substrate having a connector such as an FPC or TCP attached, or a substrate having an IC mounted on the substrate by a COG method, a touch panel module, a display module, or simply a touch panel And so on.

(Embodiment 1)
In this embodiment, a display panel and a display device of one embodiment of the present invention will be described.

  A display panel of one embodiment of the present invention includes a display portion including a plurality of pixels, and a first driver circuit and a second driver circuit which are arranged along the outline of the display portion. The display panel has a region that transmits visible light along the outline of the display unit.

  As a more specific example, for example, the first drive circuit is arranged along a part of the outline of the display unit, and the second drive circuit is arranged along the other part. In addition, a region that transmits visible light is provided along the outline of the display portion located on the opposite side of the display portion with respect to the first drive circuit and the second drive circuit.

  By combining two or more such display panels as described below, a display device capable of performing seamless display can be realized.

  Of the two display panels, a display panel (hereinafter referred to as the first display panel) disposed on the display surface side and a display panel (hereinafter referred to as the first display panel) disposed on the side opposite to the display surface side. The two display panels are arranged so as to overlap with the display unit of 2). Thereby, the light emitted from the display unit of the second display panel is emitted to the outside through the region of the first display panel that transmits visible light. Further, the positions of the two display panels are adjusted so that the two display units are seamlessly continuous when viewed from the display surface side. Thereby, a seamless image can be displayed across the two display panels.

  A first driver circuit included in one display panel has a function of sampling an input video signal and outputting the sampled video signal to each pixel of the display portion. The second driver circuit has a function of generating a selection signal for selecting each pixel. The first driver circuit functions as, for example, a source line driver circuit (also referred to as a signal line driver circuit or a source driver), and the second driver circuit includes, for example, a gate line driver circuit (a scanning line driver circuit or a gate driver). Etc.).

  Each of the first driver circuit, the second driver circuit, and the semiconductor element included in the display portion is preferably formed over one substrate.

  Here, the first drive circuit and the second drive circuit are required to operate at a high drive frequency in accordance with the frame frequency of the image to be displayed. In particular, the second driving circuit is required to have a higher driving frequency than the first driving circuit. Therefore, some of the transistors applied to the second driver circuit are not required to have high withstand voltage performance, but may be required to have a large current flow capability. On the other hand, some of the transistors provided in the pixels of the display portion may be required to have sufficient withstand voltage performance for driving the display element.

  Thus, according to one embodiment of the present invention, a transistor with high withstand voltage is applied to one of transistors provided in a pixel, and one of transistors provided in the first driver circuit has low withstand voltage but higher drive frequency. Apply transistor.

  As a more specific structure, a transistor whose gate insulating layer is thinner than that of one transistor applied to the display portion is applied to one transistor applied to the first driver circuit. In this manner, by forming two types of transistors separately, the first driver circuit that functions as a source driver can be formed over a substrate provided with a display portion.

  Further, it is preferable that a transistor having a channel length shorter than that of the one transistor applied to the display portion be applied to the one transistor applied to the first driver circuit. For example, the channel length of the transistor included in the second driver circuit is less than 1.5 μm, preferably 1.2 μm or less, more preferably 1.0 μm or less, further preferably 0.9 μm or less, and further preferably 0.8 μm. Hereinafter, it is more preferably 0.6 μm or less, and preferably 0.1 μm or more.

  On the other hand, each transistor provided in the display portion preferably has a longer channel length than a transistor having the shortest channel length among the transistors included in the first driver circuit. For example, the channel length of one transistor provided in the display portion is 1 μm or more, preferably 1.2 μm or more, more preferably 1.4 μm or more, and 20 μm or less, preferably 15 μm or less, more preferably 10 μm or less. It is preferable.

  In each transistor applied to the first driver circuit, the second driver circuit, and the display portion, a metal oxide is preferably used for a semiconductor in which a channel is formed. As a result, for example, a first driver circuit that functions as a source driver that is difficult to realize in a display panel using amorphous silicon can be mounted on the display panel. Further, compared to the case where polycrystalline silicon or the like is applied, variation in characteristics is small and an increase in area is easy, so that a display panel can be manufactured with low cost and high yield.

  Note that in this specification and the like, the channel length direction of a transistor refers to one of directions parallel to a straight line connecting the source and the drain with the shortest distance. That is, the channel length direction corresponds to the direction of current flowing through the semiconductor layer when the transistor is on. The channel width direction is a direction orthogonal to the channel length direction. Note that depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be determined as one.

  In this specification and the like, the channel length of a transistor refers to the length in a channel length direction of a region where a semiconductor layer and a gate electrode overlap in a top view or a cross-sectional view of the transistor, for example. The channel width of the transistor refers to the length of the region in the channel width direction.

  Note that depending on the structure and shape of the transistor, the channel length and the channel width may not be determined as one value. Therefore, in this specification and the like, the channel length and the channel width can be the maximum value, the minimum value, or the average value, or any value between the maximum value and the minimum value. Typically, the channel length and the channel width are the minimum values.

  Further, depending on the structure of the transistor, the transistor may include a pair of gate electrodes (a first gate electrode and a second gate electrode) that sandwich the semiconductor layer. At this time, two channel lengths and channel widths of the transistor can be defined corresponding to each gate electrode. Therefore, in the present specification and the like, when simply referred to as a channel length, one of the longer or shorter of the two channel lengths, both, or an average value thereof is indicated. Similarly, in the present specification and the like, when simply referred to as a channel width, it refers to either the longer or the shorter of the two channel widths, both, or an average value thereof.

  Hereinafter, more specific examples will be described with reference to the drawings.

[Configuration example]
[Display panel configuration example]
FIG. 1 is a schematic top view of a display panel 10 exemplified below as viewed from the display surface side.

  The display panel 10 includes a display unit 11, a first drive circuit 12, a second drive circuit 13, a region 14 that transmits visible light, a terminal unit 15, and the like. In FIG. 1, the display panel 10 has two terminal portions 15, and an example in which an FPC 21 is connected to each terminal portion 15 is shown.

  Here, even if the display panel 10 is a single unit, an image can be displayed on the display unit 11.

  A plurality of pixels are arranged in a matrix on the display unit 11. The pixel includes at least one display element and one transistor. As the display element, an organic EL element, a liquid crystal element, or the like can be typically used.

  The first drive circuit 12 includes a circuit that functions as a source driver. The first driver circuit 12 has a function of generating a gradation signal based on the video signal input from the FPC 21 and supplying the gradation signal to the pixels included in the display portion 11.

  The second drive circuit 13 includes a circuit that functions as a gate driver. The second drive circuit 13 has a function of generating a selection signal based on a signal input from the FPC 21 and supplying the selection signal to the pixels included in the display unit 11.

  The region 14 is a region that transmits visible light. A material that transmits visible light can be applied to the member provided in the region 14. In addition, a light-shielding material processed so as to be invisible (for example, a width of 5 μm or less) can be applied.

[Configuration example of display device]
2A and 2B show a configuration example of a display device 20 having four display panels (display panel 10a, display panel 10b, display panel 10c, and display panel 10d). 2A is a schematic top view when the display device 20 is viewed from the display surface side, and FIG. 2B is a view when the display device is viewed from the side opposite to the display surface (also referred to as the back surface side). FIG.

  In the following description, when there is no particular description, each display panel and components of the display panel will be described separately with reference numerals a to d. In addition, when explaining matters common to each of these display panels and components of the display panel, these symbols may not be attached.

  2A and 2B, a display panel 10a, a display panel 10b, a display panel 10c, and a display panel 10d are stacked in that order from the back side. The display panel 10a is located on the back side, and the display panel 10d is located on the most display side.

  Here, a part of the region 14b of the display panel 10b is provided so as to overlap with a part of the display unit 11a. In a portion of the display unit 11a that overlaps the region 14b, light from the display element passes through the region 14b and is emitted to the display surface side.

  Similarly, a part of the region 14c included in the display panel 10c is provided so as to overlap with a part of the display unit 11a. Further, a part of the area 14d of the display panel 10d is provided so as to overlap with a part of the display part 11a, the other part is provided so as to overlap with a part of the display part 11b, and the other part is provided as a display part. 11c is provided so as to overlap with a part of 11c.

  That is, the display area 25 of the display device 20 includes the display unit 11a, the display unit 11b, the display unit 11c, and the display unit 11d. Thereby, a display unit having an area approximately four times that of one display panel 10 can be realized.

  As shown in FIG. 2B, the FPC 21a connected to the display panel 10a and the FPC 21b connected to the display panel 10b are provided so as to overlap with the display panel 10c or the display panel 10d, respectively.

  Here, since each display panel 10 is provided with the first drive circuit 12 and the second drive circuit 13, the number of signals supplied to each display panel 10 can be reduced. Therefore, since the number of FPCs 21 connected to one display panel 10 can be reduced, the number of parts can be reduced. Further, as shown in FIG. 2B, the lengths of the FPCs 21 connected to the display panels 10 are made different, and the ends of the FPCs 21 are gathered on one side of the display device 20 so that signals or the like are sent to the display device 20. The driving circuit for supplying the power can be concentrated in one place. Thereby, the structure of the back side of the display apparatus 20 can be simplified (clean).

  FIG. 2C shows a schematic cross-sectional view when the display device 20 is cut along the alternate long and short dash line XY in FIG.

  A portion of the display panel 10a that overlaps the display panel 10c is curved in the back surface direction, and the FPC 21a is connected to the terminal portion 15a in the portion. At this time, the first drive circuit 12a and the terminal unit 15a of the display panel 10a are arranged so as to overlap the display unit 11c of the display panel 10c. Thereby, an image with high display quality can be displayed in the display area 25 of the display device 20 without a seam.

[Configuration Example of First Driving Circuit]
Below, the structural example of the 1st drive circuit 12 which the display panel 10 has is demonstrated.

  FIG. 3 shows a block diagram of the display panel 10. FIG. 3 shows the display unit 11, the first drive circuit 12, and the second drive circuit 13.

  The display unit 11 includes a plurality of pixels PIX arranged in a matrix. The display unit 11 is provided with a plurality of source lines SL connected to the first drive circuit 12 and a plurality of gate lines GL connected to the second drive circuit 13.

  The first drive circuit 12 includes a shift register circuit 31, a latch circuit unit 41, a level shifter circuit unit 42, a DA conversion unit 43, an analog buffer circuit unit 44, and the like.

  The latch circuit unit 41 includes a plurality of latch circuits 32 and a plurality of latch circuits 33. The level shifter circuit unit 42 includes a plurality of level shifter circuits 34. The DA converter 43 includes a plurality of DAC circuits 35. The analog buffer circuit unit 44 includes a plurality of analog buffer circuits 36.

  A clock signal CLK and a start pulse signal SP are input to the shift register circuit 31. The shift register circuit 31 generates a timing signal for sequentially shifting the pulses in accordance with the clock signal CLK and the start pulse signal SP, and outputs the timing signal to each latch circuit 32 of the latch circuit unit 41.

The video signal S ₀ and the latch signal LAT are input to the latch circuit unit 41.

When a timing signal is input to the latch circuit 32, the video signal S ₀ is sampled according to the pulse of the timing signal and written to each latch circuit 32 in order. At this time, the period until the writing of the video signals S ₀ to the latch circuits 32 is completed is may be referred to as a line period.

  When one line period ends, the video signals held in the latch circuits 32 are simultaneously written and held in the latch circuits 33 in accordance with the pulse of the latch signal LAT input to the latch circuits 33. The latch circuit 32 that has finished sending the video signal to the latch circuit 33 sequentially writes the next video signal in accordance with the timing signal from the shift register circuit 31 again. During the second line period, the video signal written and held in the latch circuit 33 is output to each level shifter circuit 34 of the level shifter circuit unit 42.

  The video signal input to each level shifter circuit 34 of the level shifter circuit unit 42 is sent to each DAC circuit 35 in the DA converter 43 after the amplitude of the voltage of the signal is increased by the level shifter circuit 34. The video signals input to the group of DAC circuits 35 are converted into analog signals and output to the analog buffer circuit unit 44 as a single analog signal. The video signal input to the analog buffer circuit unit 44 is output to each source line SL via each analog buffer circuit 36.

  On the other hand, the second drive circuit 13 sequentially selects the gate lines GL. The video signal input to the display unit 11 from the first drive circuit 12 via the signal line SL is input to each pixel PIX connected to the gate line GL selected by the second drive circuit 13.

  Instead of the shift register circuit 31, another circuit that can output a signal in which pulses are sequentially shifted may be used.

  The transistors provided in the first drive circuit 12 and the second drive circuit 13 do not require high withstand voltage performance as compared with the transistors included in the pixel PIX. For this reason, the transistors used in the first driver circuit 12 and the second driver circuit 13 can be miniaturized as compared with the transistor used in the pixel PIX, and a transistor having a thin gate insulating layer can be used for high speed. Operation becomes possible, and an image can be displayed at a higher frame frequency.

[Modification of First Driving Circuit]
The first driving circuit 12 illustrated in FIG. 3 is configured to convert a digital signal into an analog signal and output the analog signal to the display unit 11. However, by using the analog signal as an input signal, the second driving circuit 12 is used. The configuration can be further simplified.

  The first driver circuit 12 a illustrated in FIG. 4A includes a shift register circuit 31, a latch circuit unit 41, and a source follower circuit unit 45. The source follower circuit unit 45 includes a plurality of source follower circuits 37.

The latch circuit 32 samples the analog video signal S ₀ as analog data in accordance with the timing signal from the shift register circuit 31. Each latch circuit 32 outputs the video signal held in each latch circuit 33 all at once according to the latch signal LAT.

  The video signal held in the latch circuit 33 is output to one source line SL via the source follower circuit 37. Note that the analog buffer circuit may be used in place of the source follower circuit 37.

  The first driver circuit 12 b illustrated in FIG. 4B includes a shift register circuit 31 and a demultiplexer circuit 46.

The demultiplexer circuit 46 has a plurality of sampling circuits 38. Each sampling circuit 38 receives a plurality of analog video signals S ₀ from a plurality of wirings, and simultaneously outputs video signals to a plurality of source lines SL in accordance with a timing signal input from the shift register circuit 31. The shift register circuit 31 outputs a timing signal so as to sequentially select a plurality of sampling circuits 38.

For example, when the number of source lines SL connected to the display unit 11 is 2160 and the number of lines to which the video signal S ₀ is supplied is 54, by providing 40 sampling circuits 38 in the demultiplexer circuit 46, One line period is divided into 40, and video signals can be simultaneously output to 54 source lines SL within each period.

  The above is the description of the first drive circuit unit.

[Example of display configuration]
The display unit 11 can have a configuration in which at least one display element and a plurality of pixels PIX each including one transistor are arranged in a matrix.

  FIG. 5 shows an example of a circuit diagram of the display unit 11 when a light emitting element is applied as the display element. 5 is connected to m (m is an integer of 2 or more) gate lines GL and n (n is an integer of 2 or more) source lines SL.

  The pixel PIX included in the display unit 11 includes a transistor 51, a transistor 52, a capacitor 53, and a light emitting element 54. The pixel PIX is connected to a source line SL, a gate line GL, and a wiring VL1 and a wiring VL2 to which a power supply potential is supplied.

  Here, as the transistor 51 and the transistor 52 illustrated in FIGS. 5A and 5B, a transistor to which an oxide semiconductor (a metal oxide having semiconductor characteristics) is applied is preferably used.

  The transistor 51 has a gate connected to the gate line GL, one of a source and a drain connected to the source line SL, and the other connected to one electrode of the capacitor 53 and the gate of the transistor 52. In the transistor 52, one of a source and a drain is connected to one electrode of the light-emitting element 54, and the other is connected to the wiring VL1. The capacitor 53 has the other electrode connected to the wiring VL1. The other electrode of the light emitting element 54 is connected to the wiring VL2.

  The pixel PIX is selected by a signal supplied from the gate line GL. Further, by controlling the current flowing to the light-emitting element 54 by the potential written from the source line SL to the node to which the gate of the transistor 52 is connected through the transistor 51, the light emission luminance of the light-emitting element 54 can be controlled.

  As the light-emitting element 54, an organic electroluminescent element (also referred to as an organic EL element) or the like can be typically used. Note that the light-emitting element 54 is not limited thereto, and an inorganic EL element containing an inorganic material, a light-emitting diode, or the like may be used.

  The above is the description of the configuration example of the display portion.

[Example of transistor structure]
A transistor that can be used for the display device of one embodiment of the present invention is described below. Here, two types of transistors having different gate insulating layer thicknesses and channel lengths are described.

  In the following description, components common to the two transistors are denoted by the same reference numerals, and redundant description may be omitted.

  The transistor of one embodiment of the present invention is a transistor including a semiconductor layer in which a channel is formed, a gate insulating layer, and a gate electrode over a formation surface. The semiconductor layer preferably includes a metal oxide exhibiting semiconductor characteristics (hereinafter also referred to as an oxide semiconductor).

  Here, the transistor is preferably a so-called top gate transistor in which a gate electrode is provided over a semiconductor layer with a gate insulating layer interposed therebetween. At this time, a structure in which the second gate electrode is provided on the surface to be formed side of the semiconductor layer with the second gate insulating layer interposed therebetween may be employed.

  It is preferable that the upper surface shape of the gate electrode and the gate insulating layer are approximately the same. In other words, the gate electrode and the gate insulating layer are preferably processed so that the side surfaces are continuous. For example, an insulating film to be a gate insulating layer and a conductive film to be a gate electrode can be stacked and then processed successively using the same etching mask. Alternatively, the gate insulating layer may be formed by processing the insulating film using the previously processed gate electrode as a hard mask.

  Here, when a region overlapping with the gate electrode and the gate insulating layer of the semiconductor layer is a first region and a region not overlapping with the second region is a second region, the first region functions as a channel formation region, The region 2 functions as a source region or a drain region. At this time, it is desired that the second region has a lower resistance than the first region.

  Hereinafter, more specific examples will be described with reference to the drawings.

[Configuration example 1]
6A1 is a top view of the transistor 100, FIG. 6B1 corresponds to a cross-sectional view of a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 6A1, and FIG. FIG. 6A corresponds to a cross-sectional view of a cut surface along a dashed-dotted line B1-B2 illustrated in FIG.

  6A2 is a top view of the transistor 100A, and FIG. 6B2 corresponds to a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 6A2. FIG. Corresponds to a cross-sectional view of a cut surface along a dashed-dotted line B3-B4 in FIG.

  Note that in FIGS. 6A1 and 6A2, some of the components (a gate insulating layer and the like) of the transistor 100 and the transistor 100A are omitted. The alternate long and short dash lines A1-A2 direction and A3-A4 direction may be referred to as a channel length direction, and the alternate long and short dash lines B1-B2 direction and B3-B4 direction may be referred to as a channel width direction.

  The transistor 100 and the transistor 100A are transistors that can be formed over the same substrate 102. The transistor 100 and the transistor 100A have substantially the same structure except that the channel length and the channel width are different and the thickness of the gate insulating layer is different.

  First, the transistor 100 is described.

  The transistor 100 includes an insulating layer 104, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, a metal oxide layer 117, an insulating layer 118, and the like. The semiconductor layer 108 is provided over the insulating layer 104. The insulating layer 110, the metal oxide layer 114, and the conductive layer 112 are stacked over the semiconductor layer 108 in this order. The metal oxide layer 117 is provided to cover the top surface and side surfaces of the insulating layer 104 and the semiconductor layer 108, the side surface of the insulating layer 110, the side surface of the metal oxide layer 114, and the top surface and side surfaces of the conductive layer 112. The insulating layer 118 is provided so as to cover the metal oxide layer 117.

  Part of the conductive layer 112 functions as a gate electrode. A part of the insulating layer 110 functions as a gate insulating layer. The transistor 100 is a so-called top gate transistor in which a gate electrode is provided over the semiconductor layer 108.

  The semiconductor layer 108 preferably contains a metal oxide. The semiconductor layer 108 includes a region 108i that is in contact with the insulating layer 110 and a pair of regions 108n that sandwich the region 108i.

  A region 108 i of the semiconductor layer 108 that overlaps with the conductive layer 112 functions as a channel formation region of the transistor 100. On the other hand, the pair of regions 108 n provided with the region 108 i interposed therebetween functions as a source region or a drain region of the transistor 100.

  The region 108n is a part of the semiconductor layer 108 and has a lower resistance than the region 108i that is a channel formation region. The region 108n is a region having a higher carrier density than the region 108i, a region having a high oxygen defect density, a region having a high nitrogen concentration, a region that is n-type, or a region having a high hydrogen concentration.

  Further, the upper surface shape of the conductive layer 112, the metal oxide layer 114, and the insulating layer 110 is substantially the same.

  Note that in this specification and the like, “the top surface shape is approximately the same” means that at least a part of the contour overlaps between the stacked layers. For example, the case where the upper layer and the lower layer are processed by the same mask pattern or a part thereof by the same mask pattern is included. However, strictly speaking, the contours do not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer.

  Here, as illustrated in FIGS. 6A1 and 6B1, the channel length L1 in the transistor 100 is the width of the conductive layer 112 in the channel length direction. Further, as illustrated in FIGS. 6A1 and 6C1, the channel width W1 in the transistor 100 is a width in a channel width direction in a portion overlapping with the conductive layer 112 of the semiconductor layer 108.

  In addition, as illustrated in FIGS. 6A1 and 6B1, the transistor 100 may include a conductive layer 120a and a conductive layer 120b over the insulating layer 118. The conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to the region 108n through the opening 141a or the opening 141b provided in the metal oxide layer 117 and the insulating layer 118, respectively.

  The insulating layer 110 functioning as a gate insulating layer preferably has a function of releasing oxygen by heating. Accordingly, oxygen can be supplied into the semiconductor layer 108 by heat treatment after the formation of the insulating layer 110. Accordingly, oxygen vacancies that can be formed in the semiconductor layer 108 can be filled; thus, a highly reliable semiconductor device can be provided.

  The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film that prevents oxygen released from the insulating layer 110 from diffusing to the conductive layer 112 side. For the metal oxide layer 114, for example, a material that transmits at least less oxygen than the insulating layer 110 can be used.

  In this structure, since the metal oxide layer 114 having a high barrier property is provided between the conductive layer 112 and the insulating layer 110, a metal that easily absorbs oxygen such as aluminum or copper is used for the conductive layer 112. Even in this case, oxygen can be prevented from diffusing from the insulating layer 110 to the conductive layer 112. Further, even when the conductive layer 112 contains hydrogen, supply of hydrogen from the conductive layer 112 to the semiconductor layer 108 through the insulating layer 110 is suppressed. As a result, the carrier density of the region 108 i that is a channel formation region of the semiconductor layer 108 can be reduced.

  As the metal oxide layer 114, an insulating material or a conductive material can be used. In the case where the metal oxide layer 114 has an insulating property, it functions as part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductivity, it functions as a part of the gate electrode.

  In particular, as the metal oxide layer 114, an insulating material having a dielectric constant higher than that of silicon oxide is preferably used. In particular, an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like is preferably used.

Alternatively, a metal oxide film containing no nitrogen as a main component, such as an aluminum oxide film or a hafnium oxide film, can be used between the semiconductor layer 108 and the conductive layer 112 functioning as a gate electrode. Therefore, the metal oxide layer 114 can form a level in the film of nitrogen oxide (NO _x , x is larger than 0 and 2 or less, preferably 1 or more and 2 or less, typically NO ₂ or NO). It can be set as the structure with very little content. Thereby, a transistor having excellent electrical characteristics and reliability can be realized.

  Aluminum oxide films, hafnium oxide films, hafnium aluminate films, etc. have sufficiently high barrier properties even when they are thin (for example, about 5 nm thick), so they can be formed thin and improve productivity. Can be made. For example, the thickness of the metal oxide layer 114 can be 1 nm to 50 nm, preferably 3 nm to 30 nm. Furthermore, an aluminum oxide film, a hafnium oxide film, and a hafnium aluminate film have a feature that the dielectric constant is higher than that of a silicon oxide film or the like. As described above, since an insulating film having a high dielectric constant can be formed thin as the metal oxide layer 114, the strength of the gate electric field applied to the semiconductor layer 108 can be increased as compared with the case where a silicon oxide film or the like is used. As a result, the drive voltage can be lowered and the power consumption can be reduced.

  The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an aluminum oxide film is formed using a sputtering apparatus, oxygen can be preferably added to the semiconductor layer 108 by being formed in an atmosphere containing oxygen gas. In addition, when an aluminum oxide film is formed using a sputtering apparatus, the film density can be increased, which is preferable.

  In the case where a conductive material is used for the metal oxide layer 114, an oxide conductive material such as indium oxide or indium tin oxide can be used. Alternatively, a metal oxide that can be used for the semiconductor layer 108 may be used. In particular, a material containing the same element as the semiconductor layer 108 is preferably used. At this time, for example, it is preferable to form by a sputtering method using the same metal oxide target as the semiconductor layer 108 because a film formation apparatus can be shared.

  In addition, it is preferable that the metal oxide layer 114 hardly diffuses water or hydrogen. Thus, even when the conductive layer 112 uses a material that easily diffuses water or hydrogen, it is possible to prevent water and hydrogen from diffusing into the insulating layer 110 and the semiconductor layer 108. In particular, an aluminum oxide film or a hafnium oxide film is preferable because of its high barrier property against water and hydrogen.

  The metal oxide layer 117 is preferably formed using a material that does not easily transmit oxygen. Thus, oxygen can be prevented from being released from the semiconductor layer 108, the insulating layer 110, and the like due to heat applied during the process and diffused to the insulating layer 118 side. Therefore, an increase in carrier density in the region 108i functioning as a channel formation region can be prevented, and a highly reliable transistor can be realized.

  As the metal oxide layer 117, a film similar to the metal oxide layer 114 can be used. By providing the metal oxide layer 117 and the metal oxide layer 114, the carrier density of the region 108i functioning as a channel formation region of the semiconductor layer 108 can be more effectively reduced.

  Here, the semiconductor layer 108 and oxygen vacancies that can be formed in the semiconductor layer 108 are described.

  Oxygen deficiency formed in the semiconductor layer 108 is a problem because it affects transistor characteristics. For example, when an oxygen vacancy is formed in the semiconductor layer 108, hydrogen is bonded to the oxygen vacancy and can serve as a carrier supply source. When a carrier supply source is generated in the semiconductor layer 108, a change in electrical characteristics of the transistor 100, typically, a threshold voltage shift occurs. Therefore, it is preferable that the semiconductor layer 108 has fewer oxygen vacancies.

  Therefore, in one embodiment of the present invention, the insulating film in the vicinity of the semiconductor layer 108, specifically, the insulating layer 110 formed over the semiconductor layer 108 includes oxygen that can be released by heating. By transferring oxygen from the insulating layer 110 to the semiconductor layer 108, oxygen vacancies in the semiconductor layer 108 can be reduced.

  Note that the insulating layer 104 located below the semiconductor layer 108 may contain oxygen that can be released by heating. At this time, oxygen vacancies in the semiconductor layer 108 can be further reduced by transferring oxygen also from the insulating layer 104 to the semiconductor layer 108.

  The semiconductor layer 108 preferably contains a metal oxide. For example, the semiconductor layer 108 includes In and M (M is gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, One or more selected from hafnium, tantalum, tungsten, or magnesium) and Zn are preferable. In particular, M is preferably Al, Ga, Y, or Sn.

  In particular, the semiconductor layer 108 is preferably formed using an oxide containing In, Ga, and Zn.

  The semiconductor layer 108 preferably has a region where the atomic ratio of In is larger than the atomic ratio of M. As the In atomic ratio increases, the field-effect mobility of the transistor can be improved.

  Here, in the case of a metal oxide containing In, Ga, and Zn, since the bonding force between In and oxygen is weaker than the bonding force between Ga and oxygen, when the atomic ratio of In is large, the metal oxide film Oxygen vacancies are easily formed inside. Further, even when the metal element represented by M is used instead of Ga, there is a similar tendency. When many oxygen vacancies exist in the metal oxide film, the electrical characteristics and reliability of the transistor are deteriorated.

  However, in one embodiment of the present invention, a very large amount of oxygen can be supplied into the semiconductor layer 108 containing a metal oxide; thus, a metal oxide material having a large atomic ratio of In can be used. Thus, a transistor having extremely high field effect mobility, stable electrical characteristics, and high reliability can be realized.

  For example, a metal oxide in which the atomic ratio of In is 1.5 times or more, or 2 times or more, or 3 times or more, or 3.5 times or more, or 4 times or more of the atomic ratio of M Can be preferably used.

  In particular, the ratio of the number of In, M, and Zn atoms in the semiconductor layer 108 is preferably In: M: Zn = 5: 1: 6 or the vicinity thereof. Here, in the vicinity, when In is 5, M is 0.5 or more and 1.5 or less, and Zn is 5 or more and 7 or less.

  Note that the semiconductor layer 108 is not limited to the above composition. For example, the ratio of the number of In, M, and Zn atoms in the semiconductor layer 108 is preferably In: M: Zn = 4: 2: 3 or the vicinity thereof.

  Further, as the composition of the semiconductor layer 108, the ratio of the number of atoms of In, M, and Zn in the semiconductor layer 108 may be approximately equal. That is, the ratio of the number of atoms of In, M, and Zn may include In: M: Zn = 1: 1: 1 or a material in the vicinity thereof.

When the semiconductor layer 108 has a region where the atomic ratio of In is larger than the atomic ratio of M, the field-effect mobility of the transistor 100 can be increased. Specifically, the field effect mobility of the transistor 100 exceeds 10 cm ² / V _s , and more preferably, the field effect mobility of the transistor 100 can exceed 30 cm ² / V _s .

  For example, a display device with a narrow frame width (also referred to as a narrow frame) can be provided by using the above transistor with high field-effect mobility for a gate driver that generates a gate signal. In addition, a transistor having high field effect mobility may be a source driver that supplies a signal from a signal line included in a display device (in particular, a demultiplexer connected to an output terminal of a shift register included in the source driver), or When used in part, a display device with a small number of wirings connected to the display device can be provided.

  Note that even when the semiconductor layer 108 has a region where the atomic ratio of In is larger than the atomic ratio of M, the field-effect mobility may be low when the semiconductor layer 108 has high crystallinity.

  The crystallinity of the semiconductor layer 108 can be analyzed by, for example, analyzing using X-ray diffraction (XRD: X-Ray Diffraction), or analyzing using a transmission electron microscope (TEM: Transmission Electron Microscope). .

  Here, impurities such as hydrogen or moisture mixed in the semiconductor layer 108 are problematic because they affect the transistor characteristics. Therefore, it is preferable that the semiconductor layer 108 have fewer impurities such as hydrogen or moisture.

As the semiconductor layer 108, a metal oxide film with a low impurity concentration and a low density of defect states is preferably used because a transistor having excellent electrical characteristics can be manufactured. Here, low impurity concentration and low defect level density (low oxygen deficiency) are referred to as high purity intrinsic or substantially high purity intrinsic. A metal oxide film that is highly purified intrinsic or substantially highly purified intrinsic has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor in which a channel region is formed in the metal oxide film rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. In addition, since a highly purified intrinsic or substantially highly purified intrinsic metal oxide film has a low defect level density, the trap level density may also be low. In addition, a highly purified intrinsic or substantially highly purified intrinsic metal oxide film has an extremely small off-state current, a channel width of 1 × 10 ⁶ μm, and a channel length of 10 μm. When the voltage between the electrodes (drain voltage) is in the range of 1V to 10V, the off-state current can be less than the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 ⁻¹³ A or less.

  Further, the semiconductor layer 108 may have a stacked structure of two or more layers.

  For example, the semiconductor layer 108 in which two or more metal oxide films having different compositions are stacked can be used.

  For example, when an In—Ga—Zn oxide is used, the ratio of the number of atoms of In, M, and Zn is In: M: Zn = 5: 1: 6, In: M: Zn = 4: 2: 3. In: M: Zn = 1: 1: 1, In: M: Zn = 1: 3: 4, In: M: Zn = 1: 3: 2, or a film formed with a sputtering target in the vicinity thereof Of these, it is preferable to use two or more layers.

  Alternatively, the semiconductor layer 108 in which two or more metal oxide films having different crystallinity are stacked can be used.

  For example, in the case where the semiconductor layer 108 is formed by stacking two metal oxide films with different crystallinity, the same oxide target is used and the film formation conditions are different, so that the semiconductor layer 108 is continuously formed without being exposed to the atmosphere. Is preferred.

  For example, the oxygen flow rate ratio at the time of forming the first metal oxide film formed first is made smaller than the oxygen flow rate ratio at the time of forming the second metal oxide film formed later. Alternatively, oxygen is not allowed to flow when the first metal oxide film is formed. Thereby, oxygen can be effectively supplied when forming the second metal oxide film. In addition, the first metal oxide film can be a film having lower crystallinity and higher electrical conductivity than the second metal oxide film. On the other hand, the second metal oxide film provided on the top is a film having higher crystallinity than the first metal oxide film, so that damage during the processing of the semiconductor layer 108 or the film formation of the insulating layer 110 is caused. Can be suppressed. For example, a CAC-OS film can be used for the first metal oxide film, and a CAAC-OS film can be used for the second metal oxide film.

  More specifically, the oxygen flow rate ratio during the formation of the first metal oxide film is 0% or more and less than 50%, preferably 0% or more and 30% or less, more preferably 0% or more and 20% or less. Specifically, it is 10%. The oxygen flow rate ratio during the formation of the second metal oxide film is 50% to 100%, preferably 60% to 100%, more preferably 80% to 100%, and still more preferably 90% or more. 100% or less, typically 100%. In addition, the first metal oxide film and the second metal oxide film may have different conditions such as pressure, temperature, and power at the time of film formation, but the conditions other than the oxygen flow rate ratio are the same. This is preferable because the time required for the film forming process can be shortened.

  When the semiconductor layer 108 has such a stacked structure, a transistor with excellent electrical characteristics and high reliability can be realized.

  Next, the transistor 100A will be described. Hereinafter, differences from the transistor 100 will be mainly described. The above description can be referred to for a portion common to the transistor 100.

  The transistor 100A includes an insulating layer 210 that functions as a gate insulating layer. The insulating layer 210 is thicker than at least the insulating layer 110 included in the transistor 100. The insulating layer 210 can be formed using a material similar to that of the insulating layer 110.

  The thickness of the insulating layer 110 of the transistor 100 can be, for example, 5 nm to 50 nm, preferably 10 nm to 40 nm, more preferably 10 nm to 30 nm. Here, the metal oxide film that can be used for the semiconductor layer 108 can increase the flatness of the surface thereof, so that a highly reliable transistor can be realized even when the insulating layer 110 is thinned to about 5 nm. it can.

  On the other hand, the thickness of the insulating layer 210 of the transistor 100A may be at least thicker than the thickness of the insulating layer 110. For example, the thickness is 30 nm to 300 nm, preferably 50 nm to 250 nm, more preferably 100 nm to 200 nm. be able to. Note that the thickness of the insulating layer 210 is not limited to this, and may be larger than 300 nm depending on a withstand voltage characteristic required for the transistor 100A.

  6A2 and 6B show the channel length L2 of the transistor 100A, and FIGS. 6A2 and 6C show the channel length W2 of the transistor 100A.

  The channel length L1 of the transistor 100 is shorter than the channel length L2 of the transistor 100A. In addition, the channel width W2 of the transistor 100A may be approximately the same as or larger than the channel width W1 of the transistor 100.

  The channel length L1 of the transistor 100 is less than 1.5 μm, preferably 1.2 μm or less, more preferably 1.0 μm or less, further preferably 0.9 μm or less, more preferably 0.8 μm or less, and further preferably 0.6 μm. It is below and it is preferable that it is 0.1 micrometer or more. On the other hand, the channel length L2 of the transistor 100A is 1 μm or more, preferably 1.2 μm or more, more preferably 1.4 μm or more, and is 20 μm or less, preferably 15 μm or less, more preferably 10 μm or less. Note that the channel length L1 of the transistor 100 and the channel length L2 of the transistor 100A are not limited to this, and can be set to optimum sizes according to required transistor characteristics.

  Here, in a transistor using general polysilicon, an impurity is doped in order to reduce the resistance of the source region and the drain region. At this time, part of the doped impurities diffuses into the channel formation region. Therefore, when the channel length L is extremely shortened (for example, 3 μm or less), it may be difficult to obtain transistor characteristics. On the other hand, the transistor 100 to which the metal oxide of one embodiment of the present invention is applied can obtain favorable transistor characteristics even when the channel length L is reduced to 0.7 μm or less.

  In addition, since the general polysilicon film has extremely large surface undulations due to crystallization, there is a problem that a sufficient gate breakdown voltage cannot be obtained if the gate insulating layer is made thinner than the undulations. . Therefore, in a transistor using a general polysilicon film, it is difficult to make the gate insulating layer thin, and the thickness needs to be about 100 nm even if it is thin. On the other hand, since the surface of the metal oxide film used for the semiconductor layer 108 of the transistor 100 of one embodiment of the present invention is extremely flat, the thickness of the insulating layer 110 serving as a gate insulating layer is sufficiently thin (eg, 20 nm). The following):

  The above is the description of the configuration example 1.

  Hereinafter, a configuration example of a transistor having a part of the configuration different from the configuration example 1 will be described. In addition, below, description may be abbreviate | omitted about the part which overlaps with the said structural example 1. FIG. Moreover, in the drawings shown below, portions having the same functions as those of the above configuration example 1 have the same hatching pattern and may not be denoted by reference numerals.

[Configuration example 2]
7A1 is a top view of the transistor 100B, FIG. 7B1 is a cross-sectional view in the channel length direction of the transistor 100B, and FIG. 7C1 is a cross-sectional view in the channel width direction of the transistor 100B. It is. 7A2 is a top view of the transistor 100C, FIG. 7B2 is a cross-sectional view of the transistor 100C in the channel length direction, and FIG. 7C2 is a channel width direction of the transistor 100C. It is sectional drawing.

  Similar to the relationship between the transistor 100 and the transistor 100A, the transistor 100B and the transistor 100C are mainly different in that the channel length and the channel width are different and the thickness of the insulating layer functioning as a gate insulating layer is different. Yes.

  The transistor 100B and the transistor 100C are mainly different from the structure example 1 in that the conductive layer 106 is provided between the substrate 102 and the insulating layer 104. The conductive layer 106 has a portion overlapping with the semiconductor layer 108 with the insulating layer 104 interposed therebetween.

  In the transistor 100B and the transistor 100C, the conductive layer 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the conductive layer 112 serves as a second gate electrode (also referred to as a top gate electrode). It has a function. A part of the insulating layer 104 functions as a first gate insulating layer, and a part of the insulating layer 110 or the insulating layer 210 functions as a second gate insulating layer.

  A portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. Note that a portion overlapping with the conductive layer 112 of the semiconductor layer 108 (a portion corresponding to the region 108 i) is sometimes referred to as a channel formation region in the following description for ease of explanation. In addition, a channel can be formed in a portion overlapping with the conductive layer 106 (a portion corresponding to the region 108n).

  Here, as illustrated in FIGS. 7A1 and 7B1, the channel length L1 in the transistor 100B is the width in the channel length direction of the conductive layer 112 positioned above the semiconductor layer 108. In addition, as illustrated in FIGS. 7A1 and 7C1, the channel width W1 in the transistor 100B is a width in a channel width direction in a portion where the conductive layer 112 of the semiconductor layer 108 overlaps. The same applies to the channel length L2 and the channel width W2 of the transistor 100C.

  In addition, as illustrated in FIGS. 7C1 and 7C2, the conductive layer 106 is electrically connected to the conductive layer 112 through the insulating layer 104 and the opening 142 provided in the insulating layer 110 or the insulating layer 210. May be. Accordingly, the same potential can be applied to the conductive layer 106 and the conductive layer 112.

  The conductive layer 106 can be formed using a material similar to that of the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, the conductive layer 106 is preferably formed using a material containing copper because resistance can be reduced.

  In addition, as illustrated in FIGS. 7A1 and 7C1 and FIGS. 7A2 and 7C2, the conductive layer 112 and the conductive layer 106 are located outside the end portion of the semiconductor layer 108 in the channel width direction. It is preferable that it protrudes. At this time, as illustrated in FIGS. 7C1 and 7C2, the entire semiconductor layer 108 in the channel width direction is electrically connected to the conductive layer 112 and the conductive layer 106 with the insulating layer 110 or the insulating layer 210 and the insulating layer 104 interposed therebetween. It becomes the structure covered with.

  With such a structure, the semiconductor layer 108 can be electrically surrounded by an electric field generated by the pair of gate electrodes. At this time, it is particularly preferable to apply the same potential to the conductive layer 106 and the conductive layer 112. Accordingly, an electric field for inducing a channel can be effectively applied to the semiconductor layer 108, so that the on-state current of the transistor 100B and the transistor 100C can be increased. Therefore, the transistor 100B can be miniaturized.

  Note that the conductive layer 112 and the conductive layer 106 may not be connected to each other. At this time, a constant potential may be applied to one of the pair of gate electrodes, and a signal for driving the transistor 100B or the transistor 100C may be applied to the other. At this time, the threshold voltage when the transistor 100B or the transistor 100C is driven by the other electrode can be controlled by the potential applied to the one electrode.

  The above is the description of the configuration example 2.

  In each transistor illustrated in Structural Example 1 and Structural Example 2, the metal oxide layer 117 and the insulating layer 118 are provided between the gate electrode located above the semiconductor layer 108 and the source and drain electrodes. Compared with a bottom-gate transistor, the parasitic capacitance between them is reduced. In particular, the insulating layer 118 has little influence on the electrical characteristics of the transistor even when the thickness is increased, and thus parasitic capacitance can be further reduced. Therefore, each of the transistors exemplified in Configuration Example 1 and Configuration Example 2 can be easily driven at a high frequency, and thus can be suitably used for a display portion of a display device or a drive circuit portion.

[Components of semiconductor devices]
Next, components included in the semiconductor device of the present embodiment will be described in detail.

〔substrate〕
There is no particular limitation on the material of the substrate 102, but it is necessary that the substrate 102 have at least heat resistance to withstand heat treatment performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element is provided over these substrates. A substrate may be used as the substrate 102. When a glass substrate is used as the substrate 102, the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), the tenth generation. A large display device can be manufactured by using a large-sized substrate such as a generation (2950 mm × 3400 mm), or a 10.5th generation, an 11th generation, or a 12th generation.

  Alternatively, a flexible substrate may be used as the substrate 102, and the transistor 100 or the like may be formed directly over the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor 100 or the like. The separation layer can be used for separation from the substrate 102 and transfer to another substrate after the semiconductor device is partially or entirely completed thereon. At that time, the transistor 100 or the like can be transferred to a substrate having poor heat resistance or a flexible substrate.

[Insulating layer 104]
The insulating layer 104 can be formed using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. As the insulating layer 104, for example, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer. Note that in order to improve interface characteristics with the semiconductor layer 108, at least a region in contact with the semiconductor layer 108 in the insulating layer 104 is preferably formed using an oxide insulating film. Further, by using an oxide insulating film from which oxygen is released by heating as the insulating layer 104, oxygen contained in the insulating layer 104 can be transferred to the semiconductor layer 108 by heat treatment.

  The thickness of the insulating layer 104 can be greater than or equal to 50 nm, or greater than or equal to 100 nm and less than or equal to 3000 nm, or greater than or equal to 200 nm and less than or equal to 1000 nm. By increasing the thickness of the insulating layer 104, the amount of oxygen released from the insulating layer 104 can be increased, and interface states at the interface between the insulating layer 104 and the semiconductor layer 108 and oxygen vacancies included in the semiconductor layer 108 can be reduced. Is possible.

  As the insulating layer 104, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide can be used, and the insulating layer 104 can be provided as a single layer or a stacked layer. In this embodiment, a stacked structure of a silicon nitride film and a silicon oxynitride film is used as the insulating layer 104. In this manner, oxygen can be efficiently introduced into the semiconductor layer 108 by using the insulating layer 104 as a stacked structure and using a silicon nitride film on the lower layer side and a silicon oxynitride film on the upper layer side.

  Alternatively, a film other than an oxide film such as a silicon nitride film can be used on the side in contact with the semiconductor layer 108 of the insulating layer 104. At this time, it is preferable to perform pretreatment such as oxygen plasma treatment on the surface of the insulating layer 104 in contact with the semiconductor layer 108 to oxidize the surface of the insulating layer 104 or the vicinity thereof.

[Conductive film]
As the conductive layer 112 and the conductive layer 106 functioning as a gate electrode, the conductive layer 120a functioning as a source electrode, and the conductive layer 120b functioning as a drain electrode, chromium (Cr), copper (Cu), aluminum (Al), gold ( Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt ( Co), an alloy containing the above-described metal element as a component, an alloy combining the above-described metal elements, or the like can be used.

  The conductive layer 112 and the conductive layer 106 functioning as gate electrodes, the conductive layer 120a functioning as a source electrode, and the conductive layer 120b functioning as a drain electrode include an oxide containing indium and tin (In-Sn oxide). , Oxide containing indium and tungsten (In-W oxide), oxide containing indium, tungsten and zinc (In-W-Zn oxide), oxide containing indium and titanium (In-Ti oxidation) ), An oxide containing indium, titanium and tin (In-Ti-Sn oxide), an oxide containing indium and zinc (In-Zn oxide), an oxide containing indium, tin and silicon ( In-Sn-Si oxide), oxide conductors such as oxide containing indium, gallium, and zinc (In-Ga-Zn oxide) or gold It is also possible to apply the oxide film.

  Here, the oxide conductor will be described. In this specification and the like, the oxide conductor may be referred to as OC (Oxide Conductor). As an oxide conductor, for example, when an oxygen vacancy is formed in a metal oxide and hydrogen is added to the oxygen vacancy, a donor level is formed in the vicinity of the conduction band. As a result, the metal oxide becomes highly conductive and becomes a conductor. The conductive metal oxide can be referred to as an oxide conductor. In general, a metal oxide has a large energy gap and thus has a light-transmitting property with respect to visible light. On the other hand, an oxide conductor is a metal oxide having a donor level near the conduction band. Therefore, the oxide conductor is less affected by the absorption due to the donor level and has a light-transmitting property similar to that of the metal oxide with respect to visible light.

  Alternatively, the conductive layer 112 may have a stacked structure of a conductive film including the oxide conductor (metal oxide) and a conductive film including a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced. At this time, a conductive film including an oxide conductor is preferably applied to a side in contact with the insulating layer functioning as a gate insulating film.

  Further, a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) is applied to the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b. Also good. By using a Cu-X alloy film, it can be processed by a wet etching process, and thus manufacturing costs can be suppressed.

  In addition, the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b each include any one or more selected from titanium, tungsten, tantalum, and molybdenum among the above metal elements. Is preferred. In particular, a tantalum nitride film is preferably used as the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b. The tantalum nitride film has conductivity and high barrier properties against copper or hydrogen. Further, since the tantalum nitride film emits less hydrogen from itself, it can be preferably used as a conductive film in contact with the semiconductor layer 108 or a conductive film in the vicinity of the semiconductor layer 108.

[Insulating layer 110, insulating layer 210]
As the insulating layer 110 and the insulating layer 210 which function as a gate insulating film of the transistor 100 or the like, a silicon oxide film or a silicon oxynitride film is formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like. Film, silicon nitride oxide film, silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film and neodymium oxide film Can be used. Note that the insulating layer 110 or the insulating layer 210 may have a two-layer structure or a three-layer structure.

  The insulating layer 110 and the insulating layer 210 in contact with the semiconductor layer 108 functioning as a channel region of the transistor 100 or the like are preferably oxide insulating films, and regions containing oxygen in excess of the stoichiometric composition ( More preferably, it has an excess oxygen region. In other words, the insulating layer 110 and the insulating layer 210 are insulating films capable of releasing oxygen. Note that in order to provide an excess oxygen region in the insulating layer 110 and the insulating layer 210, for example, the insulating layer 110 and the insulating layer 210 are formed in an oxygen atmosphere, or the insulating layer 110 and the insulating layer 210 after film formation are oxygenated. Heat treatment may be performed in an atmosphere.

  In addition, when hafnium oxide is used as the insulating layer 110 and the insulating layer 210, the following effects are obtained. Hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Accordingly, the thickness of the insulating layer 110 and the insulating layer 210 can be increased as compared with the case where silicon oxide is used, so that the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off-state current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system and a cubic system. Note that one embodiment of the present invention is not limited thereto.

The insulating layer 110 and the insulating layer 210 preferably have few defects. Typically, it is preferable that the number of signals observed by an electron spin resonance (ESR) method is small. For example, the signal described above includes the E ′ center where the g value is observed at 2.001. The E ′ center is caused by silicon dangling bonds. As the insulating layer 110 and the insulating layer 210, a silicon oxide film or a silicon oxynitride whose spin density due to the E ′ center is 3 × 10 ¹⁷ spins / cm ³ or less, preferably 5 × 10 ¹⁶ spins / cm ³ or less A film may be used.

[Semiconductor layer]
In the case where the semiconductor layer 108 is an In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide preferably satisfies In> M. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 6, In: M: Zn = 5: 1: 7, In: M: Zn = 5: 1: 8, In: M: Zn = 6: 1: 6, In: M: Zn = 5: 2: 5, and the like.

  In the case where the semiconductor layer 108 is an In-M-Zn oxide, a target including a polycrystalline In-M-Zn oxide is preferably used as the sputtering target. By using a target including a polycrystalline In—M—Zn oxide, the semiconductor layer 108 having crystallinity can be easily formed. Note that the atomic ratio of the semiconductor layer 108 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element included in the sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In: Ga: Zn = 4: 2: 4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed is In: Ga: Zn = It may be in the vicinity of 4: 2: 3 [atomic ratio].

  The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.

  The semiconductor layer 108 preferably has a non-single crystal structure. The non-single-crystal structure includes, for example, a CAAC-OS (C Axis Crystalline Oxide Semiconductor), a polycrystalline structure, a microcrystalline structure, or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

  The above is the description of the components of the semiconductor device.

[Example of production method]
Hereinafter, an example of a method for forming two transistors having different gate insulating layer thickness over the same substrate will be described. Here, the transistor 100 and the transistor 100A exemplified in the above configuration example 1 are described as examples.

  Note that a thin film (an insulating film, a semiconductor film, a conductive film, or the like) included in the semiconductor device can be formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, or pulse laser deposition (PLD). ) Method, atomic layer deposition (ALD) method, or the like. Examples of the CVD method include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. As one of thermal CVD methods, there is a metal organic chemical vapor deposition (MOCVD) method.

  Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices are spin coat, dip, spray coating, ink jet, dispense, screen printing, offset printing, doctor knife, slit coat, roll coat, curtain coat. It can be formed by a method such as knife coating.

  Further, when a thin film included in the semiconductor device is processed, the thin film can be processed using a photolithography method or the like. In addition, the thin film may be processed by a nanoimprint method, a sand blast method, a lift-off method, or the like. Further, the island-shaped thin film may be directly formed by a film forming method using a shielding mask such as a metal mask.

  As a photolithography method, there are typically the following two methods. One is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is removed. The other is a method in which a thin film having photosensitivity is formed and then exposed and developed to process the thin film into a desired shape.

  In photolithography, light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Further, exposure may be performed by an immersion exposure technique. Further, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used as light used for exposure. Further, an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays, or an electron beam because extremely fine processing is possible. Note that a photomask is not necessary when exposure is performed by scanning a beam such as an electron beam.

  For etching the thin film, a dry etching method, a wet etching method, a sand blasting method, or the like can be used.

  8 and 9 are cross-sectional views in the channel length direction for describing a method for manufacturing the transistor 100 and the transistor 100A. In each figure, the left side from the broken line at the center is a region where the transistor 100 is formed, and the right side is a region where the transistor 100A is formed.

[Formation of Insulating Layer 104]
First, the insulating layer 104 is formed over the substrate 102. The insulating layer 104 can be formed by a plasma CVD method, an ALD method, a sputtering method, or the like.

  Note that in the case where the conductive layer 106 described in Structural Example 2 is provided, the conductive layer 106 can be formed before the insulating layer 104 is formed. The conductive layer 106 can be formed by forming a conductive film over the substrate 102 and processing it by etching.

[Formation of Semiconductor Layer 108]
Subsequently, a metal oxide film is formed over the insulating layer 104 (FIG. 8A).

  The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target.

  In forming the metal oxide film 108f, an inert gas (eg, helium gas, argon gas, xenon gas, or the like) may be mixed in addition to the oxygen gas. Note that the ratio of oxygen gas to the entire deposition gas when forming the metal oxide film (hereinafter also referred to as oxygen flow ratio) is 0% to 100%, preferably 5% to 20%. It is preferable to do. A transistor with an increased on-state current can be obtained by reducing the oxygen flow rate ratio and forming the metal oxide film 108f with relatively low crystallinity.

  The metal oxide film 108f may be formed at a substrate temperature of room temperature to 180 ° C., preferably the substrate temperature of room temperature to 140 ° C. It is preferable that the substrate temperature at the time of forming the metal oxide film 108f be, for example, room temperature or higher and lower than 140 ° C. because productivity is increased. In addition, when the metal oxide film 108f is formed with the substrate temperature set to room temperature or without intentional heating, the metal oxide film 108f with low crystallinity can be easily formed.

  The thickness of the metal oxide film 108f may be 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 60 nm.

  Note that when a large glass substrate (for example, the sixth generation to the twelfth generation) is used as the substrate 102, the substrate temperature when the metal oxide film 108f is formed is 200 ° C. or higher and 300 ° C. or lower. 102 may be deformed (distorted or warped). Therefore, in the case of using a large glass substrate, deformation of the glass substrate can be suppressed by setting the substrate temperature at the time of forming the metal oxide film 108f to a room temperature or higher and lower than 200 ° C.

  In addition, it is necessary to increase the purity of the sputtering gas. For example, oxygen gas or argon gas used as a sputtering gas is a gas having a dew point of −40 ° C. or lower, preferably −80 ° C. or lower, more preferably −100 ° C. or lower, more preferably −120 ° C. or lower. By using it, moisture and the like can be prevented from being taken into the metal oxide film 108f as much as possible.

In the case where the metal oxide film 108f is formed by a sputtering method, the chamber in the sputtering apparatus is provided with an adsorption-type vacuum exhaust pump such as a cryopump so as to remove water or the like that is an impurity for the metal oxide as much as possible. It is preferable to use and exhaust to a high vacuum (from about 5 × 10 ⁻⁷ Pa to about 1 × 10 ⁻⁴ Pa). In particular, the partial pressure of gas molecules corresponding to H ₂ O in the chamber (gas molecules corresponding to m / z = 18) in the standby state of the sputtering apparatus is 1 × 10 ⁻⁴ Pa or less, preferably 5 × 10 ^−5. It is preferable to set it to Pa or less.

  Further, before the metal oxide film 108f is formed, heat treatment for desorbing water or hydrogen adsorbed on the surface of the insulating layer 104 is preferably performed. For example, the heat treatment can be performed at a temperature of 70 ° C. or higher and 200 ° C. or lower in a reduced pressure atmosphere. At this time, it is preferable to continuously form the metal oxide film 108f without exposing the surface of the insulating layer 104 to the atmosphere. For example, the film formation apparatus preferably has a structure in which a heating chamber for heating the substrate and a film formation chamber for forming the metal oxide film 108f are connected to each other through a gate valve or the like.

  Subsequently, the metal oxide film 108f is processed to form an island-shaped semiconductor layer 108 (FIG. 8B).

  Either or both of a wet etching method and a dry etching method may be used for processing the metal oxide film 108f.

  Alternatively, after the metal oxide film 108f is formed or processed into the semiconductor layer 108, heat treatment may be performed to dehydrogenate or dehydrate the metal oxide film 108f or the semiconductor layer 108. The temperature of the heat treatment is typically 150 ° C. or higher and lower than the strain point of the substrate, 250 ° C. or higher and 450 ° C. or lower, or 300 ° C. or higher and 450 ° C. or lower.

  The heat treatment can be performed in an inert atmosphere containing nitrogen, a rare gas such as helium, neon, argon, xenon, or krypton. Alternatively, after heating in an inert atmosphere, heating may be performed in an oxygen atmosphere. Note that it is preferable that the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water, or the like. The treatment time may be 3 minutes or more and 24 hours or less.

  For the heat treatment, an electric furnace, an RTA apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

The metal oxide film 108f is formed while being heated, or after the metal oxide film 108f is formed, heat treatment is performed, whereby the hydrogen concentration in the metal oxide film 108f obtained by SIMS is set to 5 × 10 ¹⁹ atoms. / Cm ³ or less, or 1 × 10 ¹⁹ atoms / cm ³ or less, 5 × 10 ¹⁸ atoms / cm ³ or less, or 1 × 10 ¹⁸ atoms / cm ³ or less, or 5 × 10 ¹⁷ atoms / cm ³ or less, or 1 × 10 ¹⁶ atoms / cm ³ or less.

[Formation of Insulating Film 110f]
Next, an insulating film 110f to be the insulating layer 110 and the insulating layer 210 is formed over the semiconductor layer 108 and the insulating layer 104 (FIG. 8C).

  As the insulating film 110f, an oxide film such as a silicon oxide film or a silicon oxynitride film is preferably formed using a plasma chemical vapor deposition apparatus (a PECVD apparatus or simply a plasma CVD apparatus). In this case, it is preferable to use a deposition gas and an oxidation gas containing silicon as the source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

  In addition, as the insulating film 110f, PECVD is performed such that the flow rate of the oxidizing gas with respect to the flow rate of the deposition gas is greater than 20 times and less than 100 times, or 40 times or more and 80 times or less, and the pressure in the processing chamber is less than 100 Pa or 50 Pa or less. By using the apparatus, a silicon oxynitride film with a small amount of defects can be formed.

  In addition, as the insulating film 110f, the substrate placed in the processing chamber evacuated in the PECVD apparatus is held at 280 ° C. or higher and 350 ° C. or lower, and a source gas is introduced into the processing chamber so that the pressure in the processing chamber is 20 Pa or higher and 250 Pa. Hereinafter, a dense silicon oxide film or silicon oxynitride film can be formed as the insulating film 110f under the condition where the pressure is higher than or equal to 100 Pa and lower than or equal to 250 Pa and high-frequency power is supplied to the electrode provided in the processing chamber.

  Alternatively, the insulating film 110f may be formed using a PECVD method using microwaves. Microwave refers to the frequency range from 300 MHz to 300 GHz. Microwaves have a low electron temperature and a low electron energy. In addition, in the supplied power, the ratio used for accelerating electrons is small, it can be used for dissociation and ionization of more molecules, and high density plasma (high density plasma) can be excited. . Therefore, the insulating film 110f with less plasma damage and less defects on the deposition surface and the deposit can be formed.

[Processing of insulating film 110f]
Subsequently, a resist mask 151 is formed over the insulating film 110f. The resist mask 151 is provided so as to cover at least a portion which will later become the insulating layer 110 of the transistor 100.

  After that, a portion of the insulating film 110f that is not covered with the resist mask 151 is thinned by etching (FIG. 8D). Thereafter, the resist mask 151 is removed.

  It is important to perform the etching so that the insulating film 110f is not lost. As an etching method, a wet etching method may be used, but a dry etching method is preferable because the etching rate can be easily controlled.

  Further, when two or more films having different etching rates are stacked as the insulating film 110f, the insulating film 110f can be suitably prevented from disappearing. Thus, the insulating film 110f can be processed with a high yield even when, for example, a large substrate is used.

  Here, in the processed insulating film 110f, damage due to the etching process, organic contamination in the removal process of the resist mask 151, or the like may occur. Therefore, it is preferable to clean the upper surface of the insulating film 110f after the processing of the insulating film 110f. Alternatively, a part of the upper portion of the insulating film 110f may be thinly etched. Further, by performing heat treatment after the processing of the insulating film 110f, damage and contamination associated with the processing can be reduced.

  Subsequently, a metal oxide film 114f to be the metal oxide layer 114 is formed over the insulating film 110f.

  The metal oxide film 114f is preferably formed, for example, in an atmosphere containing oxygen. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. Accordingly, oxygen can be supplied to the insulating film 110f when the metal oxide film 114f is formed.

  For example, as a film formation condition of the metal oxide film 114f, it is preferable to form the metal oxide film by a reactive sputtering method using oxygen as a film formation gas and using a metal target. When aluminum is used as the metal target, for example, an aluminum oxide film can be formed.

  When the metal oxide film 114f is formed, the higher the ratio (oxygen flow ratio) of the oxygen flow rate to the total flow rate of the film formation gas introduced into the film formation chamber of the film formation apparatus or the higher the oxygen partial pressure in the film formation chamber, the higher The oxygen supplied into the film 110f can be increased. The oxygen flow rate ratio or the oxygen partial pressure is, for example, 50% to 100%, preferably 65% to 100%, more preferably 80% to 100%, and still more preferably 90% to 100%. In particular, it is preferable that the oxygen flow rate ratio is 100% and the oxygen partial pressure is as close as possible to 100%.

  In this manner, by forming the metal oxide film 114f by a sputtering method in an atmosphere containing oxygen, oxygen is supplied to the insulating film 110f when the metal oxide film 114f is formed, and oxygen is supplied from the insulating film 110f. Desorption can be prevented. As a result, a very large amount of oxygen can be confined in the insulating film 110f. A large amount of oxygen can be supplied to the semiconductor layer 108 by heat treatment performed later. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced and a highly reliable transistor can be realized.

  In the case of the structure exemplified in Structure Example 2, the metal oxide film 114f, the insulating film 110f, and part of the insulating layer 104 are etched after the metal oxide film 114f is formed, whereby the conductive layer 106 is formed. Form an opening to reach. Accordingly, the conductive layer 112 and the conductive layer 106 to be formed later can be electrically connected through the opening.

[Formation of Conductive Film 112f]
Subsequently, a conductive film 112f to be the conductive layer 112 is formed over the metal oxide film 114f (FIG. 8E).

  The conductive film 112f is preferably formed by a sputtering method using a metal or alloy sputtering target.

[Etching of Conductive Film 112f, Metal Oxide Film 114f, and Insulating Film 110f]
Subsequently, part of the conductive film 112f, the metal oxide film 114f, and the insulating film 110f is etched to expose part of the semiconductor layer 108.

  Here, the conductive film 112f, the metal oxide film 114f, and the insulating film 110f are each preferably processed using the same resist mask. Alternatively, the metal oxide film 114f and the insulating film 110f may be etched using the etched conductive layer 112 as a hard mask.

  Accordingly, the insulating layer 110 and the insulating layer 210 having different thicknesses can be formed at the same time.

  As shown in FIG. 9A, in the region where the transistor 100 is formed after the etching of the insulating film 110f, the island-shaped conductive layer 112, the metal oxide layer 114, and the insulating layer 110 whose top shapes are approximately the same are formed. In the region where the transistor 100A is formed, the island-shaped conductive layer 112, the metal oxide layer 114, and the insulating layer 210 whose upper surface shapes are approximately the same are formed.

  Note that when the conductive film 112f, the metal oxide film 114f, and the insulating film 110f are etched, part of the semiconductor layer 108 that is not covered with the insulating layer 110 and the insulating layer 210 is also etched to be thin.

  Here, when the resist mask is formed on the conductive film 112f, the pattern width of the resist mask can be reduced more than the minimum processing dimension in an apparatus such as an exposure machine or a developing machine by adjusting the exposure time. For example, a resist pattern finer than the minimum processing dimension can be formed by using a photomask having a pattern width thinner than the minimum processing dimension and shortening the exposure time as compared with the conventional case. Alternatively, a resist pattern finer than the minimum processing dimension may be formed by using a photomask having a pattern width equal to or larger than the minimum processing dimension, for example, by making the exposure time longer than the conventional one.

  Alternatively, the resist mask formed over the conductive film 112f may be subjected to slimming treatment to reduce the width of the resist mask, and the processed conductive layer 112 may be reduced in width in the channel length direction. Alternatively, in the case where the conductive film 112f or the like is etched using a hard mask, a slimming process can be performed on the resist mask used when the hard mask is processed. As the slimming treatment, for example, after forming a resist mask, the pattern width of the resist mask is increased by plasma treatment or heat treatment in an atmosphere containing oxygen, or treatment of irradiating ultraviolet light in a state exposed to an ozone atmosphere. Can be reduced.

  By the above-described method, a resist pattern having a width smaller than the minimum processing dimension can be formed. For example, even when an apparatus having a minimum pattern width processing size of about 2.0 μm or about 1.5 μm is used, the pattern width is less than 1.5 μm, preferably less than 1.0 μm, more preferably less than 0.5 μm. It becomes possible to reduce.

[Formation of the first layer 116]
Subsequently, the first layer 116 is formed.

  Here, as the first layer 116, an insulating film or a conductive film can be formed.

  As the first layer 116, a film containing at least one of metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium is formed. In particular, at least one of aluminum, titanium, tantalum, and tungsten is preferably included. In particular, a nitride containing at least one of these metal elements or an oxide containing at least one of these metal elements can be preferably used. As the insulating film, a nitride film such as an aluminum titanium nitride film, a titanium nitride film, or an aluminum nitride film, an oxide film such as an aluminum titanium oxide film, or the like can be preferably used.

  For example, as the first layer 116, a metal film or an alloy film containing at least one of metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium can be formed in addition to the above. In particular, at least one of aluminum, titanium, tantalum, and tungsten is preferably included.

  Here, the first layer 116 is preferably formed by a sputtering method using nitrogen gas or oxygen gas as a deposition gas. Thereby, even when the same sputtering target is used, the film quality can be easily controlled by controlling the flow rate of the film forming gas.

[Heat treatment]
Subsequently, heat treatment is performed. As illustrated in FIG. 9B, the resistance of the region in contact with the first layer 116 of the semiconductor layer 108 is reduced by heat treatment, so that a low-resistance region 108 n is formed in the semiconductor layer 108.

  The heat treatment is preferably performed in an inert gas atmosphere such as nitrogen or a rare gas. The higher the temperature of the heat treatment, the better, but the temperature can be set in consideration of the heat resistance of the substrate 102, the conductive layer 106, the conductive layer 112, and the like. For example, the temperature can be 120 ° C. or higher and 500 ° C. or lower, preferably 150 ° C. or higher and 450 ° C. or lower, more preferably 200 ° C. or higher and 400 ° C. or lower, and even more preferably 250 ° C. or higher and 400 ° C. or lower. For example, by setting the temperature of the heat treatment to about 350 ° C., a semiconductor device can be manufactured with high yield using a production facility using a large glass substrate.

  By the heat treatment, oxygen in the semiconductor layer 108 is extracted to the first layer 116, whereby oxygen vacancies are generated. The oxygen vacancies and hydrogen contained in the semiconductor layer 108 are combined to increase the carrier concentration, so that the portion in contact with the first layer 116 is reduced in resistance.

  Alternatively, in some cases, the metal element contained in the first layer 116 is diffused into the semiconductor layer 108 by heat treatment, so that part of the semiconductor layer 108 is alloyed and the resistance is reduced.

  Alternatively, nitrogen included in the first layer 116 or nitrogen included in the heat treatment atmosphere may diffuse into the semiconductor layer 108 by heat treatment, so that the resistance of the first layer 116 may be reduced.

  The region 108n of the semiconductor layer 108 whose resistance is reduced by such a composite action is an extremely stable low resistance region. The region 108n formed in this manner has a characteristic that resistance is not easily increased even if, for example, a process of supplying oxygen is performed in a later process.

  In particular, a film that releases hydrogen by heating is provided in contact with part of the semiconductor layer 108, and the resistance is reduced by supplying the hydrogen to part of the semiconductor layer 108, so that it is less diffusible than hydrogen. It is preferable to use a method of reducing resistance by supplying a metal element or an element such as nitrogen to part of the semiconductor layer 108. Accordingly, an increase in carrier concentration in the region 108i functioning as a channel formation region can be suppressed. As a result, good switching characteristics can be obtained even when the channel length of the transistor is extremely short. For example, good switching characteristics can be obtained even with a fine transistor with a channel length of 100 nm or less.

[Removal of the first layer 116]
Subsequently, the first layer 116 is removed by etching.

  When the first layer 116a is etched, part of the conductive layer 112, the metal oxide layer 114, the insulating layer 110 or the insulating layer 210, the semiconductor layer 108, and the like may be etched. In particular, when a metal film or an alloy film is used for the first layer 116, it is preferable to select an etching method using a material different from that of the conductive layer 112 and having a high selectivity of the etching rate.

  Note that in the case where an insulating material is used for the first layer 116 or a material which is insulated by the heat treatment is used, the first layer 116 may be left without being etched.

[Formation of Metal Oxide Layer 117]
Subsequently, a metal oxide layer 117 is formed over the first layer 116. The metal oxide layer 117 can be formed by a method similar to that of the metal oxide film 114f.

  When the metal oxide layer 117 is formed, oxygen may be added to the region 108n of the semiconductor layer 108. However, the region 108n is difficult to increase in resistance and maintains a low resistance state.

  Further, when the metal oxide layer 117 is formed, oxygen can be supplied from the side surface of the insulating layer 110 or the insulating layer 210 functioning as a gate insulating layer through the first layer 116. In some cases, oxygen can be supplied to the insulating layer 104 through the semiconductor layer 108.

  Heat treatment may be performed after the metal oxide layer 117 is formed. By performing heat treatment while the semiconductor layer 108 is covered with the metal oxide layer 117 functioning as a barrier layer, the insulating layer 110, the insulating layer 210, or the insulating layer 104 is formed in the region 108i that is a channel formation region of the semiconductor layer 108. Thus, oxygen can be preferably supplied to reduce the carrier concentration.

[Formation of Insulating Layer 118]
Subsequently, an insulating layer 118 is formed so as to cover the metal oxide layer 117 (FIG. 9C).

  The insulating layer 118 can be formed by a plasma CVD method, a sputtering method, or the like.

[Formation of Openings 141a and 141b]
Subsequently, after a mask is formed by lithography at a desired position of the insulating layer 118, the insulating layer 118 and a part of the metal oxide layer 117 are etched, whereby the opening 141a and the opening 141b reaching the region 108n are obtained. Form.

[Formation of Conductive Layers 120a and 120b]
Subsequently, a conductive film is formed over the insulating layer 118 so as to cover the opening 141a, the opening 141b, and the opening 141c, and the conductive film is processed into a desired shape, whereby the conductive layer 120a and the conductive layer are formed. 120b is formed (FIG. 9D).

  Through the above steps, the transistor 100 with a thin and thin gate insulating layer and the transistor 100A with a thick gate insulating layer and high withstand voltage performance can be manufactured at the same time. Hereinafter, a process of forming a pixel electrode of a display element that is further electrically connected to the transistor 100A will be described.

[Formation of Insulating Layer 119]
Subsequently, an insulating layer 119 is formed so as to cover the conductive layer 120a, the conductive layer 120b, and the insulating layer 118.

  An organic resin is preferably used for the insulating layer 119 because flatness is increased. Typically, the insulating layer 119 can be formed by a method such as spin coating, dispensing, screen printing, or slit coating.

  Note that an inorganic insulating material may be used for the insulating layer 119. In that case, the insulating layer 118 can be formed by the same method.

  Further, by using a photosensitive resin material for the insulating layer 119, an opening reaching the conductive layer 120a can be formed at the same time as the insulating layer 119 is formed. Note that in the case where a non-photosensitive material is used for the insulating layer 119, an opening may be formed by etching using a mask.

[Formation of Conductive Layer 109]
Subsequently, a conductive layer 109 is formed (FIG. 9E). The conductive layer 109 can be formed by a method similar to that of the conductive layer 112 or the like.

  Through the above steps, the conductive layer 109 which is electrically connected to the transistor 100A can be formed. The conductive layer 109 can be used as a pixel electrode of a display element.

  The above is the description of the manufacturing method example.

[Modified example of manufacturing method]
Hereinafter, an example different from the above manufacturing method example will be described. In addition, below, the part which overlaps with the said manufacturing method example is used, and a different part is mainly demonstrated.

  First, the insulating layer 104 and the semiconductor layer 108 are formed over the substrate 102 as described above.

  Subsequently, an insulating film 110g covering the semiconductor layer 108 is formed (FIG. 10A). The insulating film 110g is a film that later becomes part of the gate insulating layer of the transistor 100D. The insulating film 110g can be formed by a method similar to that of the insulating film 110f.

  Subsequently, part of the insulating film 110g is removed by etching (FIG. 10B). More specifically, as illustrated in FIG. 10B, part of the insulating film 110g located over the semiconductor layer 108 of the transistor 100 is removed by etching. Note that when the insulating film 110g is etched, part of the semiconductor layer 108 is also etched to be thin.

  Subsequently, an insulating film 110h is formed so as to cover the insulating film 110g and a part of the exposed semiconductor layer 108 (FIG. 10C). Here, the insulating film 110 h is a film which will later become a part of the insulating layer 110 of the transistor 100 and the gate insulating layer of the transistor 100.

  Note that the exposed top surface of the semiconductor layer 108 and the top surface of the insulating film 110g are preferably washed before the insulating film 110h is formed.

  Subsequently, a metal oxide film 114f and a conductive film 112f are stacked over the insulating film 110h (FIG. 10D).

  After that, the conductive film 112f, the metal oxide film 114f, the insulating film 110g, and part of the insulating film 110h are etched to expose part of the semiconductor layer 108 (FIG. 10E).

  Thus, the insulating layer 110 functioning as the gate insulating layer of the transistor 100 and the stacked film of the insulating layer 210a and insulating layer 210b functioning as the gate insulating layer of the subsequent transistor 100D can be formed at the same time.

  Subsequently, by a method similar to the above manufacturing method example, formation of the first layer 116, heat treatment, removal of the first layer 116, formation of the metal oxide layer 117, formation of the insulating layer 118, and the conductive layer 120a Further, the transistor 100 and the transistor 100D can be formed at the same time by sequentially forming the conductive layer 120b (FIG. 10F).

  A transistor 100D illustrated in FIG. 10F has a stacked structure in which a gate insulating layer is formed by stacking an insulating layer 210a and an insulating layer 210b. Here, the insulating layer 210 b has the same thickness as the insulating layer 110 included in the transistor 100. Therefore, the thickness of the gate insulating layer of the transistor 100D can be arbitrarily determined by the thickness of the insulating film 110g to be the insulating layer 210a.

  According to the method exemplified here, the step of thinning part of the insulating film 110f in the above manufacturing method example by etching can be omitted. Therefore, controllability of the thickness of the gate insulating layer of each transistor can be improved, and variation in electrical characteristics of each transistor can be reduced.

  The above is the description of the modified example.

[Example of cross-sectional configuration of display panel]
Below, the example of the cross-sectional structure of a display panel is demonstrated with reference to drawings.

  FIG. 11 is a cross-sectional view of a light-emitting display panel having a top emission structure to which a color filter method is applied.

  The display panel illustrated in FIG. 11 includes a display portion 562 and a driver circuit 564. The driver circuit 564 is a circuit that functions as a signal line driver circuit or a scan line driver circuit.

  In addition, as illustrated in FIG. 11, the display panel includes a region 560 on the side opposite to the drive circuit 564 with the display portion 562 interposed therebetween. The region 560 is a region where a light-shielding member is not provided and functions as a region that transmits visible light.

  In the display panel, a transistor 201a included in the driver circuit 564, a transistor 201b included in the display portion 562, a transistor 251, and a light-emitting element 290 are sandwiched between a flexible substrate 261 and a substrate 271. Have

  The substrate 261 is attached to the insulating layer 263 with the adhesive layer 262 interposed therebetween, and the substrate 271 is attached to the insulating layer 273 with the adhesive layer 272 interposed therebetween. The insulating layer 263 and the insulating layer 273 each include an inorganic insulating material and function as a barrier layer for preventing moisture from entering.

  In the display portion 562, a transistor 251, a transistor 201ba, a light-emitting element 290, and the like are provided over the substrate 261. In the driver circuit 564, the transistor 201a and the like are provided over the substrate 261.

  The transistor 251 is a transistor that controls a current flowing through the light-emitting element 290, and a transistor with high withstand voltage performance can be used. As the transistor 251, a transistor with a thicker gate insulating layer than the transistor 201a can be used. For example, the transistor 100A, the transistor 100C, the transistor 100D, or the like described above can be used as the transistor 251.

  On the other hand, the transistor 201a is a transistor that requires high-speed operation among transistors included in the driver circuit 564. As the transistor 201a, a transistor with a gate insulating layer thinner than the transistor 251 and a short channel length can be used. For example, the transistor 100, the transistor 100B, or the like exemplified above can be used as the transistor 201a.

  Note that FIG. 11 illustrates an example in which a transistor similar to the transistor 201a is applied to the transistor 201b that controls the selection state of the pixel.

  The insulating layer 211 functions as the other gate insulating layer of the transistor 251 and the transistor 201a. The insulating layer 212 and the insulating layer 213 are provided so as to cover each transistor.

  The transistor 201b overlaps with the light-emitting element 290 with the insulating layer 215 provided therebetween. By arranging the transistor, the capacitor, the wiring, and the like so as to overlap with the light-emitting region of the light-emitting element 290, the aperture ratio of the display portion 562 can be increased.

  The light-emitting element 290 includes a pixel electrode 291, an EL layer 292, and a common electrode 293. The light-emitting element 290 emits light to the colored layer 281 side.

  One of the pixel electrode 291 and the common electrode 293 functions as an anode, and the other functions as a cathode. The EL layer 292 is a layer containing a light-emitting substance. When a voltage higher than the threshold voltage of the light emitting element 290 is applied between the pixel electrode 291 and the common electrode 293, holes are injected into the EL layer 292 from the anode side and electrons are injected from the cathode side. The injected electrons and holes are recombined in the EL layer 292, and the light-emitting substance contained in the EL layer 292 emits light.

  The pixel electrode 291 is electrically connected to the conductive layer 222b included in the transistor 251. These may be directly connected or may be connected via another conductive layer. The pixel electrode 291 functions as a pixel electrode and is provided for each light emitting element 290. Two adjacent pixel electrodes 291 are electrically insulated by an insulating layer 216.

  The common electrode 293 functions as a common electrode and is provided over the plurality of light emitting elements 290. A constant potential is supplied to the common electrode 293.

  The light-emitting element 290 overlaps with the colored layer 281 with the adhesive layer 294 interposed therebetween. The insulating layer 216 overlaps with the light-blocking layer 282 with the adhesive layer 294 interposed therebetween.

  The light emitting element 290 may adopt a microcavity structure. By combining the color filter (colored layer 281) and the microcavity structure, light with high color purity can be extracted from the display panel.

  The colored layer 281 is a colored layer that transmits light in a specific wavelength range. For example, a color filter that transmits light in a red, green, blue, or yellow wavelength range can be used. As a material that can be used for the colored layer 281, a metal material, a resin material, a resin material containing a pigment or a dye, or the like can be given.

  Note that one embodiment of the present invention is not limited to the color filter method, and a color separation method, a color conversion method, a quantum dot method, or the like may be applied.

  The light shielding layer 282 is provided between the adjacent colored layers 281. The light blocking layer 282 blocks light from the adjacent light emitting elements 290 and suppresses color mixing between the adjacent light emitting elements 290. Here, light leakage can be suppressed by providing an end portion of the colored layer 281 so as to overlap the light shielding layer 282. As the light-blocking layer 282, a material that blocks light emitted from the light-emitting element 290 can be used. For example, a black matrix can be formed using a metal material or a resin material containing a pigment or a dye. Note that the light-blocking layer 282 is preferably provided in a region other than the display portion 562 such as the driver circuit 564 because unintended light leakage due to guided light or the like can be suppressed.

  The substrate 111 and the substrate 113 are bonded to each other with an adhesive layer 294.

  The conductive layer 565 is electrically connected to the FPC 285 through the conductive layer 255 and the connection body 242. The conductive layer 565 is preferably formed using the same material and step as the conductive layer included in the transistor. In this embodiment, an example in which the conductive layer 565 is formed using the same material and the same step as the conductive layer functioning as a source and a drain is described.

  As the connection body 242, various anisotropic conductive films (ACF: Anisotropic Conductive Film), anisotropic conductive paste (ACP: Anisotropic Conductive Paste), and the like can be used.

  FIG. 12 is a cross-sectional view of a light-emitting display panel to which the separate coating method is applied.

  The display panel illustrated in FIG. 12 is mainly different from the display panel illustrated in FIG. 11 in the configuration of the light-emitting element 290 and the configuration on the substrate 271 side.

  A light-emitting element 290 illustrated in FIG. 12 is an element in which an EL layer 292 is formed for each pixel. The EL layer 292 has a structure in which an end portion is covered with a common electrode 293 between two adjacent pixels. Note that FIG. 12 illustrates that all of the EL layers 292 are formed separately, but one or more of the layers other than the light emitting layer in the stacked structure constituting the EL layer 292 are formed separately. There may be no configuration.

  In addition, an insulating layer 219 is provided to cover the light-emitting element 290. The insulating layer 219 is a layer that functions as a barrier film that prevents moisture from entering the light-emitting element 290 and the like. It is preferable that the insulating layer 219 include at least one inorganic insulating film because the barrier property is improved. The insulating layer 219 preferably has a stacked structure of an organic insulating film and an inorganic insulating film. More specifically, it is preferable to have a stacked structure in which an organic insulating film, an inorganic insulating film, and an organic insulating film are sequentially stacked from the light-emitting element 290 side.

  The above is the description of the configuration example of the display panel.

[Appendix]
In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel formation region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and between the source and drain via the channel formation region. A current can flow. Note that in this specification and the like, a channel formation region refers to a region through which a current mainly flows.

  In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

  In addition, in this specification and the like, “electrically connected” includes a case of being connected via “thing having some electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. For example, “thing having some electric action” includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

  Further, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

  In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

  In this specification and the like, unless otherwise specified, off-state current refers to drain current when a transistor is off (also referred to as a non-conduction state or a cutoff state). The off state is a state where the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor unless otherwise specified. Is higher than the threshold voltage Vth.

  The off-state current of the transistor may depend on Vgs. Therefore, the off-state current of the transistor being I or less sometimes means that there exists a value of Vgs at which the off-state current of the transistor is I or less. The off-state current of a transistor may refer to an off-state current in an off state at a predetermined Vgs, an off state in a Vgs within a predetermined range, or an off state in Vgs at which a sufficiently reduced off current is obtained.

As an example, when the threshold voltage Vth is 0.5 V, the drain current when Vgs is 0.5 V is 1 × 10 ⁻⁹ A, and the drain current when Vgs is 0.1 V is 1 × 10 ⁻¹³ A. Assume that the n-channel transistor has a drain current of 1 × 10 ⁻¹⁹ A when Vgs is −0.5 V and a drain current of 1 × 10 ⁻²² A when Vgs is −0.8 V. Since the drain current of the transistor is 1 × 10 ⁻¹⁹ A or less when Vgs is −0.5 V or Vgs is in the range of −0.5 V to −0.8 V, the off-state current of the transistor is 1 It may be said that it is below ^x10 <^-19> A. Since there is Vgs at which the drain current of the transistor is 1 × 10 ⁻²² A or less, the off-state current of the transistor may be 1 × 10 ⁻²² A or less.

  In this specification and the like, the off-state current of a transistor having a channel width W may be represented by a current value flowing around the channel width W. In some cases, the current value flows around a predetermined channel width (for example, 1 μm). In the latter case, the unit of off-current may be represented by a unit having a dimension of current / length (for example, A / μm).

  The off-state current of a transistor may depend on temperature. In this specification, off-state current may represent off-state current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C. unless otherwise specified. Alternatively, at a temperature at which reliability of the semiconductor device or the like including the transistor is guaranteed, or a temperature at which the semiconductor device or the like including the transistor is used (for example, any one temperature of 5 ° C. to 35 ° C.). May represent off-state current. The off-state current of a transistor is I or less means that room temperature, 60 ° C., 85 ° C., 95 ° C., 125 ° C., a temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or the transistor is included. There may be a case where there is a value of Vgs at which the off-state current of the transistor is equal to or lower than I at a temperature at which the semiconductor device or the like is used (for example, any one temperature of 5 ° C. to 35 ° C.).

  The off-state current of the transistor may depend on the voltage Vds between the drain and the source. In this specification, the off-state current is Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V unless otherwise specified. Or an off-current at 20V. Alternatively, Vds in which reliability of a semiconductor device or the like including the transistor is guaranteed, or an off-current in Vds used in the semiconductor device or the like including the transistor may be represented. The off-state current of the transistor is equal to or less than I. Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V There is a value of Vgs at which the off-state current of the transistor is less than or equal to Vds at which Vds guarantees the reliability of the semiconductor device including the transistor or Vds used in the semiconductor device or the like including the transistor. May be pointed to.

  In the description of the off-state current, the drain may be read as the source. That is, the off-state current sometimes refers to a current that flows through the source when the transistor is off.

  In this specification and the like, the term “leakage current” may be used in the same meaning as off-state current. In this specification and the like, off-state current may refer to current that flows between a source and a drain when a transistor is off, for example.

In this specification and the like, the threshold voltage of a transistor refers to a gate voltage (Vg) when a channel is formed in the transistor. Specifically, the threshold voltage of a transistor is a maximum slope in a curve (Vg-√Id characteristic) in which the gate voltage (Vg) is plotted on the horizontal axis and the square root of the drain current (Id) is plotted on the vertical axis. In some cases, a gate voltage (Vg) at the intersection of a straight line obtained by extrapolating a certain tangent and the square root of the drain current (Id) is 0 (Id is 0 A) may be indicated. Alternatively, the threshold voltage of the transistor is a gate in which the channel length is L, the channel width is W, and the value of Id [A] × L [μm] / W [μm] is 1 × 10 ⁻⁹ [A]. It may refer to voltage (Vg).

  In this specification and the like, even when expressed as “semiconductor”, for example, when the conductivity is sufficiently low, the semiconductor device may have characteristics as an “insulator”. Further, the boundary between “semiconductor” and “insulator” is ambiguous, and there is a case where it cannot be strictly distinguished. Therefore, the “semiconductor” and the “insulator” described in this specification and the like can be interchangeable in some cases.

  In this specification and the like, even when expressed as “semiconductor”, for example, when the conductivity is sufficiently high, the semiconductor device may have characteristics as a “conductor”. Further, the boundary between the “semiconductor” and the “conductor” is ambiguous, and there are cases where it cannot be strictly distinguished. Therefore, the term “semiconductor” and “conductor” in this specification and the like can be interchangeable in some cases.

  In this specification and the like, the atomic ratio is In: Ga: Zn = 4: 2: 3 or the vicinity thereof, when the ratio of In to the total number of In, Ga and Zn atoms is 4. In addition, the Ga ratio is 1 or more and 3 or less, and the Zn ratio is 2 or more and 4 or less. Also, the atomic ratio is In: Ga: Zn = 5: 1: 6 or the vicinity thereof, when the ratio of In to the total number of In, Ga and Zn atoms is 5, the Ga ratio is It is greater than 0.1 and less than or equal to 2 and the Zn ratio is greater than or equal to 5 and less than or equal to 7. Also, the atomic ratio is In: Ga: Zn = 1: 1: 1 or the vicinity thereof, when the ratio of In to the total number of In, Ga and Zn atoms is 1, the Ga ratio is It is assumed that the ratio of Zn is greater than 0.1 and 2 or less, and the Zn ratio is greater than 0.1 and 2 or less.

  In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In the case of “OS FET”, it can be said to be a transistor including a metal oxide or an oxide semiconductor.

  In this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

  Further, in this specification and the like, there are cases where they are described as CAAC (c-axis aligned crystal) and CAC (Cloud-aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

  In this specification and the like, a CAC-OS or a CAC-metal oxide has a conductive function in part of a material and an insulating function in part of the material, and the whole material is a semiconductor. It has the function of. Note that in the case where a CAC-OS or a CAC-metal oxide is used for an active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is an electron serving as carriers. It is a function that does not flow. By performing the conductive function and the insulating function in a complementary manner, a switching function (function to turn on / off) can be given to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

  In this specification and the like, a CAC-OS or a CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

  In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

  Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

  That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

  An example of the crystal structure of the metal oxide will be described. Note that in the following, an example of a metal oxide formed by a sputtering method using an In—Ga—Zn oxide target (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) will be described. Will be described. A metal oxide formed by a sputtering method at a substrate temperature of 100 ° C. to 130 ° C. using the above target is called sIGZO, and the substrate temperature is set to room temperature (RT) using the above target. The metal oxide formed by the method is referred to as tIGZO. For example, sIGZO has a crystal structure of one or both of nc (nano crystal) and CAAC. TIGZO has an nc crystal structure. Note that the room temperature (RT) here includes a temperature when the substrate is not intentionally heated.

  The CAAC structure is one of crystal structures such as a thin film having a plurality of nanocrystals (a crystal region having a maximum diameter of less than 10 nm), and each nanocrystal has a c-axis oriented in a specific direction, and The a-axis and the b-axis are crystal structures having the characteristics that the nanocrystals are continuously connected without forming a grain boundary without having orientation. In particular, a thin film having a CAAC structure has a feature that the c-axis of each nanocrystal is easily oriented in the thickness direction of the thin film, the normal direction of the surface to be formed, or the normal direction of the surface of the thin film.

Here, in crystallography, it is common to take a unit cell having a specific axis as the c-axis among the three axes (crystal axis) of the a-axis, b-axis, and c-axis constituting the unit cell. . In particular, in a crystal having a layered structure, two axes parallel to the plane direction of the layer are generally defined as an a axis and a b axis, and an axis intersecting the layer is generally defined as a c axis. As a typical example of a crystal having such a layered structure, there is graphite classified as a hexagonal system, the a-axis and b-axis of the unit cell are parallel to the cleavage plane, and the c-axis is orthogonal to the cleavage plane. To do. For example, an InGaZnO ₄ crystal having a YbFe ₂ O ₄ type crystal structure can be classified into a hexagonal system, the a-axis and b-axis of the unit cell being parallel to the plane direction of the layer, and the c-axis being a layer (ie a-axis and b-axis).

  The structure example, the manufacturing method example, the drawings corresponding to the structure example, and the like exemplified in this embodiment can be implemented in appropriate combination with at least part of the structure example, the manufacturing method example, the drawing, or the like.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 2)
In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

The electronic device of this embodiment includes the display panel or the display device of one embodiment of the present invention. Thereby, the display part of an electronic device can display a high quality image | video.

For example, full high vision, 2K, 4K, 8K, 16K, or higher resolution video can be displayed on the display unit of the electronic device of this embodiment. Further, the screen size of the display unit can be 20 inches or more diagonal, 30 inches or more, 50 inches or more, 60 inches or more, or 70 inches or more.

Examples of electronic devices include relatively large screens such as television devices, desktop or notebook personal computers, monitors for computers, digital signage (digital signage), and large game machines such as pachinko machines. In addition to the electronic devices provided, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, a sound reproduction device, and the like can be given.

The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal with an antenna, video, information, and the like can be displayed on the display unit. In the case where the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

The electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared).

The electronic device of one embodiment of the present invention can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for executing various software (programs), and wireless communication A function, a function of reading a program or data recorded on a recording medium, and the like can be provided.

FIG. 13A illustrates an example of a television device. In the television device 7100, a display portion 7000 is incorporated in a housing 7101. Here, a structure in which the housing 7101 is supported by a stand 7103 is shown.

The display device of one embodiment of the present invention can be applied to the display portion 7000.

The television device 7100 illustrated in FIG. 13A can be operated with an operation switch included in the housing 7101 or a separate remote controller 7111. Alternatively, the display unit 7000 may be provided with a touch sensor, and may be operated by touching the display unit 7000 with a finger or the like. The remote controller 7111 may include a display unit that displays information output from the remote controller 7111. Channels and volume can be operated with an operation key or a touch panel included in the remote controller 7111, and an image displayed on the display portion 7000 can be operated.

Note that the television device 7100 is provided with a receiver, a modem, and the like. A general television broadcast can be received by the receiver. In addition, by connecting to a wired or wireless communication network via a modem, information communication is performed in one direction (from the sender to the receiver) or in two directions (between the sender and the receiver or between the receivers). It is also possible.

FIG. 13B illustrates an example of a laptop personal computer. A laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7000 is incorporated in the housing 7211.

The display device of one embodiment of the present invention can be applied to the display portion 7000.

FIGS. 13C and 13D show examples of digital signage.

A digital signage 7300 illustrated in FIG. 13C includes a housing 7301, a display portion 7000, a speaker 7303, and the like. Furthermore, an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be provided.

FIG. 13D illustrates a digital signage 7400 attached to a columnar column 7401. The digital signage 7400 includes a display portion 7000 provided along the curved surface of the column 7401.

13C and 13D, the display device of one embodiment of the present invention can be applied to the display portion 7000.

The wider the display unit 7000, the more information can be provided at one time. In addition, the wider the display unit 7000, the more easily noticeable to the human eye. For example, the advertising effect can be enhanced.

By applying a touch panel to the display unit 7000, not only a still image or a moving image is displayed on the display unit 7000, but also a user can operate intuitively, which is preferable. In addition, when it is used for providing information such as route information or traffic information, usability can be improved by an intuitive operation.

In addition, as shown in FIGS. 13C and 13D, the digital signage 7300 or the digital signage 7400 can be linked with an information terminal 7311 such as a smartphone possessed by the user or the information terminal 7411 by wireless communication. Is preferred. For example, advertisement information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Further, the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.

Further, the digital signage 7300 or the digital signage 7400 can execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). As a result, an unspecified number of users can participate and enjoy the game at the same time.

The display system of one embodiment of the present invention can be incorporated along a curved surface of an inner wall or an outer wall of a house or a building, or an interior or exterior of a vehicle.

Examples of mounting the display system of one embodiment of the present invention on a vehicle will be described with reference to FIGS.

FIG. 14A shows an example of the appearance of a vehicle 5000. The vehicle 5000 includes a plurality of cameras 5005 (in FIG. 14A, a camera 5005a, a camera 5005b, a camera 5005c, a camera 5005d, a camera 5005d, a camera 5005e, and a camera 5005f). For example, the camera 5005a has a function of imaging the front situation, the camera 5005b has a function of imaging the rear situation, the camera 5005c has a function of imaging the right front situation, and the camera 5005d. Has a function of imaging the situation on the left front, the camera 5005e has a function of imaging the situation on the right rear, and the camera 5005f has a function of imaging the situation on the left rear. However, the number and function of the cameras that capture the periphery of the vehicle are not limited to the above configuration. For example, a camera for imaging the rear of the vehicle may be provided in front of the vehicle.

FIG. 14B illustrates an example of a vehicle 5000 interior. The vehicle 5000 includes a display portion 5001, a display panel 5008a, a display panel 5008b, and a display panel 5009. The display portion of the display system of one embodiment of the present invention can be used for one or more of the display portion 5001, the display panel 5008a, the display panel 5008b, and the display panel 5009. Note that FIG. 14B illustrates an example in which the display portion 5001 is mounted on a right-hand drive vehicle, but there is no particular limitation, and the display portion 5001 can also be mounted on a left-hand drive vehicle. In this case, the left and right arrangements of the configuration shown in FIG.

FIG. 14B shows a dashboard 5002, a handle 5003, a windshield 5004, and the like arranged around the driver's seat and the passenger seat. The display unit 5001 is disposed at a predetermined position on the dashboard 5002, specifically around the driver, and has a substantially T-shape. FIG. 14B illustrates an example in which one display portion 5001 formed using a plurality of display panels 5007 (display panels 5007a, 5007b, 5007c, and 5007d) is provided along the dashboard 5002. However, the display unit 5001 may be divided into a plurality of locations.

Note that the plurality of display panels 5007 may have flexibility. In this case, the display portion 5001 can be processed into a complicated shape, and the display portion 5001 is displayed along a curved surface such as the dashboard 5002 or displayed on a connection portion of a handle, a display portion of an instrument, an air outlet 5006, or the like. A configuration in which the display area of the portion 5001 is not provided can be easily realized.

The display panels 5008a and 5008b are respectively provided in the pillar portion. By displaying the image from the imaging means (for example, the camera 5005 shown in FIG. 14A) provided on the vehicle body on the display panels 5008a and 5008b, the field of view blocked by the pillar can be complemented. For example, an image captured by the camera 5005d can be displayed on the display panel 5008a as an image 5008c. Similarly, it is preferable to display an image captured by the camera 5005c on the display panel 5008b.

The display panel 5009 may have a function of displaying an image from a rear imaging unit (for example, the camera 5005b).

In addition, the display panels 5007, 5008a, 5008b, and 5009 may have a function of displaying legal speed, traffic information, and the like.

Each of the display panels 5008a and 5008b preferably has flexibility. Accordingly, it is easy to provide the display panels 5008a and 5008b along the curved surface of the pillar portion.

In addition, when viewing the display panel provided on the curved surface from the driver's seat, there is a possibility that the image may appear distorted. Therefore, the display panel preferably has a function of displaying an image that has been corrected so as to reduce image distortion. Image processing using a neural network is suitable for correcting the image.

14A and 14B show an example in which the cameras 5005c and 5005d are installed instead of the side mirrors, both the side mirrors and the cameras may be installed.

As the camera 5005, a CCD camera, a CMOS camera, or the like can be used. In addition to these cameras, an infrared camera may be used in combination. Since the infrared camera has a higher output level as the temperature of the subject increases, it can detect or extract a living body such as a person or an animal.

Images captured by the camera 5005 can be output to any one or more of the display panel 5007, the display panel 5008a, the display panel 5008b, and the display panel 5009, respectively. The display unit 5001, the display panel 5008a, the display panel 5008b, and the display panel 5009 are used to mainly support driving of the vehicle. The camera 5005 captures a situation around the vehicle with a wide angle of view, and displays the image on the display panel 5007, the display panel 5008a, the display panel 5008b, and the display panel 5009, so that the driver's blind spot area can be visually recognized. Thus, the occurrence of an accident can be prevented.

In addition, by using the display system of one embodiment of the present invention, video discontinuity at a joint of the display panels 5007a, 5007b, 5007c, and 5007d can be corrected. Accordingly, it is possible to display an image in which the joints are not conspicuous, and the visibility of the display unit 5001 during driving can be improved.

Further, a distance image sensor may be provided on the roof of a car, and an image obtained by the distance image sensor may be displayed on the display unit 5001. As the distance image sensor, an image sensor, a rider (LIDAR: Light Detection and Ranging), or the like can be used. By displaying the image obtained by the image sensor and the image obtained by the distance image sensor on the display unit 5001, more information can be provided to the driver and driving can be supported.

In addition, the display portion 5001 may have a function of displaying map information, traffic information, television video, DVD video, and the like. For example, the map information can be displayed in a large size using the display panels 5007a, 5007b, 5007c, and 5007d as one display screen. Note that the number of display panels 5007 can be increased in accordance with displayed images.

The images displayed on the display panels 5007a, 5007b, 5007c, and 5007d can be freely set according to the driver's preference. For example, a TV image and a DVD image are displayed on the left display panel 5007d, map information is displayed on the central display panel 5007b, instruments are displayed on the right display panel 5007c, and audio is displayed in the vicinity of the transmission gear. Display on the display panel 5007a (between the seat and the passenger seat). Further, by combining a plurality of display panels 5007, a fail-safe function can be added to the display portion 5001. For example, even if a certain display panel 5007 breaks down for some reason, the display area can be changed and display can be performed using another display panel 5007.

The windshield 5004 includes a display panel 5004a. The display panel 5004a has a function of transmitting visible light. The driver can visually recognize the background through the display panel 5004a. Note that the display panel 5004a has a function of performing display or the like for alerting the driver. 14B illustrates the structure in which the display panel 5004a is provided on the windshield 5004, the present invention is not limited to this. For example, the windshield 5004 may be replaced with the display panel 5004a.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 3)
In this embodiment, an example of a television device to which a display device including the semiconductor device of one embodiment of the present invention can be applied will be described with reference to drawings.

  FIG. 15A shows a block diagram of the television device 600.

  In the drawings attached to the present specification, the components are classified by function and the block diagram is shown as an independent block. However, it is difficult to completely separate actual components by function. A component may be involved in multiple functions.

  The television apparatus 600 includes a control unit 601, a storage unit 602, a communication control unit 603, an image processing circuit 604, a decoder circuit 605, a video signal receiving unit 606, a timing controller 607, a source driver 608, a gate driver 609, a display panel 620, and the like. Have

  The display device described as an example in the above embodiment can be applied to the display panel 620 in FIG. Accordingly, the television device 600 having a large size and high resolution and excellent visibility can be realized.

  The control unit 601 can function as, for example, a central processing unit (CPU). For example, the control unit 601 has a function of controlling components such as the storage unit 602, the communication control unit 603, the image processing circuit 604, the decoder circuit 605, and the video signal receiving unit 606 via the system bus 630.

  A signal is transmitted between the control unit 601 and each component via the system bus 630. In addition, the control unit 601 has a function of processing a signal input from each component connected via the system bus 630, a function of generating a signal output to each component, and the like, thereby being connected to the system bus 630. Each component can be controlled centrally.

  The storage unit 602 functions as a register, a cache memory, a main memory, a secondary memory, or the like that can be accessed by the control unit 601 and the image processing circuit 604.

  As a storage device that can be used as the secondary memory, for example, a storage device to which a rewritable nonvolatile storage element is applied can be used. For example, a flash memory, an MRAM (Magnetostatic Random Access Memory), a PRAM (Phase change RAM), a ReRAM (Resistive RAM), an FeRAM (Ferroelectric RAM), or the like can be used.

  In addition, as a storage device that can be used as a temporary memory such as a register, a cache memory, or a main memory, a volatile storage element such as a DRAM (Dynamic RAM) or an SRAM (Static Random Access Memory) may be used.

  For example, as a RAM provided in the main memory, for example, a DRAM is used, and a memory space is virtually allocated and used as a work space of the control unit 601. The operating system, application program, program module, program data, etc. stored in the storage unit 602 are loaded into the RAM for execution. These data, programs, and program modules loaded in the RAM are directly accessed and operated by the control unit 601.

  On the other hand, the ROM can store BIOS (Basic Input / Output System), firmware and the like that do not require rewriting. As the ROM, a mask ROM, an OTPROM (One Time Programmable Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), or the like can be used. Examples of EPROM include UV-EPROM (Ultra-Violet Erasable Programmable Read Only Memory) and EEPROM (Electrically Erasable Programmable Read Only Memory) capable of erasing stored data by ultraviolet irradiation.

  In addition to the storage unit 602, a removable storage device may be connected. For example, it has a terminal for connecting to a recording medium drive such as a hard disk drive (HDD) or a solid state drive (SSD) that functions as a storage device, a recording medium such as a flash memory, a Blu-ray disc, or a DVD. Is preferred. Thereby, a video can be recorded.

  The communication control unit 603 has a function of controlling communication performed via a computer network. For example, the control signal for connecting to the computer network is controlled in accordance with a command from the control unit 601, and the signal is transmitted to the computer network. As a result, the Internet, intranet, extranet, PAN (Personal Area Network), LAN (Local Area Network), CAN (Camper Area Network, and MAN (MetroApolNetwork), which are the foundations of the World Wide Web (WWW). Communication can be performed by connecting to a computer network such as Wide Area Network (GA) or GAN (Global Area Network).

  The communication control unit 603 has a function of communicating with a computer network or other electronic devices using a communication standard such as Wi-Fi (registered trademark), Bluetooth (registered trademark), or ZigBee (registered trademark). Also good.

  The communication control unit 603 may have a function of communicating wirelessly. For example, an antenna and a high frequency circuit (RF circuit) may be provided to transmit and receive an RF signal. The high-frequency circuit is a circuit for mutually converting an electromagnetic signal and an electric signal in a frequency band determined by the legislation of each country and performing communication with other communication devices wirelessly using the electromagnetic signal. Several tens of kHz to several tens of GHz is generally used as a practical frequency band. The high-frequency circuit connected to the antenna includes a high-frequency circuit unit corresponding to a plurality of frequency bands, and the high-frequency circuit unit includes an amplifier (amplifier), a mixer, a filter, a DSP, an RF transceiver, and the like. it can.

  The video signal receiving unit 606 includes, for example, an antenna, a demodulation circuit, an A / D conversion circuit (analog-digital conversion circuit), and the like. The demodulation circuit has a function of demodulating a signal input from the antenna. The A-D conversion circuit has a function of converting the demodulated analog signal into a digital signal. The signal processed by the video signal receiving unit 606 is sent to the decoder circuit 605.

  The decoder circuit 605 has a function of decoding video data included in a digital signal input from the video signal receiving unit 606 in accordance with the specification of a broadcast standard to be transmitted, and generating a signal to be transmitted to the image processing circuit. For example, as a broadcasting standard in 8K broadcasting, H.264 265 | MPEG-H High Efficiency Video Coding (abbreviation: HEVC).

  Examples of broadcast radio waves that can be received by the antenna included in the video signal receiving unit 606 include ground waves or radio waves transmitted from satellites. Broadcast radio waves that can be received by an antenna include analog broadcast and digital broadcast, and also includes video and audio, or audio-only broadcast. For example, broadcast radio waves transmitted in a specific frequency band in the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz) can be received. In addition, for example, by using a plurality of data received in a plurality of frequency bands, the transfer rate can be increased and more information can be obtained. Accordingly, an image having a resolution exceeding full high-definition can be displayed on the display panel 620. For example, an image having a resolution of 4K2K, 8K4K, 16K8K, or higher can be displayed.

  Further, the video signal receiving unit 606 and the decoder circuit 605 may be configured to generate a signal to be transmitted to the image processing circuit 604 using broadcast data transmitted by a data transmission technique via a computer network. At this time, when the signal to be received is a digital signal, the video signal receiving unit 606 may not include a demodulation circuit, an A-D conversion circuit, and the like.

  The image processing circuit 604 has a function of generating a video signal to be output to the timing controller 607 based on the video signal input from the decoder circuit 605.

  The timing controller 607 also outputs a signal (a signal such as a clock signal or a start pulse signal) to be output to the gate driver 609 and the source driver 608 based on a synchronization signal included in the video signal or the like processed by the image processing circuit 604. It has a function to generate. The timing controller 607 has a function of generating a video signal to be output to the source driver 608 in addition to the above signals.

  The display panel 620 includes a plurality of pixels 621. Each pixel 621 is driven by signals supplied from the gate driver 609 and the source driver 608. Here, an example of a display panel having a resolution according to the 8K4K standard having the number of pixels of 7680 × 4320 is shown. Note that the resolution of the display panel 620 is not limited to this, and may be a resolution according to a standard such as full high-definition (pixel number 1920 × 1080) or 4K2K (pixel number 3840 × 2160).

  As the control unit 601 and the image processing circuit 604 illustrated in FIG. 15A, for example, a structure including a processor can be employed. For example, the control unit 601 can use a processor that functions as a central processing unit (CPU). Further, as the image processing circuit 604, for example, other processors such as a DSP (Digital Signal Processor) and a GPU (Graphics Processing Unit) can be used. In addition, the control unit 601 and the image processing circuit 604 may have a configuration in which the processor is realized by a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array).

  The processor performs various data processing and program control by interpreting and executing instructions from various programs. The program that can be executed by the processor may be stored in a memory area of the processor, or may be stored in a storage device provided separately.

  In addition, two or more functions among the functions of the control unit 601, the storage unit 602, the communication control unit 603, the image processing circuit 604, the decoder circuit 605, the video signal receiving unit 606, and the timing controller 607 are provided. A system LSI may be configured by concentrating on one IC chip. For example, a system LSI including a processor, a decoder circuit, a tuner circuit, an A / D conversion circuit, a DRAM, and an SRAM may be used.

  Note that a transistor in which an oxide semiconductor is used for a channel formation region and an extremely low off-state current is realized can be used for the controller 601, an IC included in another component, or the like. Since the transistor has extremely low off-state current, the use of the transistor as a switch for holding charge (data) flowing into the capacitor functioning as a memory element can ensure a data holding period for a long time. it can. By using this characteristic for a register such as the control unit 601 or a cache memory, the control unit 601 is operated only when necessary, and in other cases, information on the immediately preceding process is saved in the storage element, so that it is normally. Off-computing becomes possible. Thereby, the power consumption of the television apparatus 600 can be reduced.

  Note that the structure of the television device 600 illustrated in FIG. 15A is an example, and it is not necessary to include all of the components. The television device 600 only needs to include necessary components from among the components illustrated in FIG. In addition, the television device 600 may include a component other than the components illustrated in FIG.

  For example, the television device 600 may include an external interface, an audio output unit, a touch panel unit, a sensor unit, a camera unit, and the like in addition to the configuration illustrated in FIG. For example, as an external interface, for example, a USB (Universal Serial Bus) terminal, a LAN (Local Area Network) connection terminal, a power receiving terminal, an audio output terminal, an audio input terminal, an image output terminal, an image input terminal, etc. External connection terminals, transceivers for optical communication using infrared rays, visible light, ultraviolet rays, etc., physical buttons provided on the housing, and the like. For example, the sound input / output unit includes a sound controller, a microphone, a speaker, and the like.

  Hereinafter, the image processing circuit 604 will be described in more detail.

  The image processing circuit 604 preferably has a function of executing image processing based on the video signal input from the decoder circuit 605.

  Examples of image processing include noise removal processing, gradation conversion processing, color tone correction processing, and luminance correction processing. Examples of color tone correction processing and luminance adjustment processing include gamma correction.

  The image processing circuit 604 preferably has a function of executing processing such as inter-pixel interpolation processing associated with resolution up-conversion and inter-frame interpolation processing associated with frame frequency up-conversion.

  For example, as noise removal processing, various noises such as mosquito noise generated around the outline of characters, block noise generated in high-speed moving images, flickering random noise, and dot noise generated by resolution up-conversion are removed.

  The gradation conversion process is a process for converting the gradation of an image into a gradation corresponding to the output characteristics of the display panel 620. For example, when the number of gradations is increased, a process for smoothing the histogram can be performed by interpolating and assigning gradation values corresponding to each pixel to an image input with a small number of gradations. Further, the dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.

  The inter-pixel interpolation process interpolates data that does not originally exist when the resolution is up-converted. For example, referring to pixels around the target pixel, the data is interpolated so as to display the intermediate colors.

  The color tone correction process is a process for correcting the color tone of an image. The brightness correction process is a process for correcting the brightness (brightness contrast) of the image. For example, the type, brightness, or color purity of the illumination arranged in the space where the television apparatus 600 is provided is detected, and the brightness and color tone of the image displayed on the display panel 620 are corrected accordingly. . Or, it has a function to compare the image to be displayed with the images of various scenes in the image list stored in advance, and to correct the image displayed with brightness and color tone suitable for the image of the closest scene. May be.

  Interframe interpolation generates an image of a frame (interpolation frame) that does not originally exist when the frame frequency of a video to be displayed is increased. For example, an interpolation frame image to be inserted between two images is generated from the difference between two images. Alternatively, an image of a plurality of interpolation frames can be generated between two images. For example, when the frame frequency of the video signal input from the decoder circuit 605 is 60 Hz, the frame frequency of the video signal output to the timing controller 607 is doubled by 120 Hz by generating a plurality of interpolation frames, or It can be increased to 4 times 240 Hz or 8 times 480 Hz.

  The image processing circuit 604 preferably has a function of executing image processing using a neural network. FIG. 15A illustrates an example in which the image processing circuit 604 includes a neural network 610.

  For example, the neural network 610 can perform feature extraction from image data included in a video, for example. The image processing circuit 604 can select an optimal correction method according to the extracted features, or can select parameters used for correction.

  Alternatively, the neural network 610 itself may have a function of performing image processing. That is, the image data that has been subjected to image processing may be output by inputting the image data before being subjected to image processing to the neural network 610.

  In addition, weight coefficient data used for the neural network 610 is stored in the storage unit 602 as a data table. The data table including the weighting coefficient can be updated to the latest one via the computer network by the communication control unit 603, for example. Alternatively, the image processing circuit 604 may have a learning function so that a data table including a weighting factor can be updated.

  FIG. 15B shows a schematic diagram of a neural network 610 included in the image processing circuit 604.

  In this specification and the like, a neural network refers to a general model that imitates a biological neural network, determines the connection strength between neurons by learning, and has problem solving ability. The neural network has an input layer, an intermediate layer (also referred to as a hidden layer), and an output layer. A neural network having two or more intermediate layers is called deep learning (or deep neural network (DNN)).

  In this specification and the like, when describing a neural network, determining the connection strength (also referred to as a weighting factor) between neurons from existing information may be referred to as “learning”. Further, in this specification and the like, there is a case where “inference” refers to constructing a neural network using the connection strength obtained by learning and deriving a new conclusion therefrom.

  The neural network 610 includes an input layer 611, one or more intermediate layers 612, and an output layer 613. Input data is input to the input layer 611. Output data is output from the output layer 613.

  The input layer 611, the intermediate layer 612, and the output layer 613 each have a neuron 615. Here, the neuron 615 indicates a circuit element (product-sum operation element) capable of realizing product-sum operation. In FIG. 15, the input / output direction of data between two neurons 615 included in two layers is indicated by arrows.

Arithmetic processing in each layer is executed by a product-sum operation between the output of the neuron 615 included in the previous layer and the weight coefficient. For example, if the output of the i-th neuron in the input layer is x _i and the connection strength (weight coefficient) between the output x _i and the j-th neuron in the next intermediate layer 612 is w _ji , The output y _j of the j-th neuron is y _j = f (Σw _ji · x _i ). Note that i and j are integers of 1 or more. Here, f (x) is an activation function, and a sigmoid function, a threshold function, or the like can be used. Similarly, the output of the neuron 615 of each layer is a value obtained by calculating the activation function on the product-sum operation result of the output of the neuron 615 of the previous layer and the weight coefficient. The connection between layers may be a total connection in which all neurons are connected, or a partial connection in which some neurons are connected. FIG. 15B shows the case of full coupling.

  FIG. 15B illustrates an example having three intermediate layers 612. Note that the number of the intermediate layers 612 is not limited to this, and it is only necessary to include one or more intermediate layers. In addition, the number of neurons included in one intermediate layer 612 may be changed as appropriate according to specifications. For example, the number of neurons 615 included in one intermediate layer 612 may be larger or smaller than the number of neurons 615 included in the input layer 611 or the output layer 613.

  A weighting factor that is an index of the strength of connection between the neurons 615 is determined by learning. The learning may be executed by a processor included in the television apparatus 600, but is preferably executed by a computer having an excellent arithmetic processing capability such as a dedicated server or a cloud. The weighting coefficient determined by learning is stored in the storage unit 602 as a table and is used by being read out by the image processing circuit 604. The table can be updated via a computer network as necessary.

  This completes the description of the neural network.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

10 display panel 10a display panel 10b display panel 10c display panel 10d display panel 11 display unit 11a display unit 11b display unit 11c display unit 11d display unit 12 drive circuit 12a drive circuit 12b drive circuit 13 drive circuit 14 region 14b region 14c region 14d region 15 Terminal portion 15a Terminal portion 20 Display device 21 FPC
21a FPC
21b FPC
25 display area 31 shift register circuit 32 latch circuit 33 latch circuit 34 level shifter circuit 35 DAC circuit 36 analog buffer circuit 37 source follower circuit 38 sampling circuit 41 latch circuit unit 42 level shifter circuit unit 43 DA conversion unit 44 analog buffer circuit unit 45 Source follower circuit section 46 Demultiplexer circuit 51 Transistor 52 Transistor 53 Capacitor element 54 Light emitting element 100 Transistor 100A Transistor 100B Transistor 100C Transistor 100D Transistor 102 Substrate 104 Insulating layer 106 Conductive layer 108 Semiconductor layer 108f Metal oxide film 108i Region 108n Region 109 Conductive Layer 110 insulating layer 110f insulating film 110g insulating film 110h insulating film 111 substrate 112 conductive layer 112f conductive film 1 3 Substrate 114 Metal oxide layer 114f Metal oxide film 116 First layer 116a First layer 117 Metal oxide layer 118 Insulating layer 119 Insulating layer 120a Conductive layer 120b Conductive layer 141a Opening 141b Opening 141c Opening 142 Opening Part 151 resist mask 201a transistor 201b transistor 201ba transistor 210 insulating layer 210a insulating layer 210b insulating layer 211 insulating layer 212 insulating layer 213 insulating layer 215 insulating layer 216 insulating layer 219 insulating layer 222b conductive layer 242 connector 251 transistor 255 conductive layer 261 substrate 262 Adhesive layer 263 Insulating layer 271 Substrate 272 Adhesive layer 273 Insulating layer 281 Colored layer 282 Light shielding layer 285 FPC
290 Light emitting element 291 Pixel electrode 292 EL layer 293 Common electrode 294 Adhesive layer 560 Region 562 Display unit 564 Drive circuit 565 Conductive layer 600 Television apparatus 601 Control unit 602 Storage unit 603 Communication control unit 604 Image processing circuit 605 Decoder circuit 606 Video signal Reception unit 607 Timing controller 608 Source driver 609 Gate driver 610 Neural network 611 Input layer 612 Intermediate layer 613 Output layer 615 Neuron 620 Display panel 621 Pixel 630 System bus 5000 Vehicle 5001 Display unit 5002 Dashboard 5003 Handle 5004 Windshield 5004a Display panel 5005 Camera 5005a Camera 5005b Camera 5005c Camera 5005d Camera 5005e Camera 5005f Camera 5006 Air outlet 5007 Display panel 5007a Display panel 5007b Display panel 5007c Display panel 5007d Display panel 5008a Display panel 5008b Display panel 5008c Video 5009 Display panel 7000 Display unit 7100 Television device 7101 Housing 7103 Stand 7111 Remote control device 7200 Notebook personal computer 7211 Case 7212 Keyboard 7213 Pointing device 7214 External connection port 7300 Digital signage 7301 Case 7303 Speaker 7311 Information terminal 7400 Digital signage 7401 Pillar 7411 Information terminal

Claims (5)

A display panel having a display unit, a first circuit unit, a second circuit unit, and a first region,
The display unit includes a plurality of pixels,
The first circuit unit and the second circuit unit are respectively provided along the outline of the display unit,
The first region includes a portion provided at a position facing the first circuit portion with the display portion interposed therebetween, and a portion provided at a position facing the second circuit portion sandwiching the display portion. Have
The first region has a function of transmitting visible light;
The first circuit portion has a function of outputting a gradation signal to the plurality of pixels,
The second circuit unit has a function of outputting a signal for selecting the plurality of pixels,
The first circuit unit includes a first transistor,
The first transistor has a first semiconductor layer, a first gate electrode, and a first gate insulating layer,
The second circuit unit includes a second transistor,
The second transistor has a second semiconductor layer, a second gate electrode, and a second gate insulating layer,
The first gate insulating layer is thinner than the second gate insulating layer,
Display panel. In claim 1,
The width of the first gate electrode in the channel length direction is smaller than that of the second gate electrode,
Display panel. In claim 1 or claim 2,
The first semiconductor layer and the second semiconductor layer each include a metal oxide,
Display panel. A display device having a first display panel and a second display panel,
The first display panel and the second display panel are display panels according to any one of claims 1 to 3, respectively.
The first region of the first display panel has a portion that overlaps with the display unit of the second display panel and transmits light emitted from the display unit of the second display panel.
Display device. In claim 4,
The first circuit portion or the second circuit portion of the second display panel has a portion that overlaps the display portion of the first display panel.
Display device.

Images