JP2019028043A - Voltage abnormality detector - Google Patents

Abstract

A voltage abnormality detection device capable of accurately detecting a power supply abnormality is provided. A voltage abnormality detection device detects an abnormality of an AC voltage. The voltage abnormality detection device includes a reference circuit that divides an AC voltage into a plurality of phases, and a storage unit that stores a table in which reference information defined for each frequency is associated with each circuit configuration connected to a signal line of the AC voltage. . The FPGA receives an instruction capable of specifying a circuit configuration, and determines reference information for each frequency corresponding to the circuit configuration specified by the received instruction (S11). The FPGA specifies the frequency of each of the divided phases (S17). The FPGA specifies reference information corresponding to the specified frequency (S19). The FPGA determines whether there is an abnormality in the AC voltage according to the relationship between the specified reference information and the AC voltage (S23, S25). [Selection diagram] FIG.

Description

  The present invention relates to a voltage abnormality detection device.

  Patent Document 1 discloses a voltage abnormality detection device that detects an abnormality in a three-phase AC voltage. The voltage abnormality detection device detects the duty ratio for each of the R phase, S phase, and T phase of the three-phase AC voltage. The voltage abnormality detection device compares the detected duty ratio with a predetermined threshold value and determines whether an overvoltage or a voltage drop has occurred. The voltage abnormality detection device displays the determination result on the display device.

Japanese Patent No. 6070139

  Due to the influence of the low-pass filter and the bypass capacitor provided on the signal line of the three-phase AC voltage, the duty ratio varies according to the variation of the frequency of the three-phase AC voltage. Therefore, the voltage abnormality detection device has a problem that when the duty ratio is determined with a common threshold regardless of the fluctuation of the frequency, the occurrence of an overvoltage or a voltage drop cannot be accurately determined.

  An object of the present invention is to provide a voltage abnormality detection device that can accurately detect a power supply abnormality.

  The voltage abnormality detection device according to the present invention is a voltage abnormality detection device that detects an abnormality of an alternating voltage, the voltage dividing means for dividing the alternating voltage into a plurality of phases, and the reference information defined for each frequency, A storage unit storing a table associated with each circuit configuration connected to the signal line of the AC voltage, and an instruction that can specify the circuit configuration, and each frequency corresponding to the circuit configuration specified by the received instruction Determining means for determining the reference information, first specifying means for specifying each frequency of the plurality of phases divided by the voltage dividing means, and the frequency corresponding to the frequency specified by the first specifying means A second specifying unit that specifies reference information based on the reference information for each frequency determined by the determining unit, and a relationship between the reference information specified by the second specifying unit and the AC voltage. In response, characterized by comprising a whether determination means wherein there is an abnormality in the alternating voltage.

  The voltage abnormality detection device stores reference information corresponding to the circuit configuration connected to the AC voltage signal line in a table in association with the frequency and stores the reference information in a storage unit. The voltage abnormality detection device specifies the frequency of each phase of the AC voltage and specifies the corresponding reference information based on the table. The voltage abnormality detection device determines whether there is an abnormality in the AC voltage according to the relationship between the specified reference information and the AC voltage. At this time, the voltage abnormality detection device determines whether there is an abnormality in the AC voltage based on the reference information corresponding to the changed frequency even when the frequency of the AC voltage varies according to the circuit configuration connected to the signal line. it can. Therefore, the voltage abnormality detection device can accurately detect whether there is an abnormality in the AC voltage.

  In the present invention, the AC voltage may be a three-phase AC voltage, and the voltage dividing unit may divide the three-phase AC voltage into an R phase, an S phase, and a T phase. At this time, the voltage abnormality detection device can accurately determine whether there is an abnormality in the three-phase AC voltage based on the AC voltages of the R phase, the S phase, and the T phase.

  In the present invention, when the duty ratio of two or more phases of the R phase, S phase, and T phase divided by the voltage dividing unit is larger than the first threshold value indicated by the reference information, the determination unit determines the AC voltage. It may be determined that there is an abnormality. At this time, the voltage abnormality detection device can accurately determine the overvoltage of the AC voltage.

  In the present invention, the determination means repeatedly compares the duty ratios of the R phase, S phase, and T phase divided by the voltage dividing means with the first threshold indicated by the reference information, When the duty ratio of any one of the phase and the T phase is continuously greater than the first threshold by a predetermined number of times, it may be determined that the AC voltage is abnormal. At this time, the voltage abnormality detection device can accurately determine the overvoltage of the AC voltage.

  In the present invention, a pulse output that outputs a pulse signal when the potential difference between the other two phases of the R phase, S phase, and T phase divided by the voltage dividing means is greater than or equal to a predetermined voltage. And the determination means is configured to prevent the pulse output means from outputting a pulse signal of two or more phases among the pulse signals corresponding to the R phase, S phase, and T phase divided by the voltage dividing means for a predetermined time or more. It may be determined that the AC voltage is abnormal. At this time, the voltage abnormality detection device can accurately determine the voltage drop of the AC voltage.

  In the present invention, the determination unit repeatedly compares the duty ratios of the R phase, S phase, and T phase divided by the voltage dividing unit with the second threshold value indicated by the reference information, When the duty ratio of the phase and the T phase is continuously smaller than the second threshold by a predetermined number of times, it may be determined that the AC voltage is abnormal. At this time, the voltage abnormality detection device can accurately determine the voltage drop of the AC voltage.

  In the present invention, the predetermined number of times may differ depending on the frequency specified by the first specifying means. At this time, the voltage abnormality detection device can equalize the time until the determination of whether there is an abnormality in the AC voltage is completed.

  In the present invention, a result output means for outputting a determination result by the determination means may be further provided. At this time, the voltage abnormality detection device can notify the outside of the occurrence of the voltage abnormality.

1 is a block diagram showing an electrical configuration of a numerical control device 1 and a machine tool 2. FIG. The circuit diagram of the voltage abnormality detection circuit 15. FIG. The pulse conceptual diagram when using RST phase as each reference phase, and the voltage waveform diagram of a three-phase input. The figure which shows the threshold value table 14A. The flowchart of the main process. Explanatory drawing of a pulse period and a pulse width. The flowchart of a 1st determination process. The flowchart of a 2nd determination process.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. A numerical control device 1 shown in FIG. 1 is an example of a voltage abnormality detection device of the present invention. The numerical control device 1 controls the machine tool 2 to cut a workpiece held on the upper surface of a table (not shown).

<Overview of machine tool 2>
The configuration of the machine tool 2 will be briefly described with reference to FIG. The left-right direction, the front-rear direction, and the vertical direction of the machine tool 2 are an X-axis direction, a Y-axis direction, and a Z-axis direction, respectively. The machine tool 2 includes a spindle mechanism, a spindle moving mechanism, a tool changer, and the like (not shown). The spindle mechanism includes a spindle motor 32 and rotates the spindle on which a tool is mounted. The main shaft moving mechanism includes a Z-axis motor 31, an X-axis motor 33, and a Y-axis motor 34, and moves the main shaft in each of the XYZ directions relative to the workpiece supported on the table upper surface.

  The tool changer includes a magazine motor 35, drives a tool magazine (not shown) that holds a plurality of tools, and exchanges a tool mounted on the spindle with another tool. The machine tool 2 further includes an operation panel (not shown). The operation panel includes an input device 17 and a display device 18. The input device 17 is a device for performing various inputs and settings. In addition to various display screens and setting screens, the display device 18 displays notification information and the like described later. The notification information includes an overvoltage or voltage drop state. The input device 17 and the display device 18 are connected to the input / output unit 16 of the numerical controller 1.

  The Z-axis motor 31 includes an encoder 41. The spindle motor 32 includes an encoder 42. The X-axis motor 33 includes an encoder 43. The Y-axis motor 34 includes an encoder 44. The magazine motor 35 includes an encoder 45. The encoders 41 to 45 are connected to the drive circuits 21 to 25 of the numerical controller 1, respectively.

<Outline of Numerical Control Device 1>
The electrical configuration of the numerical control device 1 will be described with reference to FIG. The numerical control device 1 includes a CPU 11, a ROM 12, a RAM 13, a nonvolatile storage device 14, a voltage abnormality detection circuit 15, an input / output unit 16, drive circuits 21 to 25, and the like, and uses a three-phase AC power source 19 as a drive source. The CPU 11 performs overall control of the numerical control device 1. The ROM 12 stores various programs. The RAM 13 temporarily stores various data during execution of various processes. The non-volatile storage device 14 stores a plurality of NC programs registered by the operator using the input device 17. The NC program is composed of a plurality of blocks including various control commands, and controls various operations including axis movement of the machine tool 2, tool change, and the like in units of blocks. The nonvolatile storage device 14 stores a threshold table 14A (see FIG. 4) described later.

  The voltage abnormality detection circuit 15 detects the presence or absence of abnormality in the three-phase AC voltage supplied from the three-phase AC power source 19. The drive circuit 21 is connected to the Z-axis motor 31 and the encoder 41. The drive circuit 22 is connected to the spindle motor 32 and the encoder 42. The drive circuit 23 is connected to the X-axis motor 33 and the encoder 43. The drive circuit 24 is connected to the Y-axis motor 34 and the encoder 44. The drive circuit 25 is connected to the magazine motor 35 and the encoder 45. The drive circuits 21 to 25 receive command signals from the CPU 11 and output drive currents to the corresponding motors 31 to 35, respectively. The drive circuits 21 to 25 receive feedback signals from the encoders 41 to 45 and perform feedback control of position and speed. The input / output unit 16 is connected to the input device 17 and the display device 18, respectively.

  The user can select one NC program from among a plurality of NC programs with the input device 17. The CPU 11 displays the selected NC program on the display device 18. The CPU 11 controls the operation of the machine tool 2 based on the NC program displayed on the display device 18.

  The three-phase AC power source 19 will be described with reference to FIG. The three-phase AC power source 19 is an AC power source combining three systems of single-phase AC with the current or voltage phases shifted from each other, and supplies an AC voltage of 200 V, for example. The first phase is the R phase, the second phase is the S phase, and the third phase is the T phase. The three-phase AC power source 19 shown in FIG. 2 has a Δ connection (delta connection). The Δ connection is a connection in which the three phases are connected in the direction in which the phase voltage is applied to form a closed circuit. The three-phase AC power source 19 may be a Y connection or a V connection in addition to the Δ connection.

<Voltage abnormality detection circuit 15>
The configuration of the voltage abnormality detection circuit 15 will be described with reference to FIG. The voltage abnormality detection circuit 15 detects an abnormality in the AC voltage supplied from the three-phase AC power source 19. The voltage abnormality detection circuit 15 includes an R-phase reference circuit 51, an S-phase reference circuit 52, a T-phase reference circuit 53, and an FPGA 55 (hereinafter collectively referred to as reference circuits 51 to 53).

  The R-phase reference circuit 51 divides the three-phase AC voltage output from the three-phase AC power source 19, and the potential difference between the other S phase and the lower one of the T phases becomes a predetermined voltage or more with the R phase as a reference. Sometimes outputs a pulse. The S-phase reference circuit 52 divides the three-phase AC voltage output from the three-phase AC power source 19, and the potential difference between the other R phase and the lower one of the T phases becomes a predetermined voltage or more with the S phase as a reference. Sometimes outputs a pulse. The T-phase reference circuit 53 divides the three-phase AC voltage output from the three-phase AC power supply 19, and the potential difference between the other R phase and the lower one of the S phases becomes a predetermined voltage or more with the T phase as a reference. Sometimes outputs a pulse. The FPGA 55 executes main processing (see FIG. 5) described later. The main process analyzes the pulse output from the reference circuits 51 to 53 and determines whether or not a voltage abnormality has occurred.

  The configuration of the R-phase reference circuit 51 will be described with reference to FIG. The R-phase reference circuit 51 includes resistors 61 and 62, a shunt regulator 63, a photocoupler 64, a bypass capacitor 65, and the like. The resistors 61 and 62 divide the three-phase AC voltage output from the three-phase AC power source 19 into an R phase, an S phase, and a T phase, respectively. The bypass capacitor 65 is connected in parallel with the resistor 62. The bypass capacitor 65 is connected to the divided R-phase voltage signal line to suppress fluctuations in the R-phase voltage. The shunt regulator 63 is turned on when the potential difference between the other S phase and the lower one of the T phases on the R phase basis becomes a predetermined voltage or more. When the shunt regulator 63 is turned on, the photocoupler 64 lights up and outputs a pulse to the FPGA 55. The shunt regulator 63 is turned off when the potential difference between the other S phase and the lower T phase is less than a predetermined voltage on the R phase basis. When the shunt regulator 63 is turned off, the photocoupler 64 is turned off.

  The S-phase reference circuit 52 includes resistors 71 and 72, a shunt regulator 73, a photocoupler 74, a bypass capacitor 75, and the like. The resistors 71 and 72 divide the three-phase AC voltage output from the three-phase AC power source 19 into an R phase, an S phase, and a T phase, respectively. The bypass capacitor 75 is connected in parallel with the resistor 72. The bypass capacitor 75 is connected to the divided S-phase voltage signal line and suppresses fluctuations in the S-phase voltage. The shunt regulator 73 is turned on when the potential difference between the other R phase and the lower one of the T phases on the S phase basis becomes a predetermined voltage or more. When the shunt regulator 73 is turned on, the photocoupler 74 is lit and outputs a pulse to the FPGA 55. The shunt regulator 73 is turned off when the potential difference between the other R phase and the lower one of the T phases is less than a predetermined voltage based on the S phase. When the shunt regulator 73 is turned off, the photocoupler 74 is turned off.

  The T-phase reference circuit 53 includes resistors 81 and 82, a shunt regulator 83, a photocoupler 84, a bypass capacitor 85, and the like. The resistors 81 and 82 divide the three-phase AC voltage output from the three-phase AC power source 19 into an R phase, an S phase, and a T phase, respectively. The bypass capacitor 85 is connected in parallel with the resistor 82. The bypass capacitor 85 is connected to the divided T-phase voltage signal line to suppress fluctuations in the T-phase voltage. The shunt regulator 83 is turned on when the potential difference between the other R phase and the lower one of the S phases is equal to or higher than a predetermined voltage on the T phase basis. When the shunt regulator 83 is turned on, the photocoupler 84 is turned on and a pulse is output to the FPGA 55. The shunt regulator 83 is turned off when the potential difference between the other R phase and the lower one of the S phases is less than a predetermined voltage on the T phase basis. When the shunt regulator 83 is turned off, the photocoupler 84 is turned off.

  The operation of the R-phase reference circuit 51 will be described with reference to FIGS. The waveform at the bottom of FIG. 3 is a voltage curve in which three phases of RST are input. Each voltage curve is a sin curve, and the phase is shifted by 120 degrees. The upper three waveforms in FIG. 3 are conceptual diagrams of each pulse waveform when the R phase reference, the S phase reference, and the T phase reference are set in order from the top. Each conceptual diagram shows a pulse waveform having a potential difference of a predetermined voltage or more (for example, 152.5 V or more) for easy understanding. When the potential difference is less than a predetermined voltage, the pulse voltage is zero.

  As described above, the R-phase reference circuit 51 outputs a pulse when the potential difference between the lower of the other S-phase and T-phase and the R-phase is equal to or higher than a predetermined voltage on the R-phase basis. For example, the description will be made by paying attention to a frame surrounded by a two-dot chain line shown in FIG. At t1, the voltage of the S phase is lower than that of the T phase, and the potential difference between the R phase and the S phase is the same. When the voltage in the S phase is lower than that in the T phase, the voltage is applied in the direction of the dotted arrow A in the R phase reference circuit 51 as shown in FIG. After t1, a potential difference is gradually generated between the R phase and the S phase, and reaches a predetermined voltage or more at t2. The shunt regulator 63 is turned on. A current flows between the K terminal (cathode terminal) and the A terminal (anode terminal) of the shunt regulator 63. The photocoupler 64 is lit and outputs a pulse to the FPGA 55. The pulse rises from t2 and reaches a certain value. The potential difference between the R phase and the S phase gradually decreases.

  At t3, the S phase and the T phase are reversed. The pulse drops slightly at t3. After t3, the voltage in the T phase is lower than that in the S phase, so that the voltage is applied in the direction of the two-dot chain line arrow B in the R phase reference circuit 51 as shown in FIG. After t3, a potential difference of a predetermined voltage or more is generated between the R phase and the T phase, so that the pulse rises again and reaches a constant value. The potential difference between the R phase and the T phase gradually decreases and becomes less than a predetermined voltage at t4. The shunt regulator 63 is turned off. The photocoupler 64 is turned off. The pulse becomes zero at t4. The pulse output from the R-phase reference circuit 51 repeats the waveform from t2 to t4 at regular intervals.

  The S phase reference circuit 52 and the T phase reference circuit 53 operate in the same manner as the R phase reference circuit 51. As shown in FIG. 3, the S-phase and T-phase pulse waveforms are out of phase with the R-phase pulse waveform. The R-phase pulse, S-phase pulse, and T-phase pulse are each output to the FPGA 55 in the RST phase order. The FPGA 55 executes main processing based on each pulse output from the reference circuits 51 to 53.

<Threshold table 14A>
FIG. 4 shows the threshold table 14 </ b> A stored in the nonvolatile storage device 14. The threshold value table 14A stores a first threshold value for detecting an overvoltage in a main process described later and a second threshold value for detecting a voltage drop in a main process described later. The first threshold value and the second threshold value are associated with each of a plurality of frequency ranges. The plurality of frequency ranges are based on a range including 50 Hz or 60 Hz, which is the reference voltage of the three-phase AC power supply 19, (thick line frame in the figure), and each frequency range is defined by 5 Hz.

  Further, the first threshold value and the second threshold value are set according to conditions (first condition to third condition, hereinafter referred to as “circuit conditions”) according to the parameters of the bypass capacitors 65, 75, and 85 (see FIG. 2). It is associated. The circuit conditions are, for example, frequency characteristics (cut-off frequency) of the bypass capacitors 65, 75, and 85. Hereinafter, the first threshold value and the second threshold value corresponding to the i-th condition (i is any one of 1 to 3) are referred to as “first threshold value (i)” and “second threshold value (i)”, respectively.

<Main processing>
The main process will be described with reference to FIG. The main process is executed by the FPGA 55. The FPGA 55 receives an instruction that can specify a circuit condition (i-th condition) for determining the first threshold value and the second threshold value (S11). For example, the FPGA 55 may accept the circuit conditions directly via the input device 17. Further, for example, the FPGA 55 may receive circuit conditions indirectly by receiving setting information of a setting switch (not shown) (such as a dip switch). The FPGA 55 may receive the setting information of the setting switch as an instruction that can specify the circuit condition, and specify the circuit condition. The FPGA 55 determines the first threshold value (i) and the second threshold value (i) corresponding to the received circuit condition based on the threshold value table 14A (S11).

  The FPGA 55 receives the RST phase pulse information (S13). The pulse information is information on pulses output from the R-phase reference circuit 51, the S-phase reference circuit 52, and the T-phase reference circuit 53, respectively. Next, the FPGA 55 measures the pulse width and the pulse period for each phase based on the pulse information (S15). As shown in FIG. 6, the pulse repeats at regular intervals. t7 is the time for the pulse to rise from the reference voltage. The reference voltage is a constant voltage of 152.5V, for example. t8 is the time when the pulse reaches the maximum voltage. t9 is the time when the pulse starts to drop from the maximum voltage. t10 is the time when the pulse drops to the reference voltage. t11 is the time when the next pulse rises from the reference voltage. The pulse width is the time from t7 to t10. The pulse period is the time from t7 to t11. The pulse width may be a time from t8 to t9.

  As shown in FIG. 5, the FPGA 55 calculates the frequency of the three-phase AC power source 19 for each phase based on the pulse period measured for each phase (S17). The FPGA 55 specifies, for each phase, a frequency range including the calculated frequency among the plurality of frequency ranges in the threshold table 14A. The FPGA 55 includes a first threshold value (i) (referred to as “first threshold value Th1”) and a second threshold value corresponding to the specified frequency range among the first threshold value (i) and the second threshold value (i) determined in S11. (I) (referred to as “second threshold Th2”) is specified for each phase (S19). The FPGA 55 calculates the ratio of the pulse width to the pulse period as the duty ratio for each phase of RST (S21).

  The FPGA 55 executes a first determination process (see FIG. 7) to determine whether or not an overvoltage has occurred (S23). The first determination process will be described with reference to FIG. The FPGA 55 determines whether the duty ratio of two or more phases is greater than the first threshold Th1 (S41). When the FPGA 55 determines that the duty ratio of two or more phases is greater than the first threshold Th1 (S41: YES), the FPGA 55 determines that an overvoltage has occurred in the AC voltage (S45). The FPGA 55 ends the first determination process and returns the process to the main process (see FIG. 5). When the FPGA 55 determines that the duty ratio of two or more phases is not greater than the first threshold value (S41: NO), the process proceeds to S43. The FPGA 55 determines whether the duty ratio of any one of the three phases is greater than the first threshold value Th1 for three consecutive times (S43). When the FPGA 55 determines that the duty ratio of any one of the three phases is not continuously greater than the first threshold value Th1 (S43: NO), the FPGA 55 ends the first determination process, and the main process is performed. Return to processing (see FIG. 5).

  As shown in FIG. 5, the FPGA 55 executes a second determination process (see FIG. 8) in order to determine whether or not a voltage drop has occurred after the first determination process (S23) is completed (S25). The second determination process will be described with reference to FIG. The FPGA 55 determines whether a reference circuit of two or more phases among the reference circuits 51 to 53 continues to output a pulse for 50 ms or more (S61). The FPGA 55 determines that a voltage drop has occurred in the AC voltage (S71) when it is determined that the reference circuit of two or more phases continues to output no pulse for 50 ms or longer (S61: YES). The FPGA 55 ends the second determination process and returns the process to the main process (see FIG. 5). When the FPGA 55 determines that the reference circuit of two or more phases has output a pulse within 50 ms (S61: NO), the FPGA 55 advances the process to S63.

  The FPGA 55 determines whether the frequency of each phase calculated by the process of S17 (see FIG. 6) is closer to 50 Hz than 60 Hz (S63). When the FPGA 55 determines that the frequency is close to 50 Hz (S63: YES), the process proceeds to S65. The FPGA 55 determines whether all the duty ratios of the three phases have become smaller than the second threshold value Th2 continuously three times (S65). When the FPGA 55 determines that all the three-phase duty ratios are not continuously smaller than the second threshold Th2 three times (S65: NO), the FPGA 55 ends the second determination process, and the process is the main process (FIG. 5). Return to).

  On the other hand, when the FPGA 55 determines that the frequency of each phase is closer to 60 Hz than 50 Hz (S63: NO), the process proceeds to S67. The FPGA 55 determines whether all the duty ratios of the three phases have become smaller than the second threshold Th2 continuously four times (S67). When the FPGA 55 determines that all three-phase duty ratios are not continuously smaller than the second threshold Th2 four times (S67: NO), the FPGA 55 ends the second determination process, and the process is the main process (FIG. 5). Return to).

  As shown in FIG. 5, after the second determination process (S25) is completed, the FPGA 55 determines that at least one of the overvoltage and the voltage drop is included in the AC voltage by the first determination process (S23) and the second determination process (S25). It is determined whether it has occurred (S27). When the FPGA 55 determines that neither an overvoltage nor a voltage drop has occurred in the AC voltage (S27: NO), the FPGA 55 returns the process to S13. The FPGA 55 repeats the processes of S13 to S25.

  When the FPGA 55 repeats the first determination process (S23) shown in FIG. 7 and determines that the duty ratio of any one of the three phases is continuously greater than the first threshold value Th1 (S43: YES). Then, it is determined that an overvoltage has occurred in the AC voltage (S45). The FPGA 55 ends the first determination process and returns the process to the main process (see FIG. 5).

  The FPGA 55 repeats the second determination process (S25) shown in FIG. 8, the frequency calculated by the process of S17 (see FIG. 6) is closer to 50 Hz than 60 Hz (S63: YES), and all three-phase duty ratios are When it is determined that the voltage is smaller than the second threshold value Th2 for three consecutive times (S65: YES), it is determined that a voltage drop has occurred in the AC voltage (S71). The FPGA 55 ends the second determination process and returns the process to the main process (see FIG. 5). Further, the FPGA 55 determines that the frequency calculated by the process of S17 is closer to 60 Hz than 50 Hz (S63: NO), and that all three-phase duty ratios are continuously smaller than the second threshold Th2 four times ( S67: YES), it is determined that a voltage drop has occurred in the AC voltage (S71). The FPGA 55 ends the second determination process and returns the process to the main process (see FIG. 5).

  As shown in FIG. 5, when the FPGA 55 determines that at least one of an overvoltage and a voltage drop has occurred in the AC voltage through the first determination process (S23) and the second determination process (S25) (S27: YES). The process proceeds to S29. The FPGA 55 outputs the determination result to the CPU 11 (S29). The CPU 11 displays notification information for notifying the occurrence of overvoltage and voltage drop on the display device 18 based on the output determination result. The FPGA 55 ends the main process.

<Operation and effect of this embodiment>
The voltage abnormality detection circuit 15 includes bypass capacitors 65, 75, 85 connected in parallel to resistors 62, 72, 82 provided on the voltage signal lines of each phase of the three-phase AC power supply 19. The nonvolatile memory device 14 of the numerical controller 1 corresponds to the first threshold value (i) and the second threshold value (i) for each circuit condition (i-th condition) of the bypass capacitors 65, 75, and 85 in a plurality of frequency ranges. The threshold value table 14A stored with this information is stored. The numerical controller 1 accepts the circuit condition directly or indirectly, and determines the first threshold value (i) and the second threshold value (i) corresponding to the accepted circuit condition based on the threshold value table 14A (S11). . The numerical control device 1 specifies the frequency of each phase (R phase, S phase, T phase) of the three-phase AC voltage (S17), and the corresponding first threshold value Th1 and second threshold value Th2 are based on the threshold value table 14A. (S19). The numerical controller 1 determines whether an overvoltage and a voltage drop have occurred in the three-phase AC voltage according to the relationship between the specified first threshold Th1 and second threshold Th2 and the duty ratio of the three-phase AC voltage (S23, S25). At this time, when the frequency of the three-phase AC voltage varies according to the circuit conditions of the bypass capacitors 65, 75, and 85, the numerical controller 1 sets the first threshold Th1 and the second threshold Th2 corresponding to the varied frequencies. Based on this, it can be determined whether the three-phase AC voltage is abnormal. Therefore, the numerical controller 1 can accurately detect whether the three-phase AC voltage is abnormal.

  The three-phase AC power source 19 is a three-phase (R phase, S phase, T phase) AC power source. Reference circuits 51 to 53 divide the three-phase AC voltage into an R phase, an S phase, and a T phase. Therefore, the numerical controller 1 can accurately determine whether there is an abnormality in the voltage of the three-phase AC power supply 19 based on the voltage of each phase.

  When the duty ratio of two or more of the R phase, S phase, and T phase divided by the reference circuits 51 to 53 is greater than the first threshold Th1 (S41: YES), the numerical controller 1 has an overvoltage in the AC voltage. It is determined that it has occurred (S45). At this time, the numerical controller 1 can accurately determine the overvoltage of the AC voltage. When the duty ratio of two or more of the three phases is not greater than the first threshold Th1 (S41: NO), the numerical control device 1 has a duty ratio of any of the three phases greater than the first threshold Th1. When it is continuously greater than three times (S43: YES), it is determined that an overvoltage has occurred in the AC voltage (S45). At this time, the numerical controller 1 can determine the overvoltage of the AC voltage with higher accuracy.

  The reference circuits 51 to 53 output a pulse signal when the potential difference between the divided R-phase, S-phase, and T-phase and the other two phases with a smaller voltage is equal to or higher than a predetermined voltage. The numerical controller 1 determines that a voltage drop has occurred in the AC voltage when a pulse signal of two or more phases among pulse signals corresponding to three phases is not transmitted from the reference circuits 51 to 53 for 50 ms or more (S61: YES). (S71). At this time, the numerical controller 1 can accurately determine the voltage drop of the AC voltage. When the numerical controller 1 determines that the reference circuit of two or more phases has output a pulse within 50 ms (S61: NO), and the three-phase duty ratio is a predetermined number of times (three or four times) from the second threshold Th2. ) When continuously small (S65: YES, S67: YES), it is determined that a voltage drop has occurred in the AC voltage (S71). At this time, the numerical controller 1 can determine the voltage drop of the AC voltage with higher accuracy.

  When the frequency of each phase of the AC voltage is closer to 50 Hz than 60 Hz (S63: YES), the numerical control device 1 is when the duty ratio of all three phases is three times consecutively smaller than the second threshold Th2 (S65). : YES), it is determined that the AC voltage is abnormal (S71). When the frequency of each phase of the AC voltage is closer to 60 Hz than 50 Hz (S63: NO), and the numerical control device 1 is when all three-phase duty ratios are continuously four times smaller than the second threshold Th2 (S67: YES) ), It is determined that the AC voltage is abnormal (S71). That is, the numerical controller 1 increases the number of comparisons with the second threshold Th2 as the frequency of each phase of the AC voltage is relatively large. The time until the determination by the above method is completed corresponds to a value obtained by multiplying the reciprocal of the frequency by the number of comparisons with the second threshold Th2. Therefore, the numerical control apparatus 1 can equalize the time until the determination of whether there is an abnormality in the AC voltage is completed regardless of the frequency of each phase of the AC voltage.

  The FPGA 55 outputs a determination result as to whether an overvoltage and a voltage drop have occurred in the AC voltage to the CPU 11 (S29). The CPU 11 displays notification information for notifying the occurrence of overvoltage and voltage drop on the display device 18 based on the output determination result. At this time, the numerical controller 1 can notify the outside of the occurrence of the voltage abnormality.

<Modification>
The present invention is not limited to the above embodiment. Although the numerical control device 1 detects the abnormality of the three-phase AC voltage, it may detect the abnormality of the two-phase AC voltage or may detect the abnormality of the AC voltage of three or more phases. The numerical controller 1 may include other light receiving element devices (for example, optical MOSFETs) instead of the photocouplers 64, 74, and 84 of the reference circuits 51 to 53. The CPU 11 may stop the operation of the machine tool 2 based on the determination result output by the FPGA 55. The FPGA 55 calculates the duty ratio from the pulse width and the pulse period, but may determine overvoltage or voltage drop only by the pulse width. The threshold value table 14A may store a first threshold value and a second threshold value that are the maximum values of the divided voltages. The FPGA 55 may determine the occurrence of overvoltage and voltage drop by comparing the maximum voltage of the voltage with the first threshold value and the second threshold value instead of the duty ratio. In the above embodiment, the numerical control device 1 has been described as an embodiment of the voltage abnormality detection device of the present invention, but a voltage abnormality detection device independent of the numerical control device 1 may be used. Various parameters (three times, four times, 50 ms, etc.) in the first determination process and the second determination process can be changed even if they are examples.

  In the threshold value table 14A, the first threshold value (i) and the second threshold value (i) are associated with the circuit condition (i-th condition) according to the parameters of the bypass capacitors 65, 75, and 85, and stored for each frequency range. The threshold value table 14A may associate the first threshold value (i) and the second threshold value (i) with circuit conditions different from the parameters of the bypass capacitors 65, 75, and 85. For example, the reference circuits 51 to 53 may include a low-pass filter and a high-pass filter that suppress fluctuations in the divided voltage. The threshold value table 14A may associate the first threshold value (i) and the second threshold value (i) with the frequency characteristics of the low-pass filter and the high-pass filter as circuit conditions.

  The FPGA 55 may determine that the AC voltage is abnormal only when the duty ratio of two or more of the three phases is greater than the first threshold Th1 (S41: YES) (S45). At this time, the FPGA 55 may not execute the process of S43. The FPGA 55 may determine that the AC voltage is abnormal only when the duty ratio of any one of the three phases is continuously larger than the first threshold Th1 three times or more (S43: YES) (S45). . At this time, the FPGA 55 may not execute the process of S41.

  The FPGA 55 may determine that a voltage drop has occurred in the AC voltage only when the reference circuits 51 to 53 do not output a pulse signal of two or more phases for 50 ms or longer (S61: YES) (S71). At this time, the FPGA 55 does not have to execute the processes of S65 and S67. The FPGA 55 determines that a voltage drop has occurred in the AC voltage only when the three-phase duty ratio is continuously smaller than the second threshold Th2 by a predetermined number of times (three times or four times) (S65: YES, S67: YES). (S71). At this time, the FPGA 55 may not execute the process of S61.

  The FPGA 55 may set the same number of determinations at the time of determination by the process of S65 or S67. That is, the FPGA 55 may use the same number of determinations when all the three-phase duty ratios are smaller than the second threshold Th2 regardless of the frequency of each phase of the AC voltage.

<Others>
The reference circuits 51 to 53 are an example of voltage dividing means and pulse output means of the present invention. The first threshold value and the second threshold value are examples of the reference information of the present invention. The nonvolatile storage device 14 that stores the threshold value table 14A is an example of the “storage unit” in the present invention. The FPGA 55 that executes the process of S11 is an example of a determination unit of the present invention. The FPGA 55 that executes the process of S17 is an example of a first specifying unit of the present invention. The FPGA 55 that executes the process of S19 is an example of the second specifying means of the present invention. The FPGA 55 that executes the processes of S23 and S25 is an example of a determination unit of the present invention. The FPGA 55 that performs the process of S29 is an example of a result output unit of the present invention.

14: Nonvolatile memory device 14A: Threshold table 15: Voltage abnormality detection circuit 19: Three-phase AC power supplies 51, 52, 53: Reference circuit 55: FPGA
65, 75, 85: Bypass capacitor

Claims (8)

A voltage abnormality detection device for detecting an abnormality in an AC voltage,
Voltage dividing means for dividing the AC voltage into a plurality of phases;
A storage unit storing a table in which reference information defined for each frequency is associated with each circuit configuration connected to the signal line of the AC voltage;
A determination unit that receives an instruction capable of specifying the circuit configuration, and determines the reference information for each frequency corresponding to the circuit configuration specified by the received instruction;
First specifying means for specifying each frequency of the plurality of phases divided by the voltage dividing means;
Second specifying means for specifying the reference information corresponding to the frequency specified by the first specifying means based on the reference information for each frequency determined by the determining means;
A voltage abnormality detection device comprising: a determination unit that determines whether or not the AC voltage is abnormal in accordance with a relationship between the reference information specified by the second specification unit and the AC voltage. The AC voltage is a three-phase AC voltage,
2. The voltage abnormality detection device according to claim 1, wherein the voltage dividing unit divides the three-phase AC voltage into an R phase, an S phase, and a T phase.   The determination means has an abnormality in the AC voltage when a duty ratio of two or more of the R phase, S phase, and T phase divided by the voltage dividing means is larger than a first threshold value indicated by the reference information. The voltage abnormality detection device according to claim 2, wherein the voltage abnormality detection device is determined. The determination means includes
The R, S, and T phase duty ratios divided by the voltage dividing means are repeatedly compared with the first threshold indicated by the reference information,
3. The AC voltage is determined to be abnormal when a duty ratio of any one of an R phase, an S phase, and a T phase is continuously greater than the first threshold by a predetermined number of times or more. The voltage abnormality detection apparatus described in 1. Pulse output means is further provided for outputting a pulse signal when the potential difference between each of the R phase, S phase, and T phase divided by the voltage dividing means and the other two phases with a smaller voltage is a predetermined voltage or more. ,
When the pulse output means does not exceed the predetermined time for the pulse signal of two or more phases among the pulse signals corresponding to the R phase, S phase, and T phase divided by the voltage dividing means, The voltage abnormality detection device according to claim 2, wherein the abnormality is determined to be abnormal. The determination means includes
The duty ratio of each of the R phase, S phase, and T phase divided by the voltage dividing means is repeatedly compared with the second threshold value indicated by the reference information,
3. The voltage abnormality according to claim 2, wherein when the duty ratio of the R phase, the S phase, and the T phase is continuously smaller than the second threshold by a predetermined number of times or more, it is determined that the AC voltage is abnormal. Detection device.   The voltage abnormality detection device according to claim 6, wherein the predetermined number of times differs depending on the frequency specified by the first specifying unit.   The voltage abnormality detection device according to claim 1, further comprising a result output unit that outputs a determination result by the determination unit.

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