JP2019062019A - Semiconductor device and semiconductor storage device - Google Patents

Abstract

An object of the present invention is to provide a semiconductor device and a semiconductor storage device which are efficient even in the case where a plurality of capacities are stacked and used, and capable of taking measures against electromagnetic interference in which an adverse influence on the surroundings is suppressed. A first power supply line VCC to which a predetermined voltage is applied, a second power supply line VSS to which a voltage lower than the predetermined voltage is applied, and one of a first power supply line VCC A first capacitor C1 to which a terminal is connected, a second capacitor C2 to which one terminal is connected to a second power supply line VSS, the other terminal of the first capacitor C1 and the other of the second capacitor C2 Switch for controlling connection and disconnection of the first capacitor C1 and the second capacitor C2 between the first power supply line VCC and the second power supply line VSS. 12, T1 and. [Selected figure] Figure 1

Description

  The present invention relates to a semiconductor device and a semiconductor storage device, and more particularly to a semiconductor device and a semiconductor storage device provided with an electromagnetic interference (EMI) countermeasure circuit.

  Electromagnetic interference means that noise generated by a specific electronic device causes an undesirable failure in another electronic device. Especially in airplanes and medical sites, malfunction of the equipment induced by electromagnetic interference may be a serious problem. Therefore, in order to prevent the problem of electromagnetic interference in advance, regulatory standards for EMI for electronic devices are set in each country.

  Countermeasures against EMI are taken not only at the electronic device main body but also at each level of modules, components (parts) and the like, and it is required to take unique measures for semiconductor devices. However, in the case of a semiconductor device such as a general-purpose memory, for example, there are a wide variety of electronic devices mounted, and it is difficult to uniquely determine specific countermeasure contents such as setting of a resonant frequency. Therefore, there has been a demand for a semiconductor device in which the content of the EMI countermeasure can be adjusted in accordance with the mounted product.

  As such a semiconductor device, for example, a semiconductor integrated circuit disclosed in Patent Document 1 is known. The semiconductor integrated circuit disclosed in Patent Document 1 includes a functional block circuit and a switching capacitor unit having a switch and a decoupling capacitor connected in series between a power supply line and a ground line. The capacitance value of the decoupling capacitor is set to shift the resonance frequency fr with the external factor by at least the frequency bandwidth Δft when the switch is turned on or off. More specifically, in the semiconductor integrated circuit according to Patent Document 1, the connection between VDD and GND is released by a transistor (switch) provided on the VDD side, and the capacitance value connected to the VDD node is adjusted. With the above configuration, the semiconductor integrated circuit disclosed in Patent Document 1 can easily take measures against EMI even after the manufacture of a device on which the semiconductor integrated circuit is mounted.

JP, 2011-009291, A

  However, in the semiconductor integrated circuit according to Patent Document 1, the on resistance of the transistor can not be ignored, and waste occurs in the disposed capacitance value. The total charge amount is lower than the original capacity due to the voltage drop due to the on resistance of the transistor. In addition, the insertion of the resistance increases the time constant, which causes a decrease in charge / discharge speed. Further, the decrease in the voltage of the power supply VDD is a factor to lower the performance of the semiconductor integrated circuit. Although there is also a method of increasing the gate width W of the transistor in order to reduce the on resistance, the area of the connection transistor is increased.

  In addition, when the switch is turned off, a node (node) connected to the switch may be a floating node (a node whose potential is not fixed). Such a floating node may exert the function of an antenna, and the floating node may be a noise source emitting noise, causing a malfunction of the semiconductor integrated circuit, or collecting noise from the surroundings to malfunction the semiconductor integrated circuit. There is a problem of causing

  By the way, as in the semiconductor integrated circuit according to Patent Document 1, a capacitor (capacitance) is an essential device in EMI countermeasures. In this regard, in the memory device, the capacity of the concate type (sometimes referred to as “crown type”) utilizing the configuration of the memory cell is often used. Concave type capacitors are, for example, capacitive elements in which a recess is formed in an interlayer insulating film, and a lower electrode, a dielectric film, and an upper electrode are formed in the recess, and miniaturization is possible while securing a constant capacitance. It is a capacitive element. Therefore, in a memory device, it is convenient if an EMI countermeasure circuit can be configured using this concatenate-type capacity. On the other hand, since the concave type capacitance generally has a low withstand voltage, a plurality of capacitances may be used in a stacked configuration (series connection). In the case where the EMI countermeasure circuit is configured using the capacitors of the concaving type, it is necessary to take such circumstances into consideration.

  In this respect, as described above, the semiconductor integrated circuit according to Patent Document 1 having the defect of the on-state resistance needs further improvement in order to apply a plurality of capacitors in a stacked configuration.

  In view of the problems as described above, the present invention is a semiconductor device that is efficient even when a plurality of capacitors are used in a stacked configuration, and capable of taking measures against electromagnetic interference with suppressed adverse effects on the surroundings. And a semiconductor memory device.

  A semiconductor device according to the present invention includes a first power supply line to which a predetermined voltage is applied, a second power supply line to which a voltage lower than the predetermined voltage is applied, and the first power supply line. A first capacitance with one terminal connected to it, a second capacitance with one terminal connected to the second power supply line, the other terminal of the first capacitance, and the second capacitance A switch connected between the other terminal and controlling whether the first and second capacitors are connected or disconnected between the first power supply line and the second power supply line Department and is included.

  On the other hand, a semiconductor memory device according to the present invention includes the above-described semiconductor device, and a memory unit including a plurality of memory cells each having a capacity equal to that of the first capacity and the second capacity.

  According to the present invention, it is possible to provide a semiconductor device and semiconductor storage device that are efficient even when using a plurality of capacitances stacked in a stack, and that can be protected against electromagnetic interference with suppressed adverse effects on the surroundings. It becomes possible.

FIG. 1 is a circuit diagram showing an EMI countermeasure circuit and a semiconductor memory device according to a first embodiment. FIG. 7 is a circuit diagram showing an EMI countermeasure circuit and a semiconductor memory device according to a second embodiment. FIG. 14 is a circuit diagram showing an EMI countermeasure circuit and a semiconductor memory device according to a third embodiment. FIG. 14 is a circuit diagram showing an EMI countermeasure circuit and a semiconductor memory device according to a fourth embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment
FIG. 1 is a circuit diagram showing an EMI countermeasure circuit 10 and a semiconductor memory device (memory) 50 according to the present embodiment.

  As shown in FIG. 1, the semiconductor memory device 50 is configured to include an EMI countermeasure circuit 10 and a semiconductor circuit 16. The semiconductor circuit 16 according to the present embodiment is a memory circuit as an example. The EMI countermeasure circuit 10 constitutes a semiconductor device according to the present invention. In FIG. 1, VCC indicates a high potential side power supply, and VSS indicates a low potential side power supply.

  As shown in FIG. 1, the EMI countermeasure circuit 10 is configured to include a control circuit 12, a P-type MOS (Metal Oxide Semiconductor) transistor T1, and capacitors C1 and C2 which are stacked. The capacitor C1 is connected between the drain of the P-type MOS transistor T1 and the power supply VCC, and the capacitor C2 is connected between the source of the P-type MOS transistor T1 and the power supply VSS. In the present embodiment, the capacitors C1 and C2 are capacitors of the concive type. The capacitors C1 and C2 are connected between the power supply VCC and the power supply VSS as needed, and are configured to function as a so-called decoupling capacitor. The capacitances C1 and C2 are "unit capacitances" according to the present invention, and "unit capacitance" means a capacitance having a common shape, capacitance value, and the like.

  Here, when current flows when the semiconductor memory device 50 operates, the wiring patterns of the power supplies VCC, VSS, etc. function as antennas and resonate, which may cause electromagnetic radiation. The EMI countermeasure circuit 10 included in the semiconductor memory device 50 according to the present embodiment changes the resonance frequency of such resonance caused by the wiring patterns of the power supplies VCC and VSS, and makes transition to a band where the resonance amplitude becomes sufficiently small. It is intended to reduce the electromagnetic radiation emitted to the outside.

The control circuit 12 has a function of switching on / off the P-type MOS transistor T1.
FIG. 1 shows only the inverter 14 which is an output stage of the control signal Sc for controlling the gate of the P-type MOS transistor T1, and the other circuits are omitted. When the control signal Sc is set to a low level (hereinafter, "L") to turn on the P-type MOS transistor T1, the capacitors C1 and C2 connected in series are connected between the power supplies VCC and VSS. On the other hand, when the control signal Sc is set to the high level (hereinafter, "H") to turn off the P-type MOS transistor T1, the capacitors C1 and C2 are disconnected, and the power supply VCC and VSS become open (open) .

  The control circuit 12 switches the connection and non-connection of the capacitors C1 and C2 according to, for example, the device (electronic apparatus) in which the semiconductor memory device 50 is mounted, and is a circuit that functions when changing the configuration (content) of the EMI countermeasure circuit 10 It is. That is, the control circuit 12 changes and fixes the control signal Sc in accordance with the device in which the semiconductor memory device 50 is mounted. Therefore, for example, a fuse may be used as the control circuit 12 and the value of the control signal Sc may be fixed. Alternatively, instead of the control circuit 12, a control terminal may be provided at the input of the inverter 14 so that control can be externally performed.

  As described above, in the present embodiment, the control circuit 12 switches the on / off state of the P-type MOS transistor T1 to change the capacitance value between the power supplies VCC and VSS (hereinafter, "inter-power supply capacitance value"). Let Thus, the EMI countermeasure circuit 10 according to the present embodiment has a function of changing the inter-power-supply capacitance value by changing the capacitance connection. By this, it is possible to shift the resonance frequency of the resonance generated in the semiconductor memory device 50 to a band where the resonance amplitude can be neglected, and reduce the electromagnetic radiation radiated from the semiconductor memory device 50 to the outside. It becomes.

  As shown in FIG. 1, in the EMI countermeasure circuit 10 according to the present embodiment, a P-type MOS transistor T1 is connected between capacitors C1 and C2. Here, since the concave type capacitor used in the memory device generally has a low withstand voltage, when used as an external power supply, the voltage applied per one stage of the capacitor is reduced by stacking (series connection) according to the power supply voltage. There is a need. Therefore, since an intermediate node exists in the middle of the stacked configuration, a stabilizing capacitance (decoupling capacitor) used by connecting between the power supplies VCC and VSS is a capacitance C1 and C2 as shown in FIG. The configuration of the present embodiment in which the P-type MOS transistor T1 is connected between can be employed.

  Furthermore, in the EMI countermeasure circuit 10 and the semiconductor memory device 50 according to the present embodiment, the ON resistance component of the P-type MOS transistor T1 connected to the power supply is removed, so the voltage drop when charging the capacitors C1 and C2. As a result, the time constant in charge / discharge can be further improved (it becomes faster). This is because in the EMI countermeasure circuit 10 according to the present embodiment, the drain side and the source side of the P-type MOS transistor T1 are DC-cut (direct current cut-off) by C1 and C2, so the semiconductor integrated circuit according to Patent Document 1 The charge / discharge current does not flow to the decoupling capacitor as shown in FIG.

Second Embodiment
The EMI countermeasure circuit 10A and the semiconductor memory device 50A according to the present embodiment will be described with reference to FIG. The semiconductor memory device 50A has a form in which the EMI countermeasure circuit 10 of the semiconductor memory device 50 according to the above embodiment is replaced with an EMI countermeasure circuit 10A. Therefore, since the semiconductor circuit 16 is the same as the semiconductor memory device 50, the detailed description will be omitted.

  As shown in FIG. 2, the EMI countermeasure circuit 10A includes a P-type MOS transistor T2, an N-type MOS transistor T3, and capacitors C3 and C4. The control circuit 12 outputs a control signal Sc in the same manner as the EMI countermeasure circuit 10 described above. In the present embodiment, the value of the control signal Sc is a binary value of H or L.

  The EMI countermeasure circuit 10A operates as follows. That is, when the control signal Sc is L, the P-type MOS transistor T2 is turned on and the N-type MOS transistor T3 is turned off. As a result, capacitances C3 and C4 are connected between the power supplies VCC and VSS. On the other hand, when the control signal Sc is H, the P-type MOS transistor T2 is turned off and the N-type MOS transistor T3 is turned on. As a result, the capacitors C3 and C4 are disconnected between the power supplies VCC and VSS.

  As described above, the EMI countermeasure circuit 10A according to the present embodiment has a function of changing the inter-power-supply capacitance value by changing the connection of the capacitance. By this, it is possible to shift the resonance frequency of the resonance generated in the semiconductor memory device 50A to a band where the resonance amplitude can be neglected, and reduce the electromagnetic radiation radiated from the semiconductor memory device 50A to the outside. It becomes.

  Further, in the EMI countermeasure circuit 10A according to the present embodiment, when the control signal Sc is set to H and the capacitors C3 and C4 are separated from the power supply VCC and VSS, the N-type MOS transistor T3 is turned on and the power supply The intermediate node (node) N1 on the VSS side is configured to be fixed to the power supply VSS. Generally, in an electronic circuit, a node (floating node) whose potential is not fixed often becomes a noise source. In particular, in the present embodiment, when the capacitors C3 and C4 are disconnected from the power supply VCC-VSS, there is a possibility that the potential of the node N1 becomes unstable and becomes a noise source. In addition, it is also assumed that the floating node acts as an antenna to pick up ambient noise and cause the electronic circuit to malfunction. However, in the EMI countermeasure circuit 10A, since the intermediate node N1 between the capacitors C3 and C4 is connected to the power supply VSS (fixed potential) and fixed in potential, generation of malfunction due to noise is suppressed. .

  In the present embodiment, the reason why the node N1 is fixed to the power supply VSS side when the capacitances C3 and C4 are disconnected is that the power supply VCC is considered to be higher in voltage and more susceptible to noise. It is. However, the present invention is not limited to this, and the node on the drain side of the P-type MOS transistor T2 may be fixed to the power supply VCC in consideration of the influence of noise and the like.

Third Embodiment
The EMI countermeasure circuit 10B and the semiconductor memory device 50B according to the present embodiment will be described with reference to FIG. The semiconductor memory device 50B has a form in which the EMI countermeasure circuit 10 of the semiconductor memory device 50 according to the above embodiment is replaced with an EMI countermeasure circuit 10B. Therefore, since the semiconductor circuit 16 is the same as the semiconductor memory device 50, the detailed description will be omitted.

  As shown in FIG. 3, the EMI countermeasure circuit 10B includes P-type MOS transistors T4 and T5, an N-type MOS transistor T6, and capacitors C5 and C6. The control circuit 12 outputs the control signal Sc as in the case of the EMI countermeasure circuit 10, but in the EMI countermeasure circuit 10B, the inverted signal of the control signal Sc (the input signal of the inverter 14) ScB (the complement of the control signal Sc) It is used to control transistors. In the present embodiment, the values of the control signals Sc and ScB are binary values of H or L.

  The EMI countermeasure circuit 10B operates as follows. That is, when the control signal ScB is H and the control signal Sc is L, the P-type MOS transistor T4 is off, the P-type MOS transistor T5 is on, and the N-type MOS transistor T6 is off. As a result, capacitors C5 and C6 are connected between the power supplies VCC and VSS. On the other hand, when the control signal ScB is L and the control signal Sc is H, the P-type MOS transistor T4 is on, the P-type MOS transistor T5 is off, and the N-type MOS transistor T6 is on. As a result, the capacitors C5 and C6 are disconnected between the power supplies VCC and VSS.

  As described above, the EMI countermeasure circuit 10B according to the present embodiment has a function of changing the inter-power-supply capacitance value by changing the connection of the capacitance. As a result, the resonance frequency of the resonance generated in the semiconductor memory device 50B can be shifted to a band where the resonance amplitude can be neglected, and the electromagnetic radiation radiated from the semiconductor memory device 50B to the outside can be reduced. It becomes.

  In the EMI countermeasure circuit 10B according to the present embodiment, when the control signals ScB is L and the control signal Sc is H to separate the capacitors C5 and C6 from between the power supplies VCC and VSS, the P-type MOS transistor T4 is formed. Is turned on, and the intermediate node (node) N2 on the power supply VCC side is configured to be fixed to the power supply VCC. Further, the N-type MOS transistor T6 is turned on, and the intermediate node (node) N3 on the power supply VSS side is fixed to the power supply VSS. As described above, in the EMI countermeasure circuit 10B, the intermediate nodes N2 and N3 between the capacitors C5 and C6 are connected to the power supplies VCC and VSS (fixed potential), respectively, and fixed in potential, so that occurrence of malfunction due to noise is suppressed. It is configured to be.

Fourth Embodiment
The EMI countermeasure circuit 10C and the semiconductor memory device 50C according to the present embodiment will be described with reference to FIG. The semiconductor memory device 50C has a form in which the EMI countermeasure circuit 10B of the semiconductor memory device 50B according to the above embodiment is replaced with an EMI countermeasure circuit 10C. Therefore, since the semiconductor circuit 16 is the same as the semiconductor memory device 50B, the detailed description will be omitted.

  As shown in FIG. 4, the EMI countermeasure circuit 10C is configured to include P-type MOS transistors T7 and T8, an N-type MOS transistor T9, and capacitors Cn and C7. The capacitance Cn is formed by connecting (consecutively) a plurality of concave-type capacitances (the case of seven is exemplified in FIG. 4). The control circuit 12 outputs the control signal Sc in the same manner as the EMI countermeasure circuit 10, but in the EMI countermeasure circuit 10C, an inverted signal (input signal of the inverter 14) ScB of the control signal Sc is also used to control each transistor. In the present embodiment, the values of the control signals Sc and ScB are binary values of H or L.

  The EMI countermeasure circuit 10C is obtained by replacing the capacitor C5 of the EMI countermeasure circuit 10B with a capacitor Cn and replacing the capacitor C6 with a capacitor C7. The specific circuit operation is the same as that of the EMI countermeasure circuit 10B, and thus the detailed description is omitted. The EMI countermeasure circuit 10C is configured to be able to switch whether to connect or disconnect the capacitors Cn and C7 between the power supply VCC and the VSS by the control signals ScB and Sc. As described above, the EMI countermeasure circuit 10C according to the present embodiment has a function of changing the inter-power-supply capacitance value by changing the connection of the capacitances. By this, it is possible to shift the resonance frequency of the resonance generated in the semiconductor memory device 50C to a band where the resonance amplitude can be neglected, and to reduce the electromagnetic radiation radiated from the semiconductor memory device 50C to the outside. It becomes.

  Furthermore, in the EMI countermeasure circuit 10C according to the present embodiment, when the capacitances Cn and C7 are disconnected between the power supplies VCC and VSS, an intermediate node (node) N4 on the power supply VCC side is fixed to the power supply VCC. The intermediate node (node) N5 on the power supply VSS side is configured to be fixed to the power supply VSS. As described above, the intermediate node N4 between the capacitors Cn and C7 which can be floating is connected to the power supply VCC, and the node N5 is connected to the power supply VSS, and the potential is fixed. It is done.

In the present embodiment, a concave type capacitance (unit capacitance) using the configuration of the memory cell is used as the capacitance, but as described above, the concave type capacitance is used as a capacitance connected for external power supply In some cases, it is necessary to stack and reduce the voltage across the individual capacitors to avoid breakdown problems. The capacity Cn is an example of such a stacked configuration.
In the present embodiment, although the capacity C7 is one capacity, it is needless to say that a plurality of unit capacities may be stacked.

  In the EMI countermeasure circuit 10C according to the present embodiment, the number of capacitances (Cn) connected to the power supply VCC side is larger than the number of capacitances (C7) connected to the power supply VSS side as described above. That is, on the side of the power supply VCC, the number of stacked capacitors of the concave type is increased more than on the side of the power supply VSS. This is because the power supply VCC is higher in voltage than the power supply VSS. That is, by increasing the number of stacks on the VCC side to which a higher voltage is applied, the voltage applied to each of the capacitors connected to the power supply VCC can be reduced. Also, although the power supply VCC to which a higher voltage is applied is more susceptible to noise from the surroundings than the power supply VSS, the number of stacked capacitors on the VCC side is increased in the EMI countermeasure circuit 10C. The influence of noise on the power supply VCC when the capacitances Cn and C7 are disconnected from the power supply VCC-VSS is effectively suppressed.

  Here, it is more preferable that the number of stacked capacitors of the concave type is at least three in terms of withstand pressure. If the number of stacking capacities is three, two should be stacked on the power supply VCC side and one should be stacked on the power supply VSS side. This more effectively suppresses the influence of noise on the power supply VCC.

  In each of the above-described embodiments, although the embodiment in which the capacitor of the concatenated type is used as the capacitor for the EMI countermeasure circuit is described as an example, the present invention is not limited to this, and another type of capacitor may be used. Furthermore, the number of capacitors in each of the above embodiments is an example, and the present invention is not limited to this. For example, in the EMI countermeasure circuit 10 (FIG. 1), each of the capacitors C1 and C2 may be stacked using a plurality of capacitors (unit capacitors).

  In each of the above-described embodiments, the switch for selecting whether the stacked capacity is connected or disconnected at the intermediate node is described as an example. However, the present invention is not limited to this. Alternatively, a plurality of switches may be arranged between different numbers of stacked capacities so that the number of capacity can be selected.

  In each of the above-described embodiments, the P-type MOS transistor and the N-type MOS transistor are illustrated as shown in the respective drawings. However, the present invention is not limited to this. The type MOS transistors may be used in the form of reversing P type and N type, respectively. Further, although the embodiment in which the inverter 14 is used as the output stage of the control circuit 12 is described as an example, the invention is not limited thereto, and a configuration using a circuit other than the inverter circuit may be used.

10, 10A, 10B, 10C EMI countermeasure circuit 12 control circuit 14 inverter 16 semiconductor circuit 50, 50A, 50B, 50C semiconductor memory devices C1 to C7, Cn capacitance N1 to N5 intermediate node Sc control signal ScB complement signal of control signal T1, T2, T4, T5, T7, T8 P-type MOS transistors T3, T6, T9 N-type MOS transistors

Claims (10)

A first power supply line to which a predetermined voltage is applied;
A second power supply line to which a voltage lower than the predetermined voltage is applied;
A first capacitance having one terminal connected to the first power supply line;
A second capacitance whose one terminal is connected to the second power supply line;
The first capacitor and the second capacitor are connected between the other terminal of the first capacitor and the other terminal of the second capacitor and the first power supply line and the second capacitor. A switching unit that controls whether to connect or disconnect between the power supply line of
Semiconductor devices. The semiconductor device according to claim 1, wherein at least one of the first capacitance and the second capacitance includes one unit capacitance or a plurality of unit capacitances connected in series. The semiconductor device according to claim 2, wherein the unit capacitance is a concave capacitance. When it is controlled to be separated by the switching unit,
At least one of the connection of the other terminal of the first capacitor to the first power supply line and the connection of the other terminal of the second capacitor to the second power supply line is performed. The semiconductor device according to any one of claims 1 to 3. The semiconductor device according to any one of claims 1 to 4, wherein a capacitance value of the first capacitance is smaller than a capacitance value of the second capacitance. The first capacitance includes a plurality of unit capacitances connected in series,
The second capacity includes one unit capacity or a plurality of unit capacities connected in series,
The semiconductor device according to claim 5, wherein the number of unit capacities included in the first capacity is larger than the number of unit capacities included in the second capacity. The first field effect transistor of the first conductivity type, wherein the switching unit has a drain terminal connected to the other terminal of the first capacitor and a source terminal connected to the other terminal of the second capacitor; A control circuit that outputs a control signal input to a gate terminal of the first field effect transistor;
The control signal switches between conduction and non-conduction of the first field effect transistor to connect the first capacitance and the second capacitance between the first power supply line and the second power supply line. The semiconductor device according to any one of claims 1 to 6, which controls whether to separate or to separate. The switching unit has a gate terminal connected to the gate terminal of the first field effect transistor, a drain terminal connected to the source terminal of the first field effect transistor, and a source terminal connected to the second power supply line Further comprising a second field effect transistor of the second conductivity type,
When the first capacitance and the second capacitance are disconnected from between the first power supply line and the second power supply line, the second field effect transistor is rendered conductive by the control signal to The semiconductor device according to claim 7, wherein a source terminal of the first field effect transistor is connected to the second power supply line. The switching unit is an inverter circuit that outputs the control signal, a gate terminal is connected to an input of the inverter circuit, a drain terminal is connected to the first power supply line, and a source terminal is the first field effect transistor And a third field effect transistor of the first conductivity type connected to the drain terminal of
When disconnecting the first capacitance and the second capacitance from between the first power supply line and the second power supply line, the third field effect transistor is rendered conductive by the complement signal of the control signal. The semiconductor device according to claim 7, wherein a drain terminal of the first field effect transistor is connected to the first power supply line. A semiconductor device according to any one of claims 1 to 9;
A storage unit including a plurality of memory cells each having a capacity equal to that of the first capacity and the second capacity;
Semiconductor memory device.