JP2018101560A - Semiconductor solid state battery - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor solid battery having high energy density and high output density.
A semiconductor layer including any one of an N-type semiconductor single layer, a P-type semiconductor single layer, and a PN junction type semiconductor layer, and an electrode provided on the semiconductor layer with an insulating layer interposed therebetween. A semiconductor solid state battery. The insulating layer preferably has a thickness of 30 nm or less and a relative dielectric constant of 10 or less. The insulating layer preferably has a film density of 60% or more. Thereby, the battery which does not use electrolyte solution can be provided.
[Selection] Figure 1

Description

  Embodiment mentioned later is related with a semiconductor solid battery.

In recent years, it has been required to efficiently use electricity from the viewpoint of the spread of electric equipment and energy saving. In connection with this, development of the secondary battery which can charge and discharge electricity is advanced. Various secondary batteries such as a Li-ion secondary battery, a lead storage battery, and a nickel metal hydride storage battery have been developed. For example, Japanese Patent Laid-Open No. 2001-338649 (Patent Document 1) discloses a Li ion secondary battery using a Li composite oxide as a positive electrode active material. Li-ion secondary batteries are used as batteries for electrical equipment because they can be miniaturized.
On the other hand, the Li ion secondary battery has a structure in which Li ions are taken in and out through an electrolytic solution. Therefore, it is a battery in which an electrolytic solution is essential. Similarly, lead acid batteries and nickel metal hydride batteries are batteries that require an electrolyte. Leakage of electrolyte may cause a fire or explosion. For this reason, the Li ion secondary battery has a sealed structure so as not to cause liquid leakage. However, there have been problems such as deterioration due to long-term use, usage of electric appliances, and liquid leakage depending on the usage environment.
In order to eliminate such problems caused by liquid leakage, development of semiconductor solid state batteries is underway. The semiconductor solid state battery is charged by capturing electrons at the energy level. Since it can be set as an all-solid-state secondary battery, it is not necessary to use electrolyte solution.
JP, 2014-154223, A (patent documents 2) is illustrated as a semiconductor solid battery.

JP 2001-338649 A JP 2014-154223 A

The semiconductor solid state battery of Patent Document 2 has a structure in which a semiconductor oxide as a charging layer and an insulating oxide as an insulating layer are stacked and an electrode is provided. In Patent Document 2, the output voltage and the discharge capacity are improved by this structure.
However, there was a demand for further improvement. The embodiment is for solving such a problem, and is for providing a semiconductor solid state battery with improved output voltage and discharge capacity.

  The semiconductor solid state battery according to the embodiment includes a semiconductor layer made of any one of an N-type semiconductor single layer, a P-type semiconductor single layer, or a PN junction type semiconductor layer, and an electrode provided on the semiconductor layer via an insulating layer. It is characterized by comprising.

The schematic diagram of the semiconductor solid battery (1st semiconductor solid battery) concerning embodiment. The schematic diagram of the other semiconductor solid battery (2nd semiconductor solid battery) concerning embodiment. The schematic diagram which shows the movement of an electron and a hole of a 1st semiconductor solid battery. The schematic diagram which shows the movement of an electron and a hole of a 2nd semiconductor solid battery.

The semiconductor solid state battery according to the embodiment includes a semiconductor layer made of any one of an N-type semiconductor single layer, a P-type semiconductor single layer, or a PN junction type semiconductor layer, and an electrode provided on the semiconductor layer via an insulating layer. It is characterized by comprising.
FIG. 1 shows a schematic diagram of a semiconductor solid state battery (first semiconductor solid state battery) according to the embodiment. In the figure, 1 is a semiconductor solid state battery, 2 is an N-type semiconductor, 3 is a P-type semiconductor, 4 is a first insulating layer, 5 is a second insulating layer, 6 is an electrode (N-type side electrode), and 7 is an electrode (P-type side electrode).
First, a PN junction type semiconductor layer in which an N type semiconductor 2 and a P type semiconductor 3 are joined is provided. A battery having a PN junction type semiconductor layer is called a first semiconductor solid state battery.
In the first semiconductor solid state battery, a first insulating layer 4 and a second insulating layer 5 are provided at both ends of a PN junction type semiconductor layer. The insulating layer provided on the N-type semiconductor 2 is referred to as a first insulating layer 4. The first insulating layer 4 is provided with an electrode 6. The electrode 6 is called an N-type side electrode. The insulating layer provided on the P-type semiconductor 3 is referred to as a second insulating layer 5. An electrode 7 is provided on the second insulating layer 5. The electrode 7 is called a P-type side electrode.

The first semiconductor solid state battery has a structure in which a PN junction semiconductor layer is sandwiched between a first insulating layer 4 and a second insulating layer 5.
When the first insulating layer 4 and the second insulating layer 5 are provided, a tunnel effect can be obtained. By obtaining the tunnel effect, the capacity can be increased.
Without the first insulating layer 4, carriers stored in the N-type semiconductor 2 easily flow to the electrode 6, and it is difficult for electricity to accumulate. Similarly, without the second insulating layer 5, carriers stored in the P-type semiconductor 3 easily flow to the electrode 7, and it is difficult for electricity to accumulate.
The first insulating layer 4 or the second insulating layer 5 preferably has a film thickness of 30 nm or less and a relative dielectric constant of 10 or less. If the film thickness exceeds 30 nm, it becomes a resistor and it becomes difficult to take out electricity. Similarly, if the relative dielectric constant is greater than 10, there is a risk of forming a resistor.
For this reason, the thickness of the first insulating layer 4 or the second insulating layer 5 is preferably 30 nm or less, more preferably 10 nm or less. The lower limit of the film thickness is not particularly limited, but is preferably 3 nm or more. If the film thickness is as thin as less than 3 nm, the tunnel effect is insufficient and carriers are easily lost.

The relative dielectric constant is preferably 10 or less, more preferably 5 or less. Further, the lower limit value of the relative dielectric constant is not particularly limited, but is preferably 2 or more. If the relative dielectric constant is less than 2, the tunnel effect may be insufficient. The relative dielectric constant indicates a value obtained by dividing the dielectric constant of a substance by the dielectric constant of a vacuum. Specific dielectric constant ε _r = dielectric constant ε of material / dielectric constant ε ₀ of vacuum. In order to obtain a sufficient tunnel effect, it is effective to control the film thickness and relative dielectric constant of the insulating layer.
The film thickness of the first insulating layer (and the second insulating layer) can be measured with an enlarged photograph of the cross section. An enlarged photograph includes an SEM photograph or a TEM photograph. It is preferable to enlarge to 5000 times or more.

In addition, a resonator method can be used for measuring the relative dielectric constant. The resonator method is a method in which a resonator such as a cavity resonator is used and measurement is performed based on a change in resonance caused by a minute object to be measured. The resonator method is a method that allows measurement with a multilayer film.
When the film thickness of the multilayer film is 100 nm or more, the perturbation type cavity resonator method is effective. The temperature of the test environment is normal temperature (25 ± 2 ° C.). In the case of a multilayer film of less than 100 nm, capacitance-voltage measurement (CV measurement) is effective.
Moreover, it is preferable that the film density of the 1st insulating layer 4 and the 2nd insulating layer 5 is 60% or more. The film density is a filling rate of a substance constituting the insulating layer and indicates a ratio of holes. The larger the film density, the fewer the holes. When the film density is 60% or more, it becomes easy to obtain the effect of suppressing recombination of electrons and holes by the first insulating layer. The higher the film density, the easier it is to obtain the effect. Therefore, the film density is preferably 60% or more, more preferably 80% or more and 100% or less. Further, when the film density is low, current leakage may easily occur.

Note that the method for measuring the film density of the first insulating layer (and the second insulating layer) takes an arbitrary cross-section as an enlarged photograph, and distinguishes the material constituting the film from the holes by image analysis.
In addition, a method of measuring film density and film thickness by the X-ray reflectivity method (XRR) is also effective. XRR is preferable when the surface roughness Ra of the sample is a flat surface of several nm or less. When the reflectance intensity is measured, the reflectance intensity oscillates with respect to the scattering angle (2θ) due to X-ray interference. Fitting is performed using the measurement data as parameters for the film thickness, film density, and surface / interface roughness of each layer. As a theoretical formula of the fitting, a combination of a Parratt multilayer film model and a Nevot-Cross roughness formula is used. By examining values such as film thickness in advance using TEM and SEM, and using them as fitting parameters, the film density and the like can be measured more accurately.

The material of the first insulating layer 4 or the second insulating layer 5 is preferably one or more selected from metal oxides, metal nitrides, and insulating resins. The metal oxide is preferably one or more oxides (including complex oxides) selected from silicon, aluminum, tantalum, nickel, copper, and iron. The metal nitride is preferably one or more nitrides (including composite nitrides) selected from silicon and aluminum. Further, it may be a metal oxynitride. Further, an insulating resin may be used.
For the metal oxide film or the metal nitride film, various film formation methods such as a CVD method, a sputtering method, and a thermal spraying method can be applied. It is also effective to make the film formation atmosphere an oxygen-containing atmosphere to form an oxide film. Similarly, the film forming atmosphere may be a nitrogen-containing atmosphere to form a nitride film. Further, heat treatment may be added as necessary.

An electrode 6 is provided on the first insulating layer 4, and an electrode 7 is provided on the second insulating layer 5. There may be one electrode 6 or a plurality of electrodes 6. Similarly, one electrode 7 or a plurality of electrodes 7 may be provided. The electrodes 6 and 7 are preferably made of a metal material having good conductivity such as copper or aluminum. Moreover, transparent electrodes, such as ITO, may be sufficient.
The N-type semiconductor 2 and the P-type semiconductor 3 are preferably made of one kind selected from metal silicide, metal oxide, amorphous silicon, polycrystalline silicon, crystalline silicon, and single crystal silicon.
The N-type semiconductor 2 uses electrons as carriers. The P-type semiconductor 3 uses holes as carriers. By forming the PN junction type semiconductor layer, electrons and holes are accelerated by the electric field at the PN junction. When electrons and holes are accelerated, the rapid charge / discharge characteristics are improved and the power density is improved. In addition, since there is no insulating layer between the N-type semiconductor 2 and the P-type semiconductor 3, electrons and holes do not concentrate on the boundary of the PN junction. For this reason, the capacity can be increased.
In order to further increase the capacity, it is necessary to optimize the amount of electrons and holes in the semiconductor layer. Metal silicide, metal oxide, amorphous silicon, polycrystalline silicon, crystalline silicon, and single crystal silicon can easily control the amount of electrons or holes serving as carriers. Further, the amount of carriers in the N-type semiconductor 2 and the P-type semiconductor 3 can be controlled by doping impurities or introducing defects.

The metal silicide is preferably one selected from barium silicide (BaSi ₂ ), iron silicide (FeSi ₂ ), and magnesium silicide (MgSi ₂ ). The metal oxide includes tungsten oxide (WO ₃ ), molybdenum oxide (MoO ₂ , MoO ₃ ), titanium oxide (TiO ₂ ), tin oxide (SnO ₂ ), zinc oxide (ZnO ₂ ), nickel oxide (NiO ₂ ). ), Copper oxide (Cu ₂ O), and aluminum oxide (Al ₂ O ₃ ) are preferred.
Further, it is preferable that an N-type semiconductor or a P-type semiconductor has an electron or hole trap level introduced. The trapping order is an energy level for trapping electrons or holes, and is also called a trap level.

In addition, it is preferable that an N-type semiconductor or a P-type semiconductor has a large number of electron or hole trap levels introduced therein. The trap level is an energy level for trapping electrons or holes, and is also called a trap level. Moreover, it is preferable that a trap level exists in the range of 10 < ¹⁸ > cm ^{< -3} > ^-10 < ²² > cm ^{< -3} >. The trap level includes an impurity level and a defect level. An impurity level is a level obtained by substituting an element by doping impurities. It can be controlled by adjusting the doping amount of impurities. The defect level is a level generated by element deficiency. If it is a metal oxide, it is a level obtained by providing an oxygen deficiency.
Semiconductor conduction mechanisms include hopping conduction and band conduction. Hopping conduction indicates a state in which electrons are almost localized in a semiconductor, and electric conduction is carried out by jumping (hopping) between them one after another. In hopping conduction, the mean free process of electrons depends on the degree of interatomic distance (distance between impurity atoms in impurity conduction), and the electric conductivity is much smaller than that of free electrons. Contrasting behavior is shown. The hopping process is aided by thermal vibrations of the atoms. Further, “the electrons are almost in a localized state” indicates a state where electrons existing in the conduction band (conduction band) are present near the energy minimum point of the conduction band.
On the other hand, band conduction indicates a state where electrons (or holes) are electrically conducted in a relatively wide range (wide band region) in a semiconductor. Electrons (or holes) are generated when the semiconductor deviates from the stoichiometric composition.

A semiconductor made of a metal silicide or a metal oxide can control a level amount (position) and a conduction mechanism by impurity doping or defect introduction.
For example, in the case of metal silicide, impurity levels can be introduced by impurity doping. By introducing impurity levels, hopping conduction becomes dominant and carriers are easily stored in trap levels.
A metal oxide can introduce a defect level by providing an oxygen vacancy. By introducing the defect level, hopping conduction through the defect becomes dominant and carriers are easily accumulated in the trap level.
As described above, a semiconductor made of metal silicide or metal oxide has dominant hopping conduction by introducing impurity levels or defect levels. In other words, it can be said that those exhibiting hopping conduction characteristics are in a state where carriers are easily accumulated in the trap level.
As described above, hopping conduction becomes dominant in a semiconductor made of metal silicide or metal oxide by introducing a defect level. In other words, it can be said that those exhibiting hopping conduction characteristics are in a state where carriers are easily accumulated in the trap level.

In addition, the temperature dependence of the resistivity of a semiconductor made of metal silicide or metal oxide decreases when the hopping conduction characteristics become dominant. When resistivity is plotted on the vertical axis, 1000 / T is plotted on the horizontal axis, and T is temperature (K: Kelvin), the slope of the graph becomes gentler as the hopping conduction characteristics become dominant. On the other hand, when the band conduction becomes dominant, the slope of the graph increases. In other words, whether the hopping conduction or the band conduction is dominant can be determined based on the inclination angle of the graph when the graph of resistivity and 1000 / T is created. In particular, the slopes of the graphs with 1000 / T in the range of 2.8 to 4.0 are compared.
In addition, when the vertical axis represents resistivity and the horizontal axis represents 1 / T, the metal silicide exhibits a substantially linear or substantially parabolic behavior when exhibiting hopping conduction characteristics. Here, T is the Kelvin temperature.
As described above, metal oxides such as WO ₃ exhibit hopping conduction due to oxygen deficiency. Further, metal silicide such as BaSi ₂ exhibits hopping conduction due to impurity doping. By showing the hopping conduction characteristics, carriers can be easily stored in the trap level.

For hopping conduction, mainly NNH (Nearest Neighbor Hopping), Mott-type VBH (Mott-type variable-range), Shklovskii-type VBH (Shklovskii-type variable-range) : Cyclofusky type variable region hopping conduction). For example, WO ₃ exhibits NNH conductivity due to oxygen deficiency. On the other hand, BaSi ₂ exhibits Mott-type VBH conduction by doping with specific impurities (Ga, Al, Ag, Cu). When showing VBH conduction, the relational expression of lnρ∝T ^1/2 , which is its characteristic, and lnρ∝T ^1/4 , which is the characteristic of Shklovskii type VBH conduction (where ρ (Ω · cm) is resistivity, and T is (Indicates temperature during resistance measurement).
Here, when the semiconductor made of metal silicide or metal oxide has dominant hopping conduction characteristics, the resistivity is greatly reduced as compared with metal silicide without impurity doping (undoped) or metal oxide without oxygen deficiency. . By making the hopping conduction characteristic dominant, the resistivity can be greatly reduced.

The aforementioned barium silicide, iron silicide, magnesium silicide, tungsten oxide, and molybdenum oxide are semiconductors that easily store carriers in trap levels by introducing defect levels. Metal silicide is suitable for P-type semiconductors. Metal oxides are suitable for N-type semiconductors.
Amorphous silicon, polycrystalline silicon, crystalline silicon, and single crystal silicon can trap carriers at grain boundaries. Thereby, a trap level (capture level) can be introduced.
As described above, trapping levels of electrons and holes due to impurity doping, defects, and grain boundaries can be introduced. Moreover, these may be 1 type and may combine 2 or more types.

Moreover, the resistivity at normal temperature of tungsten oxide powder (WO ₃ ) is 10 ³ Ωcm or more. By making the hopping conduction characteristic dominant, the resistivity can be greatly reduced. The internal resistance can be reduced by decreasing the resistivity of the semiconductor. By reducing the internal resistance, the output density can be increased. This improves the quick charge / discharge performance of the battery.

Further, the impurity doping amount into the metal silicide is preferably within the range of 10 ¹⁸ cm ⁻³ to 10 ²² cm ⁻³ . Further, the impurity doping amount into amorphous silicon, polycrystalline silicon, crystalline silicon, and single crystal silicon is preferably within a range of 10 ¹⁸ cm ⁻³ to 10 ²² cm ⁻³ . In addition, various impurities such as Ag, Al, Cu, and Ga can be used as the impurity to be doped.
The impurity doping amount can be analyzed by SIMS (secondary ion mass spectrometry). It is also effective to create a calibration curve by preparing a plurality of standard samples with different impurity doping amounts. It is also effective to perform SIMS after an impurity element is specified in advance by XPS (X-ray photoelectric spectroscopy) or the like.

The oxygen deficiency is preferably in the range of 10 ¹⁸ cm ⁻³ to 10 ²² cm ⁻³ .
Here, oxygen deficiency indicates a state in which part of oxygen atoms constituting the crystal lattice does not exist in the crystal lattice of the material constituting the semiconductor. The carrier density indicates the abundance of electrons or holes (holes) serving as carriers. In the p-type semiconductor, the carrier is a hole, and in the n-type semiconductor, the carrier is an electron. The carrier density is obtained by the product of the density of states and the Fermi Dirac distribution function.
The oxygen deficiency indicates the amount of oxygen atoms missing from the crystal lattice, while the carrier density indicates the amount of electrons (or holes) present. Oxygen defects and carrier density are different parameters. When hopping conduction is shown, a polaron is formed by lattice strain accompanying conduction of oxygen defects and conduction electrons. Polaron causes a conduction mechanism. Therefore, the oxygen vacancy amount and the carrier density can be made substantially the same value by showing the hopping conduction characteristics.
For this reason, in the case of a semiconductor in which hopping conduction is dominant, the amount of defects can be obtained by measuring the carrier density. The carrier density can be measured by SMM or SCM. SMM stands for Scanning Microwave Microscopy. SCM stands for Scanning Capacitance Microscopy.

  For the measurement of the impurity doping amount, a method of comparing the intensity of the modulation signal (dC / dV) and the microwave reflectance using a standard sample doped with a predetermined impurity amount is preferable. At this time, it is effective to prepare a plurality of standard samples with different dope amounts and prepare a calibration curve. It is also effective to specify the impurity doping material beforehand by XPS or the like. When measuring with SMM or SCM, the sample surface is mirror-polished (surface roughness Ra 0.1 μm or less).

Further, the amount of grain boundary can be controlled by adjusting the crystal size. The average crystal grain size is preferably in the range of 50 nm to 1000 nm. When the average crystal grain size is less than 50 nm, the number of grain boundaries increases, and electrons and holes are trapped too much during the movement, and the mobility is considered to decrease. A decrease in mobility leads to a decrease in power density. When the average crystal grain size exceeds 1000 nm (1 μm), the effect of improving the battery capacity (energy density) is small because the grain boundary trapping effect is small. In order to achieve both energy density and power density, the average crystal grain size is preferably in the range of 50 nm to 1000 nm.
The thicknesses of the N-type semiconductor 3 and the P-type semiconductor 4 are not particularly limited, but are preferably 0.1 μm or more and 500 μm or less. If the thickness of the semiconductor is as thin as less than 0.1 μm (100 nm), the amount of carriers generated is small, and it may be difficult to increase the electric capacity. On the other hand, if the thickness exceeds 500 μm, the moving distance of the carrier becomes long, so that the rapid charge / discharge characteristics may be deteriorated. The electric capacity is indicated by energy density (Wh / kg). The rapid charge / discharge characteristics are indicated by power density (W / kg).

Further, instead of the above-described PN junction type semiconductor layer, an N-type semiconductor single layer or a P-type semiconductor single layer may be used. FIG. 2 shows a schematic diagram of a semiconductor solid state battery having a semiconductor single layer structure composed of an N-type semiconductor single layer or a P-type semiconductor single layer. In the figure, 8 is a semiconductor solid state battery (second semiconductor solid state battery), 9 is a semiconductor, 4 is a first insulating layer, 5 is a second insulating layer, 6 is an electrode, and 7 is an electrode. The semiconductor 9 having either N-type or P-type structure is referred to as a second semiconductor solid battery.
The second semiconductor solid battery has a structure in which either the N-type or P-type semiconductor 9 is sandwiched between the first insulating layer 4 and the second insulating layer 5. The first insulating layer 4 and the second insulating layer 5 are preferably the same as described above.
Even if the semiconductor 9 is an N-type or P-type single layer, a tunnel effect can be obtained by providing an insulating layer. In addition, since the second semiconductor solid state battery does not have an insulating layer in the semiconductor layer like the first semiconductor solid state battery, electrons and holes do not concentrate in the central portion. As a result, the capacity can be increased.

Further, since the semiconductor 9 is an N-type or P-type single layer, electrons and holes can be stored in the same semiconductor layer. Thereby, since the Fermi level (pseudo Fermi level) of an electron and a hole changes a lot, it is possible to increase the capacity and the voltage. It is considered that the charging voltage is generated because the Fermi level (pseudo Fermi level) of electrons and holes changes from the thermal equilibrium state due to carrier accumulation. If holes that are minority carriers can be stored in the N-type semiconductor, the change in the pseudo-Fermi level can be increased. Similarly, if electrons that are minority carriers can be stored in a P-type semiconductor, the change in the pseudo-Fermi level can be increased.
Such an effect of increasing the quasi-Fermi level change can also be applied to the first semiconductor solid state battery. Usually, an N-type semiconductor has many donor-like impurity levels (or defect levels), and a P-type semiconductor has many acceptor-like impurity levels (or defect levels). If a donor-like trap level is introduced into a P-type semiconductor and an acceptor-like trap level is introduced into an N-type semiconductor so that more electrons can be accumulated in the P-type semiconductor and more holes in the N-type semiconductor, the change in pseudo-Fermi is more It is thought to grow.

The semiconductor 9 is preferably made of one kind selected from metal silicide, metal oxide, amorphous silicon, polycrystalline silicon, crystalline silicon, and single crystal silicon. As described above, the trap level can be easily introduced by introducing impurities, defects, and grain boundaries. Moreover, it is easy to control the amount of electrons or holes. Similarly, it is a material that easily imparts hopping conduction characteristics.
The thickness of the semiconductor 9 is not particularly limited, but is preferably 0.1 μm or more and 500 μm or less. If the thickness of the semiconductor is as thin as less than 0.1 μm (100 nm), the amount of carriers generated is small, and it may be difficult to increase the electric capacity. On the other hand, if the thickness exceeds 500 μm, the moving distance of the carrier becomes long, so that the rapid charge / discharge characteristics may be deteriorated.

Next, the operation will be described. FIG. 3 shows an outline of the movement of carriers (electrons or holes) in the first semiconductor solid state battery. In FIG. 3, 1 is a semiconductor solid state battery, 2 is an N-type semiconductor, 3 is a P-type semiconductor, 4 is a first insulating layer, 5 is a second insulating layer, 6 is an electrode (N-type side electrode), 7 is Electrodes (P-type side electrodes), 10 are electrons, 11 are holes, and 12 is a power source. FIG. 3 is a conceptual diagram of the band of the first semiconductor solid state battery, where the vertical direction indicates the energy level and the horizontal direction indicates the distance.
When electricity flows from the power supply 12, electrons 10 are generated in the N-type semiconductor 2 and holes 11 are generated in the P-type semiconductor 3. Electrons 10 and holes 11 serving as carriers accumulate. By accumulating carriers, the battery is charged. Since the 1st semiconductor solid battery is provided with the 1st insulating layer 4 and the 2nd insulating layer 5, it can acquire a tunnel effect, respectively. Thereby, the capacity can be increased.
The first semiconductor solid state battery has a PN junction type semiconductor layer. Since electrons and holes are accelerated by the electric field at the PN junction, the output density is improved. In addition, since there is no insulating layer between the N-type semiconductor 2 and the P-type semiconductor 3, electrons and holes do not concentrate on the boundary of the PN junction. Furthermore, the capacity can be increased.

  In addition, since hopping conduction characteristics are introduced, carriers are easily collected in the trap level. In addition, a PN junction such as the first semiconductor solid battery has a negative electric field on the P-type semiconductor side and a positive electric field on the N-type semiconductor side. Thereby, a lot of electrons accumulate near the insulating layer 4 in the N-type semiconductor. Further, it is considered that many holes are accumulated near the insulating layer 5 in the P-type semiconductor. Further, since the first insulating layer 4 and the second insulating layer 5 are provided, the leakage current is reduced because the semiconductor and the electrode are not in direct contact.

FIG. 4 shows an outline of the movement of carriers (electrons or holes) in the second semiconductor solid state battery. In FIG. 4, 8 is a semiconductor solid state battery, 4 is a first insulating layer, 5 is a second insulating layer, 6 is an electrode, 7 is an electrode, 9 is a semiconductor, 10 is an electron, 11 is a hole, and 12 is a power source. . FIG. 4 is a conceptual diagram of the band of the second semiconductor solid state battery, where the vertical direction indicates the energy level and the horizontal direction indicates the distance.
When electricity flows from the power supply 12, electrons 10 and holes 11 are generated in the semiconductor 9. Electrons 10 and holes 11 serving as carriers accumulate. By accumulating carriers, the battery is charged. Since the second semiconductor solid state battery is provided with the first insulating layer 4 and the second insulating layer 5, the leakage current is reduced because the semiconductor and the electrode are not in direct contact.
The semiconductor 9 is either N-type or P-type. Both electrons 10 and holes 11 are present in the semiconductor 9. Thereby, the change of the pseudo-Fermi level can be increased, and the capacity can be further increased. This is because, due to the electric field of the voltage applied at the time of charging, electrons are collected near the insulating layer on the positive side of the applied voltage, and holes are considered to be stored near the insulating layer on the negative side during charging.

As described above, the first semiconductor solid battery and the second semiconductor solid battery are provided with the first insulating layer and the second insulating layer, so that the semiconductor layer and the electrode are not in direct contact with each other, so that the leakage current is reduced. be able to.
Further, by optimizing the semiconductor layers (N-type semiconductor 2, P-type semiconductor 3, and semiconductor 9), the capacity can be further increased and the rapid charge / discharge characteristics can be improved. If the capacity can be increased, the energy density can be 100 Wh / kg or more, and further 200 Wh / kg or more. Further, the output density can be set to 1000 W / kg or more, further 1200 W / kg or more.
If it is the above semiconductor solid state batteries, the secondary battery excellent in energy density and output density can be provided. Moreover, since it is not necessary to use an electric field liquid like the conventional Li ion secondary battery, the malfunction of a liquid leak does not generate | occur | produce.

Next, a manufacturing method will be described. If the semiconductor solid battery concerning embodiment has the above-mentioned composition, the manufacturing method will not be limited, but the following is mentioned as a method for obtaining efficiently.
An electrode is formed on the substrate. Next, a first insulating layer (or a second insulating layer) is formed as necessary.
Next, an N-type semiconductor (or P-type semiconductor) is formed. When producing the first semiconductor solid state battery, a P-type semiconductor (or N-type semiconductor) is formed to form a PN junction.
Next, a second insulating layer (or first insulating layer) and an electrode are formed. Note that either the N-type semiconductor or the P-type semiconductor may be formed first.
As a film formation method, various evaporation methods such as a CVD method and a sputtering method can be applied. In the film forming step, the substrate may be heated as necessary. Moreover, Ar atmosphere, a vacuum atmosphere, etc. shall be adjusted suitably.
When an oxide film or a nitride film is formed, an atomic layer deposition method (ADL), a thermal oxidation method (heat treatment in an oxidizing atmosphere), a thermal nitridation method (heat treatment in a nitriding atmosphere), or the like may be used. .
In addition, when impurity doping is performed in the semiconductor layer deposition step, a method of co-depositing impurity elements is effective. By adjusting the rate of simultaneous vapor deposition, the impurity doping amount, that is, the impurity level amount can be controlled. Moreover, you may dope 2 or more types of impurities as needed. Different impurity levels can be introduced by doping two or more kinds of impurities.

In the case of providing oxygen vacancies, it is effective to perform a heat treatment in a reducing atmosphere after forming the semiconductor layer. In the case of a metal oxide semiconductor layer, heat treatment is preferably performed at a temperature of 600 ° C. or higher in a mixed gas of hydrogen and nitrogen. In the case of a metal oxide semiconductor layer, necking firing is performed after film formation as necessary. Moreover, necking baking may be performed in a reducing atmosphere, and the process of providing necking and oxygen deficiency may be combined.
In the case where oxygen vacancies are provided, a vapor deposition step may be performed after the metal oxide powder is heat-treated in a reducing atmosphere.
In order to adjust the amount of grain boundaries, it is preferable to control heating during film formation, film formation rate, heat treatment in a subsequent process, and the like. By controlling these, the average crystal grain size can be controlled.

(Example)
(Examples 1-7)
A P-type BaSi ₂ layer was prepared as a P-type semiconductor. In addition, an N-type WO ₃ layer was prepared as an N-type semiconductor. It was also prepared SiO ₂ layer as the first insulating layer and the second insulating layer.
In addition, the P-type BaSi ₂ layer was prepared by changing the impurity doping amount and the grain boundary amount. The thickness of the P-type BaSi ₂ layer was unified to 0.5 μm (500 nm). In addition, the N-type WO ₃ layer was prepared by changing the oxygen deficiency amount and the grain boundary amount. The thickness of the N-type WO ₃ layer was unified to 0.5 μm (500 nm). This adjusted the introduction of trap levels and the presence or absence of hopping conduction characteristics.
The first insulating layer and the second insulating layer were prepared by changing the film thickness by changing the sputtering conditions for SiO ₂ . The film density of the SiO ₂ film was unified to 95% and the relative dielectric constant was 3.8.
An Al electrode was provided as an electrode. Thus, a semiconductor solid battery having the structure shown in Table 1 was produced.
Examples 1 to 3 relate to the first semiconductor solid state battery, and Examples 4 to 8 relate to the second semiconductor solid state battery.

(Example 9 to Example 15)
In the semiconductor solid state batteries according to Examples 2 to 6, batteries having different trap level densities and average crystal grain sizes of the semiconductor layers as shown in Table 2 were prepared. It was set as Examples 8-15, respectively.

(Examples 16 to 20)
A P-type β-FeSi ₂ layer was prepared as a P-type semiconductor. In addition, an N-type WO ₃ layer was prepared as an N-type semiconductor. In addition, Si ₃ N ₄ layers were prepared as the first insulating layer and the second insulating layer.
In addition, the P-type β-FeSi ₂ layer was prepared by changing the impurity doping amount and the grain boundary amount. The thickness of the P-type β-FeSi ₂ layer was unified to 0.3 μm (300 nm). The N-type WO3 layer was prepared by changing the oxygen deficiency amount and the grain boundary amount. The thickness of the N-type WO ₃ layer was unified to 0.3 μm (300 nm). This adjusted the introduction of trap levels and the presence or absence of hopping conduction characteristics.
The first insulating layer and the second insulating layer were prepared by changing the film thickness by changing the sputtering conditions of Si ₃ N ₄ . The film density of the Si ₃ N ₄ film was unified to 93% and the relative dielectric constant was 7.5.
An Al electrode was provided as an electrode. As a result, a semiconductor solid battery having the structure shown in Table 3 was produced.
Examples 16 to 18 relate to the first semiconductor solid state battery, and Examples 19 to 20 relate to the second semiconductor solid state battery.

For the semiconductor solid state batteries according to Examples 1 to 15, the energy density and the output density were measured.
In order to measure the energy density, a charge / discharge test was performed in a voltage range of 1.0 V to 2.0 V using a charge / discharge device. Charging was first performed in the constant current mode, and when 2.0V was reached, the mode shifted to the 2.0V constant voltage mode, and charging was continued until the amount of current decreased to a constant value. After charging, the battery was discharged at a constant current, and the energy density (electric capacity) of the semiconductor solid battery was determined from the electric capacity at the time of discharging.
The power density (W / kg) was determined by _{0.25 × (V 2 -V 1)} / R / cell weight formula. V ₂ is the discharge start voltage, V ₁ is the discharge end voltage, R is the cell resistance (cell electrode area 2903 cm ² ), and the cell weight is 120 g. The results are shown in Table 4.

  As shown in the table, the energy density and output density of the semiconductor solid state battery according to the example were improved. Further, by controlling the first insulating layer and the second insulating layer, the energy density could be 60 Wh / kg or more and the output density 600 W / kg or more. Further, the characteristics were further improved by introducing trap levels and hopping conduction into the semiconductor layer. In addition, there is no fear of liquid leakage because it is not necessary to use an electric field liquid unlike a Li ion secondary battery.

  As mentioned above, although several embodiment of this invention was illustrated, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, and the like can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.

1. Semiconductor solid state battery (first semiconductor solid state battery)
2 ... N-type semiconductor 3 ... P-type semiconductor 4 ... First insulating layer 5 ... Second insulating layer 6 ... Electrode (N-type side electrode)
7 ... Electrode (P-type side electrode)
8. Semiconductor solid state battery (second semiconductor solid state battery)
9 ... Semiconductor 10 ... Electron 11 ... Hole 12 ... Power supply

Claims (7)

  A semiconductor solid comprising a semiconductor layer made of any one of an N-type semiconductor single layer, a P-type semiconductor single layer, and a PN junction type semiconductor layer, and an electrode provided on the semiconductor layer via an insulating layer battery.   2. The semiconductor solid state battery according to claim 1, wherein the insulating layer has a thickness of 30 nm or less and a relative dielectric constant of 10 or less.   The semiconductor solid battery according to claim 1, wherein the insulating layer has a film density of 60% or more.   4. The semiconductor layer according to claim 1, wherein the semiconductor layer is made of one selected from metal silicide, metal oxide, amorphous silicon, polycrystalline silicon, crystalline silicon, and single crystal silicon. 5. Semiconductor solid state battery.   5. The semiconductor solid state battery according to claim 1, wherein an N-type semiconductor or a P-type semiconductor introduces a trap level of electrons or holes.   The semiconductor solid-state battery according to any one of claims 1 to 4, wherein the semiconductor layer has introduced a trap level of electrons or holes.   The semiconductor solid state battery according to any one of claims 1 to 6, wherein the semiconductor layer has a hopping conduction mechanism.

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