JP2018196007A - Demodulation circuit and modulation circuit of digitally modulated signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a demodulation circuit and a modulation circuit capable of simplifying circuit elements for synchronous reproduction. A demodulator circuit includes a clock source 30 that generates a fixed frequency clock signal, an AD converter 1 that A-D converts an input signal of an analog signal with a clock signal generated by the clock source 30, and A. The orthogonal demodulator 12 that orthogonally demolishes the −D converted input signal, the downsampler 14 that downsamples the output signal of the orthogonal demodulator 12, and the demodulator processing unit 16 that performs demographic processing on the downsampled signal. A phase control unit 18 for controlling the downsampling device 14 to perform downsampling at the timing when the opening of the eye pattern of the demodulated signal is maximized is provided. [Selection diagram] FIG. 4

Description

  The present invention relates to a demodulation circuit and a modulation circuit for a signal digitally modulated by a modulation method such as QAM.

  As a modulation method, QAM (Quadrature Amplitude Modulation) is used in the field of wireless communication, optical communication, and the like. In this specification, QAM means multi-value QAM such as 16-value QAM and 64-value QAM.

  As a modulation circuit that performs modulation by QAM, there is a modulation circuit configured to upsample an input signal (baseband signal) that has been subjected to digital modulation processing. Further, there is a demodulation circuit configured to downsample a signal before being subjected to digital demodulation processing (see, for example, Patent Document 1).

  In the demodulation circuit described in Patent Document 1, the amplitudes of the I (In-phase) signal and the Q (Quadrature) signal before down-sampling are measured at different timings (a plurality of cycles with n times as one cycle). Measurement timing is stored, and the timing at which the plurality of amplitude values are substantially aligned is determined as the downsampling timing.

  In addition, there is a demodulation circuit that uses a timing at which the eye pattern opening is maximized as a control value (see, for example, Patent Document 2). In the demodulation circuit described in Patent Document 2, the delay detector is controlled based on the control value.

JP 2006-166005 A Japanese Patent Laying-Open No. 2015-95744

  However, Patent Document 1 includes only the technical idea of determining the timing of downsampling based on the amplitudes of the I signal and the Q signal (the signal on the input side of the downsampling circuit). From the description, it is not possible to recall a demodulation circuit that determines the timing of downsampling based on the eye pattern as described in Patent Document 2.

  FIG. 6 is a block diagram showing a configuration example of a general demodulation circuit for comparison with the demodulation circuit and the modulation circuit according to the present invention.

  The demodulation circuit shown in FIG. 6 includes an analog-to-digital converter (ADC) 1 that converts an IF signal into a digital signal, a band-pass filter (BPF) 11 that passes a necessary frequency component from the output of the ADC 1, and a BPF 11. A quadrature demodulator 12 that converts the passed signal into baseband signals (I and Q signals), low-pass filters (LPF) 13I and 13Q that remove unnecessary frequency components from the I and Q signals, and downsample the baseband signals. Down-samplers (D / S) 14I and 14Q, a demodulation processing unit 16 that performs demodulation processing based on the QAM scheme for baseband signals, and a decoding processing unit 17 that performs predetermined signal processing are included. Note that the predetermined signal processing includes, for example, error correction decoding processing.

  The demodulation circuit includes a voltage controlled crystal oscillator (VCXO) 6 that generates a clock signal used for sampling in the ADC 1, an LPF 7 that smoothes the voltage control signal of the VCXO 6, and voltage control. A D / A converter (DAC) 8 that converts the signal into an analog signal, a clock phase control unit 20 for controlling the phase of the clock signal based on the processing result of the demodulation processing unit 16, and a PLL circuit 19 are included.

  Note that the clock phase control unit 20 uses, for example, the reference symbol demapped by the demodulation processing unit 16 to correct the carrier phase shift (corresponding to the difference between the received carrier wave and the frequency of the local oscillation signal). I do. Also, the PLL circuit 19 generates a clock signal having a frequency used by each processing unit in the demodulation circuit shown in FIG. 6 based on the clock signal output from the VCXO 6.

  Each processing unit other than the ADC 1, the VCXO 6, the LPF 7, and the DAC 8 can be relatively easily integrated on one LSI (for example, an FPGA (Field Programmable Gate Array)).

  Assume that each processing unit other than ADC1, VCXO6, LPF7, and DAC8 is configured with an FPGA. In that case, for example, in particular, in a configuration in which a transmission signal from a modulation circuit to be described later is coupled and monitored, it is required to install two systems of LPFs and VCXOs, so that the amount of circuit elements increases.

  An object of the present invention is to provide a demodulation circuit and a modulation circuit that can simplify circuit elements for synchronous reproduction.

  The demodulation circuit according to the present invention includes a clock source that generates a clock signal having a fixed frequency, an A / D converter that performs A / D conversion on an analog signal input signal using the clock signal generated by the clock source, and A / D conversion. A quadrature demodulator that orthogonally demodulates the input signal, a downsampler that downsamples the output signal of the quadrature demodulator, a demodulation processor that demodulates the downsampled signal, and an eye pattern opening of the demodulated signal. And a phase control unit that controls the down-sampling device to perform down-sampling at the maximum timing.

  A modulation circuit according to the present invention includes a clock source that generates a clock signal having a fixed frequency, a modulation processing unit that performs modulation processing on an input signal of a digital signal, an upsampler that upsamples an output signal of the modulation processing unit, Based on a quadrature modulation unit that quadrature-modulates the sampled signal, a D / A converter that D / A-converts the output signal of the quadrature modulation unit with a clock signal generated by a clock source, and an output of the D / A converter A monitoring circuit that monitors the modulation process, and the monitoring circuit performs analog-to-digital conversion on an analog signal input signal using a clock signal generated by a clock source; and an analog-to-digital input signal A quadrature demodulator that performs quadrature demodulation, a downsampler that downsamples the output signal of the quadrature demodulator, and the downsampled signal Including tone processing and demodulation processing unit which performs, and a phase control unit that down-sampler is controlled to perform the down-sampling at the timing when the opening is maximized the eye pattern of the demodulated signal.

  According to the present invention, circuit elements for synchronous reproduction can be simplified.

It is a block diagram which shows the structural example of a demodulation circuit. It is explanatory drawing which shows an example of the eye pattern of a received signal, and the sampling timing of ADC. It is a block diagram which shows the structural example of a modulation circuit. It is a block diagram which shows the principal part of a demodulation circuit. It is a block diagram which shows the principal part of a modulation circuit. It is a block diagram which shows the structural example of a general demodulation circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1. FIG.
FIG. 1 is a block diagram illustrating a configuration example of a demodulation circuit which is a first embodiment of a modem circuit.

  The demodulator circuit shown in FIG. 1 converts an IF signal of a signal modulated by QAM that is an analog signal into a digital signal, BPF11 that passes a necessary frequency component from the output of ADC1, ADC1, and a signal that has passed through BPF11 as a baseband signal Quadrature demodulator 12 for converting to (I signal and Q signal), LPFs 13I and 13Q for removing unnecessary frequency components for I and Q signals, D / S 14I and 14Q for downsampling baseband signals, and downsampled basebands A phase correction unit 15 that corrects the rotational phase of the signal, a demodulation processing unit 16 that performs demodulation processing based on the QAM method for the baseband signal, a decoding processing unit 17 that performs predetermined signal processing, and downsampling of D / S 14I and 14Q Control timing and correct rotation phase of baseband signal A phase control unit 18 for the control eyes.

  The demodulation circuit includes a temperature compensated crystal oscillator (TCXO) 2 that generates a clock signal used for sampling in the ADC 1 and a PLL circuit 19. Note that an element or a circuit other than the TCXO may be used as an element or a circuit that generates a clock signal.

  In the present embodiment, the BPF 11, the quadrature demodulation unit 12, the LPFs 13I and 13Q, the D / S 14I and 14Q, the phase correction unit 15, the demodulation processing unit 16, the decoding processing unit 17, the phase control unit 18, and the PLL circuit 19 are included in the FPGA 10A. Is formed.

  The PLL circuit 19 generates a clock signal having a frequency used by each processing unit formed in the FPGA 10A based on the clock signal output from the TCXO2.

  The operations of the BPF 11, the quadrature demodulation unit 12, the LPFs 13I and 13Q, the D / S 14I and 14Q, the demodulation processing unit 16, the decoding processing unit 17, and the PLL circuit 19 are the same as those shown in FIG.

  Next, the operation of the demodulation circuit will be described.

  The TCXO2 generates a clock signal having a frequency that is an integral multiple of the symbol rate. In the present embodiment, it is assumed that the frequency of the clock signal generated by the TCXO 2 is 12 times the symbol rate as shown in FIG. FIG. 2 also illustrates an eye pattern of the received signal.

  The ADC 1 is a clock signal generated by the TCXO 2 and AD-converts the IF signal. The A / D converted IF signal is input to the FPGA 10A.

  In the FPGA 10A, the BPF 11 removes unnecessary signals outside the signal band. The quadrature demodulator 12 orthogonally transforms the IF signal that has passed through the BPF 11 to obtain a baseband signal (I signal and Q signal). LPFs 13I and 13Q remove unnecessary components from the I and Q signals after downsampling.

  The D / S 14I and 14Q downsample the I signal and the Q signal. The sampling timing is the timing at which the eye pattern opening is maximized. In the example shown in FIG. 2, the time point “7” is the sampling timing.

  The phase control unit 18 can recognize the eye pattern from the processing result of the demodulation processing unit 16. The phase control unit 18 detects the timing at which the eye pattern opening is maximized, and notifies the timing to the D / S 14I and 14Q. The D / S 14I and 14Q adjust the sampling timing according to the notification from the phase control unit 18.

  Note that phase rotation occurs when a phase shift of less than the sampling period occurs during downsampling in D / S 14I and 14Q. The phase control unit 18 calculates a phase error from the processing result of the demodulation processing unit 16. The phase control unit 18 outputs the calculated phase error to the phase correction unit 15.

  Phase rotation is compensated by multiplying the phase correction unit 15, for example, the I signal and the Q signal by a phase error.

  The demodulation processing unit 16 performs demodulation processing on the baseband signal, and the decoding processing unit 17 performs predetermined signal processing.

  As described above, in the demodulation circuit of the present embodiment, the function of performing synchronous reproduction is implemented in the FPGA 10A. The ADC 1 provided outside the FPGA 10A performs A / D conversion using a clock signal having a fixed frequency generated by the TCXO2. Therefore, compared with the demodulation circuit illustrated in FIG. 6, a hardware circuit (in the configuration illustrated in FIG. 6, ADC 1, VCXO 6, LPF 7, and the like) that is not realized by the FPGA (portion surrounded by a dotted line in FIG. 6). The configuration of the DAC 8) is simplified.

Embodiment 2. FIG.
FIG. 3 is a block diagram illustrating a configuration example of a modulation circuit which is a second embodiment of the modem circuit. The modulation circuit shown in FIG. 3 includes a monitoring circuit for monitoring the operating state of the modulation circuit.

  The modulation circuit shown in FIG. 3 includes an encoding processing unit 21 that encodes an input signal, a modulation processing unit 22 that generates a baseband signal (I signal and Q signal) by QAM modulating the output of the encoding processing unit 21, Up-samplers (U / S) 23I and 23Q for up-sampling I and Q signals, low-pass filters (LPF) 24I and 24Q for removing out-of-band signals of the up-sampled baseband signals, and baseband signals as IF signals A quadrature modulation unit 25 for converting the digital signal into an analog signal, a D / A converter (DAC) 3 for converting the digital signal into an analog signal, a TCXO 2 for generating a fixed frequency reference clock signal, and an analog signal output by the DAC 3 A directional coupler 4 for distributing the IF signal is included.

  The modulation circuit further includes ADC 1, BPF 11, quadrature demodulation unit 12, LPF 13 I, 13 Q, D / S 14 I, 14 Q, phase correction unit 15, demodulation processing unit 16, decoding processing unit 17, and phase control shown in FIG. A monitoring circuit including the unit 18 is provided.

  The encoding processing unit 21, the modulation processing unit 22, U / S 23I, 23Q, LPF 24I, 24Q, quadrature modulation unit 25, BPF 11, quadrature demodulation unit 12, LPF 13I, 13Q, D / S 14I, 14Q, phase correction unit 15, The demodulation processing unit 16, the decoding processing unit 17, and the phase control unit 18 are formed in the FPGA 10B.

  Further, the FPGA 10B is formed with a PLL circuit 19 that generates a clock signal having a frequency used by each processing unit formed in the FPGA 10B based on the clock signal output from the TCXO2.

  The ADC 1 inputs the IF signal distributed by the directional coupler 4. The ADC 1 performs A / D conversion using a clock signal generated by the TCXO 2 provided in the modulation circuit.

  The operation of other elements in the monitoring circuit is the same as the operation of each element in the demodulation circuit shown in FIG.

  Next, the operation of the modulation circuit will be described. The encoding processing unit 21 performs encoding processing such as error correction on the input signal. The modulation processing unit 22 generates an IF signal by performing modulation processing based on a QAM scheme such as symbol mapping.

  The U / S 23I and 23Q upsample the I signal and the Q signal. The LPFs 24I and 24Q remove unnecessary bands of the upsampled I and Q signals. The quadrature modulation unit 25 converts the baseband signal into an IF signal. The DAC 3 converts the IF signal of the digital signal into an analog signal using a fixed frequency clock signal generated by the TCXO 2.

  As shown in FIG. 3, the clock signal generation source (clock source) used by the ADC 1 in the monitoring circuit is the same as the clock signal clock source used by the DAC 3 in the modulation circuit. That is, even if the monitoring circuit is formed in the FPGA 10B, the scale of the hardware circuit outside the FPGA 10B does not increase.

  In each of the above embodiments, a modulation / demodulation circuit that performs single-carrier QAM modulation / demodulation has been illustrated, but the present invention may be applied to a modulation / demodulation circuit that performs orthogonal modulation / demodulation and synchronous reproduction other than the QAM modulation / demodulation circuit.

  FIG. 4 is a block diagram showing the main part of the demodulation circuit. The demodulation circuit includes a clock source 30 (for example, TCXO2) that generates a clock signal having a fixed frequency, an A / D converter 1 that performs A / D conversion on an analog signal input signal using the clock signal generated by the clock source 30, and A quadrature demodulator 12 that orthogonally demodulates an input signal that has been A / D converted, a downsampler 14 that downsamples an output signal of the quadrature demodulator 12 (for example, D / S 14I and 14Q), and a downsampled signal A demodulation processing unit 16 that performs demodulation processing, and a phase control unit 18 that controls the down-sampling device 14 to perform down-sampling at the timing when the eye pattern opening of the demodulated signal is maximized are provided.

  A phase correction unit 15 that compensates for the phase rotation of the downsampled signal is provided. The phase control unit 18 calculates a phase error from the processing result of the demodulation processing unit 16, and the phase correction unit 15 performs phase correction according to the phase error. It is preferable to compensate for the rotation.

  The quadrature demodulator 12, downsampler 14, phase corrector 15, demodulator 16 and phase controller 18 are formed in the FPGA 10A, and the clock source 30 and AD converter 1 are formed outside the FPGA 10A. It is preferable.

  FIG. 5 is a block diagram showing the main part of the modulation circuit. The modulation circuit includes a clock source 30 (for example, TCXO2) that generates a fixed-frequency clock signal, a modulation processing unit 22 that performs modulation processing on an input signal of a digital signal, and an up-sampling of an output signal of the modulation processing unit 22 The sampler 23 (for example, U / S 23I, 23Q), the quadrature modulation unit 25 that quadrature modulates the upsampled signal, and the output signal of the quadrature modulation unit 25 is D / A converted by a clock signal generated by the clock source 30. And a monitoring circuit 31 that monitors the modulation processing based on the output of the DA converter 3. The monitoring circuit 31 generates an input signal of an analog signal by the clock source 30. An A / D converter 1 that performs A / D conversion using a clock signal, a quadrature demodulation unit 12 that performs quadrature demodulation on the A / D converted input signal, and a quadrature demodulation unit 1 Down-sampler 14 (eg, D / S 14I, 14Q) for down-sampling the output signal, demodulation processing unit 16 for demodulating the down-sampled signal, and timing at which the eye pattern opening of the demodulated signal is maximized And the phase control unit 18 that controls the down-sampling unit 14 to perform down-sampling.

  The modulation processing unit 22, the upsampling unit 23, the quadrature modulation unit 25, the quadrature demodulation unit 12, the downsampling unit 14, the phase correction unit 15, the demodulation processing unit 16, and the phase control unit 18 are formed in the FPGA 10B, and the clock source 30, It is preferable that the DA converter 3 and the AD converter 1 are formed outside the FPGA 10B.

1 A-D converter (ADC)
2 Temperature compensated crystal oscillator (TCXO)
3 DA converter (DAC)
10A, 10B FPGA
11 Bandpass filter (BPF)
12 Quadrature demodulator 13I, 13Q Low-pass filter (LPF)
14 Downsampler 14I, 14Q Downsampler (D / S)
DESCRIPTION OF SYMBOLS 15 Phase correction part 16 Demodulation process part 17 Decoding process part 18 Phase control part 19 PLL circuit 21 Encoding process part 22 Modulation process part 23 Upsampler 23I, 23Q Upsampler (U / S)
24I, 24Q Low-pass filter (LPF)
25 Quadrature modulation unit 30 Clock source 31 Monitoring circuit

Claims (7)

A clock source for generating a fixed frequency clock signal;
An analog-to-digital converter that analog-to-digital converts an input signal of an analog signal with a clock signal generated by the clock source;
An orthogonal demodulator that orthogonally demodulates an input signal that has undergone A-D conversion;
A downsampler for downsampling the output signal of the quadrature demodulator;
A demodulation processing unit that performs demodulation processing on the downsampled signal;
And a phase control unit that controls the down-sampling device to perform down-sampling at a timing at which the eye pattern opening of the demodulated signal is maximized. A phase correction unit that compensates for the phase rotation of the downsampled signal is provided.
The phase control unit calculates a phase error from the processing result of the demodulation processing unit,
The demodulation circuit according to claim 1, wherein the phase correction unit compensates for phase rotation according to the phase error. The quadrature demodulator, downsampler, phase corrector, demodulation processor, and phase controller are formed in the FPGA.
The demodulation circuit according to claim 2, wherein the clock source and the AD converter are formed outside the FPGA. The demodulation circuit according to any one of claims 1 to 3, wherein the demodulation processing unit performs a demodulation process on a signal modulated by the QAM method. A clock source for generating a fixed frequency clock signal;
A modulation processing unit that performs modulation processing on an input signal of a digital signal;
An upsampler for upsampling the output signal of the modulation processing unit;
A quadrature modulation unit that quadrature modulates the upsampled signal;
A DA converter that DA converts an output signal of the quadrature modulation unit with a clock signal generated by the clock source;
A monitoring circuit for monitoring modulation processing based on the output of the DA converter,
The monitoring circuit is
An analog-to-digital converter that analog-to-digital converts an input signal of an analog signal with a clock signal generated by the clock source;
An orthogonal demodulator that orthogonally demodulates an input signal that has undergone A-D conversion;
A downsampler for downsampling the output signal of the quadrature demodulator;
A demodulation processing unit that performs demodulation processing on the downsampled signal;
A phase control unit that controls the down-sampling device to perform down-sampling at a timing when the eye pattern opening of the demodulated signal is maximized. The modulation processing unit, upsampler, quadrature modulation unit, quadrature demodulation unit, downsampler, phase correction unit, demodulation processing unit and phase control unit are formed in the FPGA,
The modulation circuit according to claim 5, wherein the clock source, the DA converter, and the AD converter are formed outside the FPGA. The modulation processing unit performs modulation processing by the QAM system,
The modulation circuit according to claim 5, wherein the demodulation processing unit in the monitoring circuit performs demodulation processing of a signal modulated by the QAM method.

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