JP2018190773A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that allows for easy and successful positioning in an electrical test, and a method of manufacturing the same.SOLUTION: A semiconductor device according to one embodiment includes: a plurality of chip regions 10; and a scribe region 20 that includes a reference mark 25 between the plurality of chip regions 10. The reference mark 25 has a first region 21 and a second region 22 directly contacted with each other. A part where a reflective index to visible light changes most significantly in the scribe region 20, is provided at a boundary between the first region 21 and the second region 22.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, due to the spread of portable devices and the demand for energy saving and waste reduction, there is an increasing demand for semiconductor devices incorporating a nonvolatile memory that can rewrite data and retain data even when the power is turned off. .

  Nonvolatile memory includes EEPROM (Electric Erasable Programmable Read Only Memory), flash memory, FeRAM (Ferroelectric Random Access Memory), and the like. A test performed after the nonvolatile memory is completed includes an electrical test (retention test) for checking the presence or absence of data loss after heating to a predetermined temperature. This electrical test is usually performed on a chip-by-chip basis at the wafer level. Then, the test result is visualized in the form of a wafer map, and in the subsequent process, only good chips are selected using the wafer map, and defective chips are discarded.

  In the electrical test at the wafer level, the semiconductor wafer and the test apparatus are aligned using a reference mark previously formed at a specific position of the semiconductor wafer as a mark.

  However, as the semiconductor device becomes finer, the reference mark becomes finer, making it difficult to recognize the reference mark. Various methods have been proposed so far, but it is difficult to perform alignment with sufficient accuracy in any case.

JP 2003-7640 A JP2003-304098A JP 2002-83784 A Japanese Patent Laid-Open No. 2003-100903 JP 11-330247 A

  An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can be easily and reliably aligned during an electrical test.

  One aspect of the semiconductor device includes a plurality of chip regions and a scribe region including a reference mark between the plurality of chip regions. The reference mark has a first region and a second region that are in direct contact with each other, and a portion in which the reflectance with respect to visible light changes most greatly in the scribe region is the first region and the second region. At the boundary.

  In one aspect of the method for manufacturing a semiconductor device, a plurality of chip regions and a scribe region including a reference mark between the plurality of chip regions are formed. The reference mark has a first region and a second region that are in direct contact with each other, and a portion where the reflectance with respect to visible light changes most in the scribe region is defined as the first region and the second region. Set at the boundary.

  According to the above semiconductor device or the like, since an appropriate reference mark is included in the scribe region, alignment can be performed easily and reliably during an electrical test.

1 is a layout diagram illustrating a semiconductor device according to a first embodiment. It is sectional drawing which shows the structure of the chip area | region in 1st Embodiment. It is sectional drawing which shows the structure of the scribe area | region in 1st Embodiment. It is a flowchart which shows the alignment method at the time of performing the electrical test of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment (chip area | region). FIG. 5B is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment (chip region) following FIG. 5A. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment (scribe area | region). FIG. 6B is a cross-sectional view subsequent to FIG. 6A showing the method for manufacturing the semiconductor device according to the first embodiment (scribe region). It is sectional drawing which shows the structure of the chip area | region in 2nd Embodiment. It is sectional drawing which shows the structure of the scribe area | region in 2nd Embodiment. It is sectional drawing which shows the structure of a capacitive film. It is sectional drawing which shows the structure of the chip area | region in 3rd Embodiment. It is sectional drawing which shows the structure of the scribe area | region in 3rd Embodiment. FIG. 10 is a layout diagram illustrating a semiconductor device according to a fourth embodiment. It is a flowchart which shows the alignment method at the time of performing the electrical test of the semiconductor device which concerns on 4th Embodiment. It is a figure which shows the example of the layout of a reference mark. It is a figure which shows the other example of the layout of a reference mark. It is a figure which shows the influence of halation. It is a figure which shows the reference mark of the semiconductor device which concerns on 5th Embodiment. It is sectional drawing along the II line | wire in Fig.17 (a). It is sectional drawing which followed the II-II line | wire in Fig.17 (a). It is sectional drawing which shows the structure of the scribe area | region 20 in 6th Embodiment.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. FIG. 1 is a layout diagram illustrating the semiconductor device according to the first embodiment.

  As shown in FIG. 1, the semiconductor device 100 according to the first embodiment includes a plurality of chip regions 10 arranged vertically and horizontally, and a scribe region 20 is provided between adjacent chip regions 10. A reference mark 25 is included in the scribe area 20. The reference mark 25 includes a high reflection region 21 and a low reflection region 22 that are in direct contact with each other. The portion where the reflectance with respect to visible light changes most greatly in the scribe region 20 is at the boundary between the high reflection region 21 and the low reflection region 22. For example, within a specific range 30 including the reference mark 25, the first reflectance with respect to visible light on the upper surface side of the high reflection region 21 is the maximum, and the second reflection with respect to visible light on the upper surface side of the low reflection region 22. The rate is minimal. The high reflection region 21 is an example of a first region, and the low reflection region 22 is an example of a second region.

  FIG. 2 is a cross-sectional view showing the configuration of the chip region 10 in the first embodiment, and FIG. 3 is a cross-sectional view showing the configuration of the scribe region 20 in the first embodiment. FIG. 3 shows a cross section taken along line II in FIG.

  As shown in FIGS. 2 and 3, the chip region 10 and the scribe region 20 include a substrate 101 and a transistor layer 102. The substrate 101 is, for example, a silicon substrate, and the transistor layer 102 includes, for example, a transistor of a drive circuit that drives a memory cell array. An insulating film 103 such as a silicon oxide film is formed on the transistor layer 102, and a multilayer wiring is formed above the insulating film 103. The multilayer wiring includes, for example, five wiring layers 104, 106, 108, 110, and 112. The wiring layers 104, 106, 108, 110, and 112 include, for example, a low resistance film such as a Cu film or an AlCu alloy film, and include barrier metal films on the front and back surfaces of the low resistance film. For example, a titanium nitride film 121 is formed on the surface of the wiring layer 112 as a barrier metal film. The thickness of the titanium nitride film 121 is, for example, 50 nm to 100 nm. An insulating film 105 is formed on the wiring layer 104, an insulating film 107 is formed on the wiring layer 106, an insulating film 109 is formed on the wiring layer 108, an insulating film 111 is formed on the wiring layer 110, and the wiring layer An insulating film 113 is formed on 112. The wiring layer 106 is connected to the wiring layer 104 through a conductive plug in a via hole formed in the insulating film 105. The wiring layer 108 is connected to the wiring layer 106 through a conductive plug in a via hole formed in the insulating film 107. The wiring layer 110 is connected to the wiring layer 108 via a conductive plug in a via hole formed in the insulating film 109. The wiring layer 112 is connected to the wiring layer 110 via a conductive plug in a via hole formed in the insulating film 111. A silicon nitride film 122 is formed on the insulating film 113, and a polyimide film 123 is formed on the silicon nitride film 122.

  In the chip region 10, as shown in FIG. 2, an opening for exposing the wiring layer 112 is formed in the polyimide film 123, the silicon nitride film 122, the insulating film 113, and the titanium nitride film 121. In the low reflection region 22, the wiring layer 112 is covered with a titanium nitride film 121 as shown in FIG. 3. In the highly reflective region 21, as shown in FIG. 3, the polyimide film 123, the silicon nitride film 122, the insulating film 113, and the titanium nitride film 121 are not present, and the wiring layer 112 is exposed. In the region (third region) 23 outside the reference mark 25 in the scribe region 20, there is no polyimide film 123, silicon nitride film 122, insulating film 113, titanium nitride film 121, and wiring layer 112 as shown in FIG. 3. A part of the insulating film 111 is etched. The third region 23 includes alignment marks 131 and 132. For example, the alignment mark 131 is formed on the insulating film 103, and the alignment mark 132 is formed on the insulating film 107. As described above, the materials of the layers formed on the substrate 101 are different between the first region (high reflection region) 21, the second region (low reflection region) 22, and the third region 23. .

  In the semiconductor device 100 according to the first embodiment, the reflectance of the wiring layer 112 with respect to visible light is extremely high, and the visible light absorption rate of the titanium nitride film 121 is extremely high. For example, the wiring layer 112 in the high reflection region 21 reflects 50% or more of the visible light incident from the surface, and the titanium nitride film 121 in the low reflection region 22 reflects 50% or more of the visible light incident from the surface. Absorb. Further, the polyimide film 123, the silicon nitride film 122, and the insulating film 113 hardly reflect visible light. Therefore, the portion where the reflectance with respect to visible light changes most greatly in the scribe region 20 is at the boundary between the high reflection region 21 and the low reflection region 22. For this reason, in the electrical test, the reference mark 25 can be detected easily and reliably and the semiconductor wafer and the test apparatus can be aligned.

  Next, an alignment method when performing an electrical test of the semiconductor device 100 according to the first embodiment will be described. FIG. 4 is a flowchart showing an alignment method when an electrical test of the semiconductor device according to the first embodiment is performed.

  First, the semiconductor device 100 is mounted on the stage of the test apparatus, and the stage is moved to a position where image recognition by the image recognition apparatus of the test apparatus is possible (step S11). Next, a part of the image in the semiconductor device 100 is acquired using visible light, and this is compared with the template of the reference mark 25 created in advance (step S12). Until the acquired image matches the template, the processes from the stage movement to the image comparison are repeated (steps S11 to S13). When the acquired image matches the template, the image recognition is completed (step S14), and the positioning ends. Thereafter, the probe of the test apparatus is brought into contact with the exposed portion of the wiring layer 112 in the chip region 10, that is, the pad portion, and an electrical test is performed.

  According to this method, it is possible to detect the reference mark 25 easily and reliably and to align the semiconductor wafer and the test apparatus.

  Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. 5A to 5B and FIGS. 6A to 6B are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. 5A and 5B show the chip region 10 and FIGS. 6A and 6B show the scribe region 20.

  First, as illustrated in FIGS. 5A and 6A, the transistor layer 102 is formed over the substrate 101, and the insulating film 103 is formed over the transistor layer 102. Next, a multilayer wiring including wiring layers 104, 106, 108, 110 and 112 and insulating films 105, 107, 109, 111 and 113 is formed in the chip region 10 above the insulating film 103. A titanium nitride film 121 is formed on the surface of the wiring layer 112 as a barrier metal film. On the other hand, in the scribe region 20, alignment marks 131 and 132 are appropriately formed in the third region 23. The alignment marks 131 and 132 are used for alignment when forming the wiring layers 106, 108, 110 and 112. The wiring layer 112 and the titanium nitride film 121 are formed in the high reflection region 21 and the low reflection region 22 and are not formed in the third region 23.

  After the formation of the insulating film 113, a silicon nitride film 122 is formed on the insulating film 113, and a polyimide film 123 is formed on the silicon nitride film 122. Subsequently, as shown in FIG. 5B, in the chip region 10, an opening is formed in the polyimide film 123, and an opening is formed in the silicon nitride film 122, the insulating film 113, and the titanium nitride film 121 through this opening. . As a result, a part of the low resistance film of the wiring layer 112 is exposed. In the scribe region 20, as shown in FIG. 6B, an opening is formed in the polyimide film 123 in the high reflection region 21 and the third region 23, and the inside of the high reflection region 21 and the third region 23 is formed through this opening. Openings are formed in the silicon nitride film 122, the insulating film 113, and the titanium nitride film 121. Since the titanium nitride film 121 is not formed in the third region 23, a part of the insulating film 111 is also removed.

  In this way, the semiconductor device 100 according to the first embodiment can be manufactured.

(Second Embodiment)
Next, a second embodiment will be described. The second embodiment is different from the first embodiment in terms of the configuration of the layers of the chip region 10 and the scribe region 20. FIG. 7 is a cross-sectional view showing the configuration of the chip region 10 in the second embodiment, and FIG. 8 is a cross-sectional view showing the configuration of the scribe region 20 in the second embodiment.

  In the semiconductor device according to the second embodiment, as shown in FIG. 7, the capacitor region 210 on the wiring layer 110 is included in the chip region 10. FIG. 9 is a cross-sectional view showing the configuration of the capacitive film 210. As shown in FIG. 9, the capacitor film 210 includes a titanium nitride film 211 that also serves as a barrier metal film on the surface of the wiring layer 110, a dielectric film 212 on the titanium nitride film 211, and a titanium nitride film on the dielectric film 212. 213 is included. The titanium nitride film 213 is thicker than the titanium nitride film 121, and the thickness of the titanium nitride film 213 is, for example, 100 nm to 200 nm. Other configurations of the chip region 10 are the same as those in the first embodiment.

  As shown in FIG. 8, the configuration of the first region (high reflection region) 21 and the third region 23 is the same as that of the first embodiment. Unlike the first embodiment, the second region (low reflection region) 22 includes a wiring layer 110 on the insulating film 109 and a capacitor film 210 on the wiring layer 110, and includes the wiring layer 112 and titanium. The nitride film 121 is not formed. Other configurations of the scribe region 20 are the same as those in the first embodiment.

  In the second embodiment, the titanium nitride film 213 of the capacitor film 210 is thicker than the titanium nitride film 121 on the surface of the wiring layer 112. Therefore, the low reflection region 22 in the second embodiment is easier to absorb visible light than the low reflection region 22 in the first embodiment. For this reason, the contrast between the high reflection region 21 and the low reflection region 22 becomes stronger, and the reference mark 25 can be detected more reliably.

  When manufacturing the semiconductor device according to the second embodiment, for example, the capacitance film 210 is formed on the wiring layer 110 before the wiring layer 110 is patterned, and the capacitance film 210 is formed when the wiring layer 110 is patterned. Also pattern.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment is different from the first embodiment in the configuration of the layers of the chip region 10 and the scribe region 20. FIG. 10 is a cross-sectional view showing the configuration of the chip region 10 in the third embodiment, and FIG. 11 is a cross-sectional view showing the configuration of the scribe region 20 in the third embodiment.

  In the semiconductor device according to the third embodiment, as shown in FIG. 10, a ferroelectric capacitor 310 on the transistor layer 102 is included in the chip region 10. The ferroelectric capacitor 310 includes a lower electrode 311, a ferroelectric film 312 on the lower electrode 311, and an upper electrode 313 on the ferroelectric film 312. For example, the lower electrode 311 is a platinum (Pt) film, the ferroelectric film 312 is a lead zirconate titanate (PZT) film, and the upper electrode 313 is an iridium oxide film. Other configurations of the chip region 10 are the same as those in the first embodiment.

  As shown in FIG. 11, the configuration of the second region (low reflection region) 22 and the third region 23 is the same as that of the first embodiment. Unlike the first embodiment, the first region (high reflection region) 21 includes a Pt film as the lower electrode 311 on the transistor layer 102, and the wiring layer 112 is formed above the lower electrode 311. Absent. Other configurations of the scribe region 20 are the same as those in the first embodiment.

  In the third embodiment, the reflectance of the Pt film used for the lower electrode 311 with respect to visible light is higher than the reflectance of the Cu film or AlCu alloy film used for the wiring layer 112 with respect to visible light. Visible light that has entered the highly reflective region 21 reaches the lower electrode 311 without being blocked by the titanium nitride film 121 or the wiring layer 112, and is reflected by the lower electrode 311. Therefore, the highly reflective region 21 in the third embodiment reflects visible light more easily than the highly reflective region 21 in the first embodiment. For this reason, the contrast between the high reflection region 21 and the low reflection region 22 becomes stronger, and the reference mark 25 can be detected more reliably.

  When manufacturing the semiconductor device according to the third embodiment, for example, a film constituting the ferroelectric capacitor 310 is formed on the insulating film 103 before the insulating film 103 is formed, and this film is etched. Only the Pt film of the lower electrode 311 remains in the highly reflective region 21.

(Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment is different from the first embodiment in the layout of the reference mark 25. FIG. 12 is a layout diagram illustrating the semiconductor device according to the fourth embodiment.

  In the semiconductor device 400 according to the fourth embodiment, three reference marks 25 are included in the scribe region 20 as shown in FIG. The dimension in the longitudinal direction of the reference mark 25 is approximately the same as the sum of the dimensions of the two chip regions 10 in the same direction and the width of the scribe region 20 between them. The three reference marks 25 are arranged so as to be shifted by one column on the grid of the scribe region 20 in the horizontal direction, and are shifted by two columns on the grid of the scribe region 20 in the vertical direction. That is, in the vertical direction, the reference marks 25 are arranged at a pitch that is an integral multiple (1 times, 2) of the number (2) of the chip regions 10 corresponding to the longitudinal dimension of the reference mark 25. Other configurations are the same as those of the first embodiment.

  Next, an alignment method when performing an electrical test of the semiconductor device 400 according to the fourth embodiment will be described. FIG. 13 is a flowchart showing an alignment method when performing an electrical test of the semiconductor device according to the fourth embodiment.

  First, the semiconductor device 400 is mounted on the stage of the test apparatus, and the stage is moved to a position where image recognition by the image recognition apparatus of the test apparatus is possible (step S21). Next, a part of the image in the semiconductor device 400 is obtained using visible light, and this is compared with the first template of the reference mark 25 created in advance (step S22). Until the acquired image matches the first template, the processes from the stage movement to the image comparison are repeated (steps S21 to S23). When the acquired image matches the first template, the second template of the three reference marks 25 is called (step S24), and the current visual field is divided (step S25). Thereafter, the second template is compared with the divided matrix image (step S26), and when the comparison of all the matrices is completed (step S27), the positional relationship of the same matrix as the second template is calculated (step S28). ). Then, the position information is compared with the position information of the second template (step S29), and the processes from the stage movement to the position information comparison are repeated until they match (steps S21 to S30). When the matrix image matches the second template, the image recognition is completed (step S31), and the positioning is finished. Thereafter, the probe of the test apparatus is brought into contact with the exposed portion of the wiring layer 112 in the chip region 10, that is, the pad portion, and an electrical test is performed.

  According to this method, it is possible to easily and more reliably detect the reference mark 25 and align the semiconductor wafer and the test apparatus.

  The cross-sectional configurations of the chip region 10 and the scribe region 20 may be the same as those in the second or third embodiment.

  As shown in FIG. 14, in the longitudinal direction of the reference mark 25, two or more reference marks 25 are formed at a pitch that is an integral multiple of the number of chip regions 10 (two in this case) corresponding to the longitudinal dimension of the reference mark 25. It is preferable that two or more reference marks 25 are disposed at positions shifted from each other in the short direction of the reference marks 25. As shown in FIG. 15, in the longitudinal direction, the number of chip regions 10 corresponding to the longitudinal dimension of the reference mark 25 (two) is 0.5 times (1) or 1.5 times (3). When two or more reference marks 25 are arranged at a pitch or the reference marks 25 are arranged at the same position in the short direction, the processing in the flowchart shown in FIG. 13 can be complicated.

  The greater the difference in reflectance between the high reflection region 21 and the low reflection region 22, the easier the detection of the reference mark 25 based on contrast. However, when the reflectance of the high reflection region 21 is too high, halation May occur and the low reflection region 22 may be blurred. FIG. 16 is a diagram illustrating the influence of halation. As shown in FIG. 16A, even if the boundary between the high reflection region 21 and the low reflection region 22 is linear, if halation occurs, as shown in FIG. It can be determined that the boundary between the bright area and the dark area is curved. In this case, assuming that the curved boundary does not match the template, it may not be detected that there is a boundary between the high reflection region 21 and the low reflection region 22 here. In the following fifth and sixth embodiments, a configuration that reduces the influence of halation is employed.

(Fifth embodiment)
A fifth embodiment will be described. FIG. 17 is a diagram illustrating the reference marks of the semiconductor device according to the fifth embodiment. 18A is a cross-sectional view taken along a line II in FIG. 17A, and FIG. 18B is a cross-sectional view taken along a line II-II in FIG.

  In the fifth embodiment, as shown in FIG. 17A, the light absorbing portions 24 are formed near the boundary between the high reflection region 21 and the low reflection region 22 at a pitch shorter than the wavelength of visible light to be irradiated. Yes. As shown in FIGS. 18A and 18B, the light absorbing portion 24 includes a titanium nitride film 121. As described above, the visible light absorption rate of the titanium nitride film 121 is extremely high.

  In the fifth embodiment, halation is alleviated by the light absorber 24, and it is determined that the boundary between the bright area and the dark area is linear as shown in FIG. It is reliably detected that there is a boundary between the region 21 and the low reflection region 22.

(Sixth embodiment)
Next, a sixth embodiment will be described. The sixth embodiment is different from the first embodiment in the configuration of the layer of the scribe region 20. FIG. 19 is a cross-sectional view showing the configuration of the scribe region 20 in the sixth embodiment.

  In the semiconductor device according to the sixth embodiment, as shown in FIG. 19, the configurations of the second region (low reflection region) 22 and the third region 23 are the same as those of the first embodiment. Unlike the first embodiment, the first region (high reflection region) 21 includes the wiring layer 104 on the insulating film 103, and the wiring layer 112 is not formed above the wiring layer 104. Other configurations are the same as those of the first embodiment.

  In the sixth embodiment, since the wiring layer 104 in the high reflection region 21 is positioned closer to the substrate 101 than the wiring layer 110 in the low reflection region 22, visible light reflected by the wiring layer 104 toward the low reflection region 22 side. Is difficult to be released to the outside. Therefore, halation is also alleviated by the sixth embodiment.

  The layer structure of the high reflection region 21, the low reflection region 22, and the third region 23 is not particularly limited, but the high reflection region 21 has a reflection film that reflects 50% or more of the visible light incident from the surface. The low reflection region 22 preferably has an absorption film that absorbs 50% or more of the visible light incident from the surface. The third region 23 preferably has a film having a reflection characteristic between the reflective film in the high reflection region 21 and the absorption film in the low reflection region 22 with respect to visible light incident from the surface.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
Multiple chip areas;
A scribe region including a reference mark between the plurality of chip regions;
Have
The reference mark has a first region and a second region that are in direct contact with each other;
The semiconductor device according to claim 1, wherein a portion where the reflectance with respect to visible light changes most in the scribe region is at a boundary between the first region and the second region.

(Appendix 2)
A substrate,
A plurality of layers formed on the substrate;
Have
2. The semiconductor device according to appendix 1, wherein the material of the layer is different between the first region and the second region.

(Appendix 3)
Within a specific range of the scribe region including the first region and the second region,
The first reflectance of visible light in the first region is maximum;
The semiconductor device according to appendix 1 or 2, wherein the second reflectance of visible light in the second region is minimum.

(Appendix 4)
The first region has a reflective film that reflects 50% or more of visible light incident from the surface;
4. The semiconductor device according to any one of appendices 1 to 3, wherein the second region has an absorption film that absorbs 50% or more of visible light incident from the surface.

(Appendix 5)
The semiconductor device according to appendix 4, wherein the scribe region has a film that exhibits a reflection characteristic between the reflection film and the absorption film with respect to visible light incident from the surface outside the reference mark. .

(Appendix 6)
The scribe region includes two or more reference marks,
Appendices 1 to 5, wherein in the longitudinal direction of the reference mark, the two or more reference marks are arranged at a pitch that is an integral multiple of the number of the chip regions corresponding to the longitudinal dimension of the reference mark. The semiconductor device according to any one of the above.

(Appendix 7)
The scribe region includes two or more reference marks,
The semiconductor device according to any one of appendices 1 to 6, wherein the two or more reference marks are arranged at positions shifted from each other in a short direction of the reference mark.

(Appendix 8)
Forming a plurality of chip regions, and a scribe region including a reference mark between the plurality of chip regions,
The reference mark has a first region and a second region that are in direct contact with each other;
A method of manufacturing a semiconductor device, wherein a portion where the reflectance with respect to visible light changes most in the scribe region is provided at a boundary between the first region and the second region.

(Appendix 9)
Forming a plurality of layers on the substrate;
9. The method of manufacturing a semiconductor device according to appendix 8, wherein the material of the layer is made different between the first region and the second region.

10: Chip area 20: Scribe area 21: High reflection area (first area)
22: Low reflection region (second region)
23: Third region 24: Light absorption unit 100, 400: Semiconductor device 101: Substrate 102: Transistor layer 112: Wiring layer 121: Titanium nitride film 210: Capacitance film 310: Ferroelectric capacitor 311: Lower electrode (Pt film) )

Claims (7)

Multiple chip areas;
A scribe region including a reference mark between the plurality of chip regions;
Have
The reference mark has a first region and a second region that are in direct contact with each other;
The semiconductor device according to claim 1, wherein a portion where the reflectance with respect to visible light changes most in the scribe region is at a boundary between the first region and the second region. A substrate,
A plurality of layers formed on the substrate;
Have
The semiconductor device according to claim 1, wherein a material of the layer is different between the first region and the second region. Within a specific range of the scribe region including the first region and the second region,
The first reflectance of visible light in the first region is maximum;
3. The semiconductor device according to claim 1, wherein the second reflectance of visible light in the second region is minimum. The scribe region includes two or more reference marks,
2. The two or more reference marks are arranged in the longitudinal direction of the reference mark at a pitch that is an integral multiple of the number of the chip regions corresponding to the longitudinal dimension of the reference mark. 4. The semiconductor device according to any one of items 3. The scribe region includes two or more reference marks,
5. The semiconductor device according to claim 1, wherein the two or more reference marks are arranged at positions shifted from each other in a short direction of the reference mark. 6. Forming a plurality of chip regions, and a scribe region including a reference mark between the plurality of chip regions,
The reference mark has a first region and a second region that are in direct contact with each other;
A method of manufacturing a semiconductor device, wherein a portion where the reflectance with respect to visible light changes most in the scribe region is provided at a boundary between the first region and the second region. Forming a plurality of layers on the substrate;
7. The method of manufacturing a semiconductor device according to claim 6, wherein a material of the layer is made different between the first region and the second region.

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