JP2018186112A - DML driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of a circuit area. SOLUTION: A driver circuit 12 is turned on and off according to a modulation signal D0, a transistor Q0, a resistance element R0 connected between an emitter terminal of Q0 and a ground potential GND, a collector terminal of Q0 and a connection node N. The power supply circuit 11 is composed of a resistance element R2 having one end connected to the power supply potential VCS and the other end connected to the connection node N. [Selection diagram] Fig. 1

Description

  The present invention relates to a shunt-type LD driving technique used when driving a DML (Directly Modulated Laser) that directly modulates the light intensity of an LD (Laser Diode).

  In recent years, with an increase in communication traffic, an increase in capacity of an optical communication network using optical fibers has been demanded. In particular, the capacity of Ethernet (registered trademark), which is a main standard element of communication networks, is increasing. With this increase in capacity, standardization of Ethernet has been completed for 10 GbE and 40 GbE, and standardization of 100 GbE aimed at further increase in capacity is being completed.

  FIG. 11 is a configuration example of a 100 GBase-LR4 / ER4 optical transmission system. An LD driver using a shunt type circuit configuration has been reported as an LD driver capable of high-speed operation with low power consumption in the transmission front end.

  FIG. 12 is a configuration example of a transmission front end using a shunt type LD driver. FIG. 13 shows an operation example of the transmission front end of FIG. A portion surrounded by a broken line in FIG. 12 is a shunt type LD driver portion. By adding a shunt type LD driver part in parallel to the LD, it is possible to turn on / off the switch of the LD driver part and put information as shown in FIG. Further, since the shunt type LD driver has a high output resistance, it is integrated monolithically with the LD or mounted in the same package as the LD. Therefore, it is not necessary to match impedance, and high speed operation is possible with low power consumption.

T. Kishi, M. Nagatani, S. Kanazawa, W. Kobayashi, T. Shindo, H. Yamazaki, M. Ida, K. Kurishima, and H. Nosaka, "A 45-mW 50-Gb / s Linear Shunt LD Driver in 0.5-μm InP HBT Technology ", Compound Semiconductor Integrated Circuit Symposium, 2016

FIG. 14 is a circuit configuration example showing a conventional transmission front end. This transmission front end is provided with a DML driver (LD driver) and an LD.
The DML driver 50 is connected in parallel to the power supply circuit 51 that supplies current from the power supply potential V _CC to the LD, and bypasses part of the current in accordance with the input modulation signal D _0. And a driver circuit 52 to be operated.

The driver circuit 52 includes a transistor Q to which a modulation signal D ₀ is applied to the gate terminal, a resistance element R ₀ having one end connected to the emitter terminal of Q, and the other end connected to the ground potential GND, and one end having Q. The resistor element R ₁ is connected to the collector terminal and the other end is connected to the connection node N.
The power supply circuit 51 includes a high frequency choke coil L having one end connected to V _CC and the other end connected to the connection node N.
The LD has an anode terminal connected to the connection node N and a cathode terminal connected to GND.

As described above, in the conventional transmission front end, the connection node is set as the power supply circuit 51 so that the sum of the drive current I _LD flowing through the _LD and the bypass current I ₀ flowing through the driver circuit 52, that is, the supply current I _CC becomes a constant value. A high frequency choke coil L is mounted between N and the power supply potential V _CC .
For this reason, a certain amount of circuit area is required for mounting the high-frequency choke coil L, and as a result, there is a problem in that the circuit area of the entire transmission front end cannot be reduced.

  The present invention has been made to solve such a problem, and an object thereof is to provide a transmission front end capable of reducing the circuit area.

  In order to achieve such an object, a DML driver according to the present invention includes a power supply circuit that supplies current to an LD having an anode terminal and a cathode terminal connected to a connection node and a ground potential, respectively, A DML driver that is connected in parallel and bypasses a part of the current according to the input first modulation signal, wherein the driver circuit corresponds to the first modulation signal. A first transistor that is turned on and off, a first resistance element connected between the first output terminal of the first transistor and the ground potential, and a second output terminal of the first transistor And a second resistance element connected between the connection node, and the power supply circuit includes a third resistance element having one end connected to a power supply potential and the other end connected to the connection node. It is made of.

Also, in one configuration example of the DML driver according to the present invention, when the first modulation signal is a voltage V _inhigh indicating a high level, the anode-cathode voltage of the LD and the drive current flowing through the LD are _expressed as V _LDmin and _ILDmin , and when the first modulation signal is a voltage V _inlow indicating a low level, the anode-cathode voltage of the LD and the drive current flowing through the LD are _VLDmax and _ILDmax , and the driver circuit When the bypass current flowing through the driver circuit is I _{0max_min} when the power consumption of the power supply is minimum, the power supply potential of the power supply and the third resistance element are expressed by equations (6) and (7) described later. and it has a potential V _CCmin and resistance R _2min.

In one configuration example of the DML driver according to the present invention, the power supply circuit further includes a first capacitor element connected in parallel with the third resistor element.
Also, in one configuration example of the DML driver according to the present invention, the driver circuit further includes a second capacitor element connected in parallel with the second resistor element.

  Also, in one configuration example of the DML driver according to the present invention, the driver circuit includes a first basic driver circuit including the first transistor, the first resistance element, and the second resistance element. A first transistor group (n is an integer of 2 or more) connected in parallel, and a second transistor that is turned on / off in response to a second modulation signal independent of the first modulation signal; , A first resistance element connected between the first output terminal of the second transistor and the ground potential, and a second resistor connected to the second output terminal of the second transistor and the connection node. The second basic driver circuit composed of the resistive elements is provided with a second circuit group in which n × 2 second basic driver circuits are connected in parallel.

  According to the present invention, since the mounting area of the resistance element is extremely smaller than the mounting area of the high-frequency choke coil, the circuit area required for the DML driver can be greatly reduced. Therefore, the circuit area of the entire transmission front end 1 can be greatly reduced.

1 is a circuit diagram showing a configuration of a DML driver according to a first embodiment. FIG. It is a graph which shows the IV characteristic of LD. It is explanatory drawing which shows operation | movement of the transmission front end concerning 1st Embodiment. It is a graph which shows the relationship between the power consumption of a DML driver, and a bypass current. 2 is a configuration example of a derivative circuit of the DML driver of FIG. 3 is another example of a derived circuit configuration of the DML driver of FIG. 1. It is a circuit diagram which shows the structure of the DML driver concerning 2nd Embodiment. It is explanatory drawing of a PAM4 modulation system. 8 is a configuration example of a derivative circuit of the DML driver of FIG. 8 is another example of a derived circuit configuration of the DML driver of FIG. It is a structural example of a 100 GBase-LR4 / ER4 optical transmission system. It is a structural example of the transmission front end using a shunt type LD driver. 13 is an operation example of the transmission front end of FIG. 12. It is an example of a circuit structure which shows the conventional transmission front end.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a DML driver 10 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram showing the configuration of the DML driver according to the first embodiment.

  The DML driver 10 according to the present invention is a shunt type used when driving a DML (Directly Modulated Laser) that directly modulates the light intensity of an LD (Laser Diode) in the transmission front end 1 of the optical transmission system. This is an LD drive circuit. In this embodiment, a configuration example of a current source load type will be described.

As shown in FIG. 1, the DML driver 10 according to the present embodiment includes a power supply circuit 11 that supplies a supply current I _CC (drive current I _LD + bypass current I ₀ ) from the power supply potential V _CC to the LD, The driver circuit 12 is connected in parallel to the LD and bypasses a part of the supply current I _CC (bypass current I ₀ ) according to the input modulation signal D ₀ . The present invention is characterized in that a resistance element R ₂ is used as the power supply circuit 11 in place of the high-frequency choke coil.

The driver circuit 12 has a gate terminal to which a modulation signal D ₀ is applied (first transistor) Q ₀ , one end connected to the emitter terminal (first output terminal) of Q ₀ , and the other end to the ground potential. A resistor element (first resistor element) R ₀ connected to GND, a resistor element (first resistor element) having one end connected to the collector terminal (second output terminal) of Q ₀ and the other end connected to the connection node N 2 resistive elements) R ₁ .

A modulation signal (first modulation signal) D ₀ having a value of “1” (high level) or “0” (low level) is applied to the gate terminal of Q ₀ from the outside. The resistance element R _m connected between the gate terminal of Q ₀ and GND is a resistance for input matching, and when it is a 50Ω-type input transmission line, R _m is 50Ω.

The power supply circuit 11 includes a resistance element (third resistance element) R _{2 having} one end connected to the power supply potential V _CC and the other end connected to the connection node N.
The LD has an anode terminal connected to the connection node N and a cathode terminal connected to GND.

[Operation of First Embodiment]
Next, the operation of the DML driver 10 according to the present embodiment will be described.
When the supply current supplied from the power supply potential V _CC via the power supply circuit 11 is I _CC , the bypass (drawing) current flowing to the driver circuit 12 is I _0, and the drive current flowing to the LD is I _LD , I _CC = I ₀ + I _LD

At this time, the transistor Q ₀ and the resistance element R of the driver circuit 12 under the condition that I _CC is a constant value so that I _LD is controlled to a current value corresponding to a desired light intensity according to the modulation signal D _0. Circuit constants related to ₀ and R ₁ are designed.
For example, when the LD anode-cathode voltage V _LD and the drive current I _LD required for the light intensity corresponding to “1” of the modulation signal D ₀ are V _LDmin and I _LDmin , the bypass current I _0max is I _0max. = I _CC -I _LDmin . As a result, the resistance value R ₀ + R ₁ = V _LDmin / I _0max , and the resistance value R ₀ is determined from the base current of Q ₀ .

FIG. 2 is a graph showing the IV characteristics of the LD. FIG. 3 is an explanatory diagram illustrating an operation of the transmission front end according to the first embodiment.
As shown in FIG. 2, as the input voltage V _in indicating a modulation signal D _0, when the modulation signal D ₀ is "1", that is the input voltage V _Inhigh showing a high level is input, the anode of the LD - cathode voltage V _The drive current I _LD flowing through _LD and LD is _defined as V _LDmin (minimum value) and I _LDmin (minimum value).

On the other hand, when the modulation signal D ₀ is “0”, that is, when the input voltage V _inlow indicating the low level is input, the anode-cathode voltage V _LD and the drive current I _LD are set to V _LDmax (maximum value) and I _LDmax (maximum value). ).
In the region between these minimum and maximum values, V _LD and I _LD are linearly proportional.

Accordingly, as shown in FIG. 3, when the modulation signal D ₀ indicates the value “1” and V _in , V _LD , and I _LD are V _inhigh , V _LDmin , and I _LDmin , the supply current I _CC The bypass current I ₀ is I _0max + I _LDmin and I _0max (maximum value).
When the modulation signal D ₀ indicates the value “0” and V _in , V _LD , and I _LD are V _inlow , V _LDmax , and I _LDmax , the supply current I _CC and the bypass current I ₀ are I become _0min + I _LDmax and I _0min (minimum value).

Therefore, when the I _0min = 0, V _LDmax, the V _LDmin, the following equation (1) and (2) is satisfied.

The power consumption P [W] in the DML driver 10 can be expressed by the following formula (3), and V _CC can be expressed by the following formula (4).

Therefore, the following equation (5) can be obtained for P by substituting equation (4) into equation (3).

In this formula (5), since I _LDmax , I _LDmin , V _LDmax , and V _LDmin are desired circuit constants at the time of circuit design, P can be regarded as a function of I _0max .
FIG. 4 is a graph showing the relationship between the power consumption of the DML driver and the bypass current, which is plotted by substituting an example of circuit constants related to I _LDmax , I _LDmin , V _LDmax , and V _LDmin into equation (5). is there.

In FIG. 4, the power consumption P once decreases with the increase of I _{0max and reaches} a minimum value P _min . Then the value of I _0max and _I 0max_min. Thereafter, the power consumption P gradually increases as I _0max increases.
Therefore, the value of V _CC in P _min and V _CCmin, the value of R ₂ When R _2min, V _CCmin and R _2min can be expressed by the following equation (6) and (7).

Thus, as V _CC and R _2, by setting the value of V _CCmin and R _2min determined by equation (6) and (7), it is possible to minimize the power consumption P of a DML driver 10 .

FIG. 5 is an example of a derived circuit configuration of the DML driver of FIG. Here, an example is shown in which a capacitive element (first capacitive element) C ₂ is connected in parallel to the resistive element R ₂ of the power supply circuit 11. Thereby, the overshoot of the optical waveform due to the relaxation oscillation frequency of the LD can be suppressed.
FIG. 6 shows another example of the derived circuit configuration of the DML driver of FIG. Here, an example is shown in which a capacitive element (second capacitive element) C ₁ is connected in parallel to the resistive element R ₁ of the driver circuit 12. Thereby, the frequency characteristic of the driver circuit 12 can be improved. At this time, the capacitive element C ₂ of FIG. 5 may be provided in addition to the capacitive element C ₁ .

[Effect of the first embodiment]
As described above, in this embodiment, the driver circuit 12 includes the transistor Q _{0 that is} turned on / off according to the modulation signal D ₀ and the resistance element R ₀ connected between the emitter terminal of Q ₀ and the ground potential GND. And a resistance element R ₁ connected between the collector terminal of Q ₀ and the connection node N, the power supply circuit 11 has one end connected to the power supply potential V _CC and the other end connected to the connection node N. The resistor element R ₂ is used.

Thereby, since the mounting area of the resistance element R ₂ is extremely smaller than the mounting area of the high-frequency choke coil, the circuit area required for the DML driver 10 can be greatly reduced. Therefore, the circuit area of the entire transmission front end 1 can be greatly reduced.

In the present embodiment, when the modulation signal D ₀ is a voltage V _inhigh indicating a high level, the anode-cathode voltage of the LD and the drive current flowing through the LD are V _LDmin and I _LDmin , and the modulation signal D ₀ is When the voltage V _inlow indicating the Low level is set, the voltage between the anode and the cathode of the LD and the drive current flowing through the LD are V _LDmax and I _LDmax , and the driver circuit 12 has a power consumption P that is the minimum value P _min. If a bypass current flowing to 12 was _I 0max_min, the value of the power supply potential V _CC and a resistor R _2, be a V _CCmin and R _2min obtained in the above-mentioned formula (6) and (7) Good.
As a result, the power consumption P in the DML driver 10 can be minimized.

[Second Embodiment]
Next, a DML driver 10 according to a second exemplary embodiment of the present invention is described with reference to FIG. FIG. 7 is a circuit diagram illustrating a configuration of a DML driver according to the second embodiment.
In the long-distance optical communication, the transmission rate is evolving from 100 Gbps to 400 Gbps and further to 1 Mbps as the data transmission capacity increases. On the other hand, multi-level modulation schemes such as quaternary modulation scheme PAM4 (PAM: Pulse Amplitude Modulation) are being introduced from the conventional binary modulation schemes such as NRZ code modulation. In the present embodiment, an example in which the DML driver 10 of the present invention is adapted to PAM4 will be described.

8A and 8B are explanatory diagrams of the PAM4 modulation method. FIG. 8A shows an example of a time waveform of PAM4, and FIG. 8B shows an eye pattern of PAM4. PAM4 is a modulation scheme for transmitting two bits of digital information (modulation signal) D _1, D ₀ at the same time, four to light intensity 0-3, set the D _1, D _0, that is, "00" , “01”, “10”, and “11” are assigned.

As shown in FIG. 7, in the DML driver 10 according to the present embodiment, a circuit group (first circuit group) 12A and a circuit group (second circuit group) 12B are provided in the driver circuit 12. ing.
The circuit group 12A is a circuit in which n (n is an integer of 2 or more) basic driver circuits 13A that perform an on / off operation based on the modulation signal D ₀ are connected in parallel.
The circuit group 12B is a circuit in which n × 2 basic driver circuits 13B that perform an on / off operation based on a modulation signal (second modulation signal) D ₁ are connected in parallel.

A basic driver circuit (first basic driver circuit) 13A includes a transistor (first transistor) Q ₀ to which a modulation signal D ₀ is applied to a gate terminal, and an emitter terminal (first output terminal) having one end Q _0. It is connected to the other end and ground potential GND connected to the resistance element (first resistor element) R _0, one end connected to the collector terminal (second output terminal) of Q _0, the other end connected to a node And a resistance element (second resistance element) R ₁ connected to N.

Basic driver circuit (second basic driver circuit) 13B are transistors modulated signal D ₁ is applied to the gate terminal (second transistor) Q _1, one end for Q ₁ emitter terminal (first output terminal) It is connected to the other end and ground potential GND connected to the resistance element (first resistor element) R _0, one end connected to the collector terminal (second output terminal) of Q _1, the other end connected to a node And a resistance element (second resistance element) R ₁ connected to N.

At this time, the transistors of the basic driver circuits 13A and 13B under the condition that I _CC is a constant value so that I _LD is controlled to a current value corresponding to a desired light intensity according to the modulation signals D ₁ and D _0. Circuit constants relating to Q ₀ , Q ₁ and resistance elements R ₀ , R ₁ are determined.

With this configuration, the value of the bypass current I ₀ that increases when the modulation signal D ₁ is “1” corresponds to twice the value of the bypass current I ₀ that increases when the modulation signal D ₀ is “1”. It will be. Therefore, by combining these D ₁ and D ₀ , four types of bypass currents I ₀ can be generated, and the four types of optical signals shown in FIG. 8 can be emitted from the LD.
Note that the power supply potential V _CC and the resistance element R ₂ can be applied to the present embodiment in the same manner as in the first embodiment.

FIG. 9 is a derivation circuit configuration example of the DML driver of FIG. Here, an example in which a capacitive element C ₂ is connected in parallel to the resistance element R ₂ of the power supply circuit 11 is shown. Thereby, the overshoot of the optical waveform due to the relaxation oscillation frequency of the LD can be suppressed.
FIG. 10 shows another derivative circuit configuration example of the DML driver of FIG. Here, an example is shown in which a capacitive element C ₁ is connected in parallel to the resistive element R ₁ of the basic driver circuits 13A and 13B. As a result, the frequency characteristics of the basic driver circuits 13A and 13B can be improved. At this time, the capacitive element C ₂ of FIG. 9 may be provided in addition to the capacitive element C ₁ .

[Effect of the second embodiment]
Thus, in the present embodiment, the driver circuit 12 is provided with a circuit group 12A in which n basic driver circuits 13A each including the transistor Q ₀ and the resistance elements R ₀ and R ₁ are connected in parallel, and the modulation signal D A transistor Q ₁ that operates on and off in response to a modulation signal D ₁ independent of ₀ , a resistance element R ₀ connected between the emitter terminal of Q ₁ and the ground potential GND, a collector terminal of Q ₁ and a connection node in which basic driver circuit 13B composed of the resistor connected R ₁ Metropolitan to n is provided n × 2 pieces connected in parallel comprising circuits 12B.
As a result, the same effect as that of the first embodiment can be obtained even with the PAM4 modulation type DML driver 10.

[Extended embodiment]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, each embodiment can be implemented in any combination within a consistent range.

1 ... From the front end, 10 ... DML driver, 11 ... power supply circuit, 12 ... driver circuit, 12A, 12B ... circuits, 13A, 13B ... basic driver circuit, Q _0, Q ₁ ... transistors, R _0, R _1, R ₂ , R _m ... resistance elements, C ₁ , C ₂ ... capacitive elements, LD ... laser diode, N ... connection node, D ₀ , D ₁ ... modulation signal, V _in , V _inhigh , V _inlow ... input voltage, V _CC ... power supply potential, GND ... ground potential, I _CC ... supply _{current, V LD, V LDmin, V} LDmax ... anode - cathode _{voltage, I LD, I LDmin, I} LDmax ... drive current, I _0, I _0min, I _0max , _{I0max_min} : Bypass current, P, _Pmin : Power consumption.

Claims (5)

A power supply circuit for supplying a current to an LD having an anode terminal and a cathode terminal connected to a connection node and a ground potential, respectively, and connected in parallel with the LD in accordance with an input first modulation signal A DML driver comprising a driver circuit for bypassing a part of the current,
The driver circuit includes a first transistor that is turned on / off in response to the first modulation signal, and a first resistance element connected between the first output terminal of the first transistor and the ground potential. And a second resistance element connected between the second output terminal of the first transistor and the connection node,
The power supply circuit includes a third resistance element having one end connected to a power supply potential and the other end connected to the connection node. The DML driver according to claim 1,
When the first modulation signal is a voltage V _inhigh indicating a high level, the anode-cathode voltage and drive current of the LD are set to V _LDmin and I _LDmin, and the first modulation signal is a voltage V indicating a low level. _{When inlow} , the anode-cathode voltage and drive current of the LD are V _LDmax and I _LDmax, and the bypass current flowing through the driver circuit when the power consumption of the driver circuit is minimum is I _{0max_min} , It said power supply potential and said third resistance element, DML driver, characterized in that each has a potential V _CCmin and resistance R _2min shown in the following equation.

The DML driver according to claim 1 or 2,
The DML driver, wherein the power supply circuit further includes a first capacitor element connected in parallel with the third resistor element. In the DML driver according to any one of claims 1 to 3,
The DML driver, wherein the driver circuit further includes a second capacitor element connected in parallel with the second resistor element. In the DML driver according to any one of claims 1 to 4,
The driver circuit is
A first circuit group in which n (n is an integer of 2 or more) first basic driver circuits including the first transistor, the first resistance element, and the second resistance element are connected in parallel. Prepared,
And a second transistor that is turned on and off in response to a second modulation signal independent of the first modulation signal, and connected between a first output terminal of the second transistor and a ground potential. N × 2 second basic driver circuits each including a first resistance element, a second output terminal of the second transistor, and a second resistance element connected to the connection node are connected in parallel. A DML driver comprising the second circuit group.

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