JP2018160882A - Power amplification and distribution circuit and multi-stage power amplification and distribution circuit - Google Patents

Abstract

A compact power amplification and distribution circuit capable of amplifying signal power with high efficiency and distributing the signal power to a plurality of systems is provided. A power amplifying and distributing circuit includes a single-turn annular first inductor and an N-turn annular second inductor having a shape along a part of the first inductor, and the input signal is a positive-phase signal. A conversion element for converting into a negative phase signal, a first transistor whose source is connected to the third power source and receiving the positive phase signal at the gate, and a second transistor whose source is connected to the fourth power source and receiving the negative phase signal at the gate. A transistor, a first impedance circuit connected between the gate of the first transistor and the drain of the second transistor, and a second impedance circuit connected between the gate of the second transistor and the drain of the first transistor; And an output matching circuit that is connected to the drain of the first transistor and the drain of the second transistor and outputs the first distribution signal and the second distribution signal. [Selection] Figure 4

Description

  The present disclosure relates to a power amplification distribution circuit and a multistage power amplification distribution circuit.

  In recent years, millimeter-wave bands have attracted attention because wireless technologies such as communication and radar can use wideband signals. For example, in the millimeter wave band, the 60 GHz band is used for high-speed communication, and the 76 GHz band is used for high-resolution radar. And the expansion to the frequency band exceeding 100 GHz is anticipated for the purpose of the further further performance improvement in the future.

  In order to realize millimeter-wave band high-speed communication and high-resolution radar, methods such as beam forming and MIMO (Multiple-Input Multiple-Output) are used as radio signal transmission / reception methods. In systems such as beam forming and MIMO, signal power is amplified, the amplified signal is distributed to a plurality of systems, and signal processing is performed on the distributed signals of each system. Therefore, in systems such as beam forming and MIMO, circuits that amplify signal power and distribute it to a plurality of systems are being studied.

  For example, Non-Patent Document 1 discloses a circuit that amplifies the power of a millimeter-wave band signal and distributes it to a plurality of systems.

“A 65nm CMOS 4-Element Sub-34mW / Element 60GHz Phased-Array Transceiver” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2011, pp. 20-24.

  However, since the circuit disclosed in Non-Patent Document 1 is based on the operating principle using the wavelength of a signal that passes therethrough, the gain is low due to the large power loss that accompanies the increase in circuit size.

  The non-limiting example of the present disclosure contributes to the provision of a small power amplification distribution circuit and a multistage power amplification distribution circuit that can amplify signal power with high efficiency and distribute the signal power to a plurality of systems.

  A power amplification distribution circuit according to an aspect of the present disclosure includes a first-turn annular first inductor provided with a first terminal to which an input signal is input and a second terminal connected to a first power supply, and a positive phase A third terminal for outputting a signal, a fourth terminal for outputting a reverse phase signal, and a fifth terminal connected to the second power source are provided, and N windings (N is 1) shaped along a part of the first inductor. A second number of annular second inductors, a conversion element for converting the input signal into the positive phase signal and the negative phase signal, a source connected to a third power source, and the positive phase signal at the gate A first transistor that is input, a source that is connected to a fourth power supply, a second transistor that receives the reverse-phase signal input to a gate, and a connection between the gate of the first transistor and the drain of the second transistor The first impedance circuit to be A second impedance circuit connected between a gate of the second transistor and a drain of the first transistor; a drain connected to the drain of the first transistor; and a drain of the second transistor; a first output terminal; An output matching circuit for outputting the first distribution signal and the second distribution signal from the output terminals, respectively.

  A multistage power amplification distribution circuit according to an aspect of the present disclosure is a multistage power amplification distribution circuit that connects a plurality of power amplification distribution circuits, and each of the plurality of power amplification circuits receives an input signal as an input signal. A first winding-shaped first inductor provided with a first terminal to be connected and a second terminal connected to the first power source, and a third terminal for outputting a positive phase signal and a fourth terminal for outputting a negative phase signal And a fifth terminal connected to a second power source, and having an N-shaped second inductor with N windings (N is a number greater than 1) shaped along a part of the first inductor, and the input signal Is converted to the positive phase signal and the negative phase signal, a source is connected to the third power source, the first transistor is input to the gate of the positive phase signal, the source is connected to the fourth power source, A second transistor in which the negative-phase signal is input to the gate; A first impedance circuit connected between the gate of the first transistor and the drain of the second transistor; and a second impedance connected between the gate of the second transistor and the drain of the first transistor. An output matching circuit connected to the drain of the first transistor and the drain of the second transistor and outputting a first distribution signal and a second distribution signal from the first output terminal and the second output terminal, respectively. The first output terminal of the first power amplification distribution circuit is connected to the first terminal of the second power amplification distribution circuit, and the second output terminal of the first power amplification distribution circuit is X output terminals connected to the first terminals of the three power amplification distribution circuits and not connected to the first terminals of the plurality of power amplification distribution circuits (X is an integer of 2 or more). , And it outputs a divided signal of the X lines.

  Note that these comprehensive or specific aspects may be realized by a system, method, integrated circuit, computer program, or recording medium. Any of the system, apparatus, method, integrated circuit, computer program, and recording medium may be used. It may be realized by various combinations.

  According to one aspect of the present disclosure, it is possible to realize a small power amplification distribution circuit that can amplify signal power with high efficiency and distribute the signal power to a plurality of systems.

  Further advantages and effects in one aspect of the present disclosure will become apparent from the specification and drawings. Such advantages and / or effects are provided by some embodiments and features described in the description and drawings, respectively, but all need to be provided in order to obtain one or more identical features. There is no.

The figure which shows the structure of the power amplification distribution circuit disclosed by the nonpatent literature 1. The figure which shows the constitution of the differential amplifier circuit which uses the cross couple capacitor Plan view showing an example of a transformer-type balun of one roll Sectional view along line X1-X2 in FIG. 3A A circuit diagram showing an example of composition of a power amplification distribution circuit concerning Embodiment 1 of this indication A circuit diagram showing an example of composition of a power amplification distribution circuit concerning Embodiment 1 of this indication The figure which shows the 1st example of the characteristic comparison of the power amplification distribution circuit which concerns on Embodiment 1 of this indication. The figure which shows the 2nd example of the characteristic comparison of the power amplification distribution circuit which concerns on Embodiment 1 of this indication The top view which shows the 1st structural example of the transformer type balun whose turns ratio is 1: 2. Sectional drawing in line X1-X2 of FIG. 7A The top view which shows the 2nd structural example of the transformer type balun whose turns ratio is 1: 2. Sectional view taken along line X1-X2 in FIG. 8A The figure which shows the structural example of the power amplification distribution circuit which concerns on Embodiment 2 of this indication. The figure which shows the 1st example of a structure of the detector in Embodiment 2 of this indication. The figure which shows the 2nd example of a structure of the detector in Embodiment 2 of this indication. A flowchart showing a first example of a phase control method according to the second embodiment of the present disclosure. Flowchart illustrating a second example of the phase control method according to the second embodiment of the present disclosure. Flowchart illustrating a third example of the phase control method according to the second embodiment of the present disclosure. 8 is a flowchart illustrating an example of a phase adjustment order control method according to the second embodiment of the present disclosure. Plan view showing a configuration example of a transformer type balun having a turns ratio of 1: 1.5.

  FIG. 1 is a diagram illustrating a configuration of a power amplification distribution circuit 100 disclosed in Non-Patent Document 1.

  The power amplification distribution circuit 100 includes an amplification circuit 101 and Wilkinson power distribution circuits 102-1 to 102-n.

Amplifier circuit 101 is a single-phase output amplifier circuit amplifies an input signal V _in, and outputs the amplified signal to the Wilkinson power divider circuit 102-1.

  The Wilkinson power distribution circuit 102-1 distributes the signal input from the amplifier circuit 101 into two systems, outputs one of the divided signals to the Wilkinson power distribution circuit 102-2, and outputs the other signal to the Wilkinson power distribution circuit 102. To -3. Similarly, the Wilkinson power distribution circuit 102-2 to Wilkinson power distribution circuit 102-n distribute the input signal to two systems.

With this configuration, the power amplifier distribution circuit 100 which is disclosed in Non-Patent Document 1 amplifies an input signal _{V in,} x line (x is an integer of 2 or more) of the output signal (output signal _{V out1} ~ output signal V _outx ).

  However, since the Wilkinson power distribution circuits 102-1 to 102-n are based on the operating principle using the wavelength of the signal passing therethrough, the power loss associated with the expansion of the circuit size is large, so the amplification factor is low.

  There are a maximum available gain (MAG) and a stability coefficient (Kf) as indexes for evaluating the performance (for example, the magnitude of power loss) in the high frequency band of the amplifier circuit.

MAG indicates the theoretical maximum amplification factor in the configuration of the amplifier circuit. Kf quantitatively indicates whether the amplifier circuit oscillates. MAG and Kf are expressed by the following expressions (1) and (2) using the Y parameters (Y11, Y12, Y21, Y22) of the amplifier circuit.

MAG = | Y21 / Y12 | * (Kf- (Kf ^ 2-1) ^ (1/2))… (1)
Kf = {2Re [Y11] Re [Y22] -Re [Y12 * Y21]} / | Y21 * Y12 |… (2)

  The larger the MAG value, the smaller the theoretical power loss of the amplifier circuit, which means that the signal can be amplified with higher efficiency. Further, the larger the value of Kf, the more the signal can be stably amplified by suppressing the oscillation of the amplifier circuit.

  As a configuration for amplifying millimeter-wave band signals with high efficiency, there is a differential amplifier circuit using a cross-coupled capacitor. FIG. 2 is a diagram showing a configuration of a differential amplifier circuit 200 using a cross-coupled capacitor.

The differential amplifier circuit 200 includes a transistor 201, a transistor 202, a capacitor 203, and a capacitor 204. The differential amplifier circuit 200, an input signal _{V in,} and an input signal _{-V in} the input. Phase as the input signal _{-V in} the phase of the input signal _{V in} is different 180 °

The source terminal of the transistor 201 is grounded. The gate terminal of the transistor 201, the input signal _{V in} is inputted. The source terminal of the transistor 202 is grounded. An input signal −V _in is input to the gate terminal of the transistor 202.

  The capacitor 203 has a capacitance value Cx and is connected between the drain terminal of the transistor 201 and the gate terminal of the transistor 202. The capacitor 204 has a capacitance value Cx and is connected between the drain terminal of the transistor 202 and the gate terminal of the transistor 201.

  The gate terminal of the transistor 201 and the gate terminal of the transistor 202 are connected to an input matching circuit (not shown). The gate voltages of the transistors 201 and 202 are supplied through the input matching circuit.

  The drain terminal of the transistor 201 and the drain terminal of the transistor 202 are connected to an output matching circuit (not shown). The drain voltages of the transistors 201 and 202 are supplied through the output matching circuit.

Then, the output signal V _out is output from the drain terminal side of the transistor 201, and the output signal −V _out is output from the drain terminal side of the transistor 202. The phase of the output signal V _{out and} the phase of the output signal −V _out differ by 180 °.

The Y parameters Y12 and Y21 of the differential amplifier circuit 200 are expressed by the following equations (3) and (4), respectively.

Y12 = -jω (Cgd-Cx) (3)
Y21 = gm-jω (Cgd-Cx) (4)

  Here, Cgd represents the value of the parasitic capacitance between the gate and drain of the transistors 201 and 202, and gm represents the transconductance of the transistors 201 and 202.

  In Expressions (3) and (4), Y12 and Y21 can be reduced by canceling the parasitic capacitance value Cgd by the capacitance value Cx. In particular, as Y12 decreases, the value of MAG shown in Equation (1) increases, and the theoretical maximum amplification factor of the differential amplifier circuit 200 increases. Further, as Y12 becomes smaller, the value of Kf shown in Expression (2) becomes larger, so that the stability of the differential amplifier circuit 200 is improved. That is, as Y12 becomes smaller, the amplification factor and stability of the differential amplifier circuit 200 are improved.

  In order to apply the differential amplifier circuit 200 shown in FIG. 2 to a power amplifier distribution circuit, a balun for converting a single-phase signal into a differential signal is required on both sides of the input and output. The balun has a distributed constant type configuration such as a rat race type and a lumped constant type configuration such as a transformer type.

  The configuration of the distributed constant type is large in circuit size and power loss, like the Wilkinson power distribution circuits 102-1 to 102-n shown in FIG. On the other hand, a lumped constant type balun such as a transformer type has the advantages of small size and low loss.

However, a balun having a lumped-constant configuration such as a transformer type has a large phase error of the converted differential signal due to the asymmetry of the structure and external parasitic components depending on the internal or connection destination. When this phase error is taken into account, Y12 and Y21 shown in the equations (3) and (4), respectively, are replaced by the following equations (5) and (6), respectively.

Y12 = −jω (Cgd−Cx * EXP (jθ _b )) (5)
Y21 = gm1-jω (Cgd-Cx * EXP (jθ _a )) (6)

Here, θ _a and θ _b are phase errors with respect to an ideal differential signal. Specifically, θ _a and θ _b represent phase errors from 180 °. θ _a and θ _b are functions of the frequency f of the signal, respectively.

When θ _a and θ _b , which are functions of the frequency f of the signal, are 180 ° at a specific frequency fs, the values of EXP (jθ _b ) and EXP (jθ _a ) are −1. Therefore, the Cx terms (that is, -Cx * EXP (jθ _b ) and -Cx * EXP (jθ _a )) in the equations (5) and (6) become positive, and the differential amplifying circuit 200 has the frequency fs. And positive feedback. As a result, the differential amplifier circuit 200 may become unstable and oscillate.

  As a configuration of the balun for suppressing the phase error, for example, there are configurations shown in FIGS. 3A and 3B. FIG. 3A is a plan view showing an example of a single transformer-type balun 300. 3B is a cross-sectional view taken along line X1-X2 in FIG. 3A. (A) to (e) in FIG. 3B correspond to (a) to (e) in FIG. 3A, respectively.

  A transformer balun 300 shown in FIG. 3A includes an unbalanced annular inductor 303 having a terminal 301 and a terminal 302, and a balanced side annular inductor 307 having a terminal 304, a terminal 305, and a terminal 306.

  Each of the unbalanced annular inductor 303 and the balanced annular inductor 307 is a highly symmetrical one-turn annular inductor. The ring portion of the balanced-side annular inductor 307 is provided inside the ring portion of the unbalanced-side annular inductor 303 in the plan view shown in FIG. 3A. As shown in FIG. 3B, the unbalanced annular inductor 303 is provided in the first layer, and the balanced annular inductor 307 is provided in the second layer located below the first layer. The unbalanced side annular inductor 303 and the balanced side annular inductor 307 may be the same size, or the balanced side annular inductor 307 may be larger than the unbalanced side annular inductor 303.

  The terminal 301 is a terminal to which a single-phase input signal is input, and the terminal 302 is a terminal to which DC power is supplied. The terminal 304 is a terminal from which a positive phase output signal is output, the terminal 305 is a terminal from which a negative phase output signal is output, and the terminal 306 is a center tap terminal to which DC power is supplied. Note that DC power may be supplied to the terminal 301 and a single-phase input signal may be input to the terminal 302. In this case, a normal phase output signal is output from the terminal 305 and a negative phase output signal is output from the terminal 304.

  The transformer-type balun 300 shown in FIGS. 3A and 3B has a configuration in which a highly symmetrical one-turn annular inductor is used for each of the balanced side and the unbalanced side. It can be converted into a motion signal.

  However, in the transformer type balun 300 shown in FIGS. 3A and 3B, the transformer type balun 300 is limited to the one-turn annular inductor, and it is difficult to use the N-turn (N is an integer of 2 or more) annular inductor. The degree of freedom in design is low, and it is difficult to achieve optimum impedance conditions in the differential amplifier circuit. Therefore, the amplification factor of the differential amplifier circuit is lowered.

  In view of such circumstances, an object of the present disclosure is to provide a small power amplification distribution circuit capable of amplifying and distributing signal power with high efficiency.

  Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiment described below is an example, and the present disclosure is not limited to the following embodiment.

(Embodiment 1)
FIG. 4 is a circuit diagram illustrating a configuration example of the power amplification distribution circuit 401 according to the first embodiment of the present disclosure. Power amplifier distribution circuit 401 amplifies an input signal inputted from the input terminal T _in, and outputs the output signal of the positive phase output terminal T _outp, and outputs an output signal of the inverse-phase output terminal T _outn. That is, the power amplification distribution circuit 401 is a distribution circuit that distributes one input signal to two output signals.

  The power amplification distribution circuit 401 illustrated in FIG. 4 includes a transformer type balun 402, a transistor 403, a transistor 404, an impedance circuit 405, an impedance circuit 406, and an output matching circuit 407.

  The transformer type balun 402 is a single-phase-to-differential conversion circuit that converts an input signal into a signal having a normal phase and a signal having a reverse phase. The transformer type balun 402 also functions as an input matching circuit that performs impedance conversion.

  The transformer type balun 402 includes an unbalanced inductor 402a that is an annular inductor and a balanced inductor 402b that is an annular inductor. The balanced inductor 402b has a shape along a part of the unbalanced inductor 402a (see FIGS. 7A and 7B described later). The turn ratio between the unbalanced inductor 402a and the balanced inductor 402b is 1 to N (N is an integer of 2 or more).

Nonequilibrium side inductor 402a has a terminal T1 connected to the input terminal _{T in,} and a terminal T2 to be connected to ground (GND). An input signal is input to the terminal T1, and a voltage of 0 [V] is supplied to the terminal T2. Note that the terminal T2 may be connected to a DC power supply that supplies a voltage other than 0 [V].

The balanced inductor 402b includes a terminal T3 from which a positive phase signal is output, a terminal T4 from which a negative phase signal is output, and a terminal (center tap terminal) T5 to which a DC power source _Vg is supplied.

  The transformer type balun 402 is configured by magnetically coupling the unbalanced inductor 402a and the balanced inductor 402b, and functions as a balun that converts an input signal input from the terminal T1 into two signals that are in opposite phases to each other. To do.

  That is, the transformer type balun 402 has a one-turn annular non-circularity provided with a terminal T1 (first terminal) to which an input signal is input and a terminal T2 (second terminal) connected to a DC power source (first power source). The balanced-side inductor 402a (first inductor) is connected to a terminal T3 (third terminal) that outputs a normal phase signal, a terminal T4 (fourth terminal) that outputs a negative phase signal, and a DC power source (second power source). Terminal T5 (fifth terminal) and an N-balanced ring-shaped balanced inductor 402b (second inductor) having a shape along a part of the unbalanced inductor 402a (first inductor). It is a conversion element that converts a signal into a normal phase signal and a negative phase signal.

  Note that another circuit element such as a capacitor, an inductor, or a resistor may be connected to the unbalanced inductor 402a and / or the balanced inductor 402b of the transformer type balun 402 to constitute an input matching circuit. Thereby, the design freedom of the transformer type balun 402 is increased.

  A configuration example of the transformer type balun 402 will be described later.

  The gate terminal of the transistor 403 is connected to the terminal T3 of the balanced inductor 402b. A positive-phase signal is input from the transformer balun 402 to the gate terminal of the transistor 403. The source terminal of the transistor 403 is connected to the ground (GND) and supplied with a voltage of 0 [V]. Note that the source terminal of the transistor 403 may be connected to a DC power supply that supplies a voltage other than 0 [V]. The drain terminal of the transistor 403 is connected to the output matching circuit 407.

  The gate terminal of the transistor 404 is connected to the terminal T4 of the balanced inductor 402b. Then, a reverse-phase signal is input from the transformer type balun 402 to the gate terminal of the transistor 404. The source terminal of the transistor 404 is connected to the ground (GND) and supplied with a voltage of 0 [V]. Note that a DC power supply that supplies a voltage other than 0 [V] may be connected to a source terminal of the transistor 404. The drain terminal of the transistor 404 is connected to the output matching circuit 407.

  The impedance circuit 405 includes at least a capacitor and is connected between the gate terminal of the transistor 403 and the drain terminal of the transistor 404. The impedance circuit 405 feeds back a certain amount of signal from the drain terminal of the transistor 404 to the gate terminal of the transistor 403. The impedance circuit 405 has an impedance value Zx.

  The impedance circuit 406 includes at least a capacitor and is connected between the gate terminal of the transistor 404 and the drain terminal of the transistor 403. The impedance circuit 406 feeds back a certain amount of signal from the drain terminal of the transistor 403 to the gate terminal of the transistor 404. The impedance circuit 406 has an impedance value Zx.

  The impedance circuit 405 and the impedance circuit 406 may have a configuration in which a capacitor and a resistor are connected in series.

The output matching circuit 407 is supplied with the power supply voltage Vdd. The output matching circuit 407 performs a matching of the signals obtained from the drain terminal of the drain terminal of transistor 404 of the transistor 403, and outputs a signal from the output terminal _{T outp,} the output terminal _{T outp} of the output signal from the output terminal _{T outn} And out of phase signal. The output signal output from the output terminal T _outp and the output signal output from the output terminal T _outn are used as two distribution signals.

The output matching circuit 407 converts, for example, the impedance of the transistor 403 with reference to the drain terminal of the transistor 403 and the impedance of the transistor 404 with reference to the drain terminal of the transistor 404 so as to have desired impedances. In addition, the output matching circuit 407 includes, for example, the drain terminal of the transistor 403 and the drain terminal of the transistor 404 so that the impedance of the input terminal T _in is equal to the impedance of the output terminal T _{outp and} the impedance of the output terminal T _outn . Transform impedance.

As described above, the power amplification distribution circuit 401 illustrated in FIG. 4 includes the transformer balun 402 (conversion element), the transistor 403 (first element) whose source is connected to the DC power source (third power source), and the positive phase signal is input to the gate. 1 transistor), a source connected to a DC power supply (fourth power supply), a transistor 404 (second transistor) in which a reverse phase signal is input to the gate, and a connection between the gate of the transistor 403 and the drain of the transistor 404 An impedance circuit 405 (first impedance circuit), an impedance circuit 406 (second impedance circuit) connected between the gate of the transistor 404 and the drain of the transistor 403, a drain of the transistor 403, and a drain of the transistor 404 It is connected to, out the output terminals _{T outp} (first And an output matching circuit 407 outputs the terminal) and the output terminal T _{outn (second} output terminal) the output signals from the (first distribution signal) and the first distributed signal and the negative phase of the output signal (the second distributed signal) Prepare. The power amplifier distribution circuit 401 amplifies an input signal inputted from the input terminal _{T in,} and outputs an output terminal _{T outp,} different output signals respectively from the output terminals _{T outn} phase.

The power amplification distribution circuit 401 shown in FIG. 4 increases the number of distribution systems by connecting the input terminal T _in of another power amplification distribution circuit 401 to the output terminal T _outp and / or the output terminal T _outn. Can do. Such a configuration example will be described with reference to FIG.

FIG. 5 is a circuit diagram showing a configuration example of the power amplification distribution circuit 411 according to the first embodiment. To the power amplifier distribution circuit 411, the input signal _{V in} is inputted. The power amplification / distribution circuit 411 outputs x-system output signals (output signal V _out1 to output signal V _outx (x is an even number equal to or greater than 2)). That is, the power amplification distribution circuit 411 distributes one system of input signals to x systems of output signals.

  A power amplification distribution circuit 411 illustrated in FIG. 5 includes a plurality of power amplification distribution circuits 401 (power amplification distribution circuit 401-1 to power amplification distribution circuit 401-n). The power amplification distribution circuit 411 has a multi-stage configuration in which the power amplification distribution circuit 401 is connected over a plurality of stages. Hereinafter, the power amplification / distribution circuit 401 of the power amplification / distribution circuit 411 will be described in the order of the first and second stages from the side closer to the input side.

Specifically, the input terminal _{T in} the first stage of the power amplifier distribution circuit 401-1, the input signal _{V in} is inputted. The output terminal _{T outp} of the power amplifier distribution circuit 401-1 is connected to the input terminal _{T in} the second stage of the power amplifier distribution circuit 401-2, the output terminal _{T outn} of the power amplifier distribution circuit 401-1 connected to the input terminal _{T in} the second stage power amplifier distribution circuit 401-3. Similarly, the input terminal T _in of each power amplification distribution circuit 401 at the third stage is connected to the output terminal T _outp or the output terminal T _outn of each power amplification distribution circuit 401 at the _previous stage.

That is, the power amplification distribution circuit 411 is a multi-stage power amplification distribution circuit in which a plurality of power amplification distribution circuits 401 (401-1 to 401-n) are connected. power amplifier distribution circuit) of the output terminal _{T outp} (first output terminal) is connected to the input terminal _{T in} the power amplifier distribution circuit 401-2 (second power amplifier distribution circuit), the power amplifier distribution circuit 401-1 The output terminal T _outn (second output terminal) is connected to the input terminal T _in of the power amplification distribution circuit 401-3 (third power amplification distribution circuit). The power amplifier distribution circuit 411, power amplifier distribution circuit 401- (n + 1-x / 2) ~401-n output terminals _{T outp} and the output terminal _{T outn} (i.e., the input terminal T of the other of the power amplifier distribution circuit 401 x distribution signals are output from x output terminals not connected to _in ).

  With the configuration shown in FIG. 5, the power amplification / distribution circuit 411 distributes the input signal to the desired number of output signals.

With this configuration, since a distribution circuit such as the Wilkinson power distribution circuit (see FIG. 1) can be omitted, it is possible to amplify and distribute power with a small size and low loss. Further, since a balun for converting a differential signal into a single-phase signal can be omitted on the output side (for example, the output terminal T _outp and the output terminal T _{outn of} the power amplification distribution circuit 401-1), the expressions (5) and ( phase error theta _a and theta _b shown in 6) can be reduced. As a result, the design flexibility of the input-side transformer-type balun 402 is increased, and a power amplification distribution circuit having a balun with an optimum power amplification factor can be realized.

FIG. 5 shows an example in which the number of power amplification distribution circuits 401 in each stage is the same as the number of output terminals T _outp and output terminals T _outn of each power amplification distribution circuit 401 in the previous stage. The number of the power amplification distribution circuits 401 may not be the same as the number of the output terminals T _outp and output terminals T _outn of the power amplification distribution circuits 401 in the previous stage.

Further, in each stage, the example in which the power amplification distribution circuit 401 is connected to the output terminal T _outp and / or the output terminal T _outn of each power amplification distribution circuit 401 in the previous stage has been described, but the present disclosure is not limited thereto. A balun (for example, a transformer type balun) may be connected to the output terminal T _outp and / or the output terminal T _outn of each power amplification distribution circuit 401 in the previous stage. By connecting a balun instead of the power amplification distribution circuit 401, the power consumption of the entire circuit can be reduced when the power amplification can be omitted.

  Next, the characteristics of the amplification factor of the power amplification / distribution circuit 401 according to the present embodiment shown in FIG. 4 will be described with reference to FIGS. 6A and 6B.

  FIG. 6A is a diagram showing a first example of characteristic comparison of the power amplification / distribution circuit 401 according to the first embodiment. FIG. 6A shows the characteristics of the power amplification distribution circuit 401 designed to operate in the 60 GHz band. In the characteristic shown in FIG. 6A, as an example, the turns ratio of the transformer type balun 402 of the power amplification distribution circuit 401 is set to 1: 2.

  In FIG. 6A, the horizontal axis indicates the frequency of the input / output signal. Further, the vertical axis of FIG. 6A indicates the amplification factor normalized by using the maximum amplification factor of the power amplification distribution circuit 401 indicated by the solid line of FIG. 6A in decibels (dB). In this case, the maximum amplification factor of the power amplification distribution circuit 401 indicated by the solid line in FIG. 6A is 0 dB.

  The comparative configuration 1 in FIG. 6A is a configuration in which the one transformer-type balun 300 shown in FIGS. 3A and 3B is provided at both the input terminal and the output terminal of the power amplifier circuit. Specifically, in the comparative configuration 1, the transformer type balun 402 in the power amplification distribution circuit 401 shown in FIG. 4 is replaced with one transformer type balun (for example, one transformer type balun 300 shown in FIGS. 3A and 3B). ), Instead of the output matching circuit 407 in the power amplification distribution circuit 401, as a matching circuit, one turn for converting the differential signal output from the drain terminal of the transistor 403 and the drain terminal of the transistor 404 into a single-phase signal The transformer type balun is connected.

  The amplification factor characteristic of the power amplification distribution circuit 401 having the transformer type balun 402 on the input side, which has a one-to-two turns ratio shown in FIG. 6A, is superior to the comparative configuration 1 at all frequencies of 40 GHz to 80 GHz. Show.

  FIG. 6B is a diagram illustrating a second example of the characteristic comparison of the power amplification distribution circuit 401 according to the first embodiment. FIG. 6B shows the characteristics of the power amplification distribution circuit 401 designed to operate in the 60 GHz band. In FIG. 6B, as an example, the turns ratio of the transformer type balun 402 of the power amplification distribution circuit 401 is set to 1: 2.

  In FIG. 6B, the horizontal axis indicates the frequency of the input / output signal. In addition, the vertical axis of FIG. 6B indicates the amplification factor normalized by the maximum amplification factor of the power amplification distribution circuit 401 indicated by the solid line in FIG. 6B in decibels (dB). That is, the maximum amplification factor of the power amplification / distribution circuit 401 indicated by the solid line in FIG. 6B is 0 dB.

  6B is a configuration in which a transformer type balun having a turns ratio of 1: 2 is provided at both the input terminal and the output terminal of the power amplifier circuit.

  The gain characteristics of the comparative configuration 2 shown in FIG. 6B temporarily increase at a frequency near 65.7 GHz. This temporary increase in the amplification factor is due to the fact that the comparative configuration 2 oscillates at a frequency near 65.7 GHz. On the other hand, the gain characteristic of the power amplification / distribution circuit 401 does not increase temporarily. That is, the power amplification / distribution circuit 401 can suppress oscillation and achieve an optimum amplification factor.

  Next, a first configuration example of the transformer type balun 402 will be described with reference to FIGS. 7A and 7B.

  FIG. 7A is a plan view showing a first configuration example of a transformer type balun 402 having a turns ratio of 1: 2. 7B is a cross-sectional view taken along line X1-X2 in FIG. 7A. (A) to (g) in FIG. 7B correspond to (a) to (g) in FIG. 7A, respectively. 7A and 7B, the same reference numerals are assigned to the same components as those in FIG.

  In the semiconductor process, a plurality of metal layers are formed. Depending on the metal layer, the thickness may be different. For example, in a three-layer structure including a first layer, a second layer, and a third layer, even if the thickness of the first layer is the same as the thickness of the second layer, the thickness of the first layer and the thickness of the second layer May be different.

  The transformer type balun 402 is configured to have a desired number of turns by connecting wiring parts of annular inductors formed in different layers with vias.

Specifically, the non-equilibrium inductor 402a is formed in the first layer that is the thickest metal layer. The first layer is a layer having the lowest resistance value. Then, as described above, the terminal T1 is connected to the input terminal _{T in,} terminal T2 is connected to the ground or DC power supply. The terminal T2 is connected to the input terminal _{T in,} terminal T1 may be connected to ground or DC power supply.

  In the balanced-side inductor 402b, a part of the wiring is formed in the first layer, and the other part of the wiring is formed in the second layer positioned below the first layer. Specifically, in the portion where the wires of the balanced inductor 402b overlap on a plane (frame W1: FIG. 7A, hereinafter referred to as the first cross portion), one wire of the balanced inductor 402b is on the second layer. The other wiring of the balanced inductor 402b is formed in the first layer. The wiring formed in the first layer and the wiring formed in the second layer of the balanced inductor 402b are connected by a via 701. In the first cross part, the wiring of the balanced inductor 402b is dropped to the second layer, which is the lower layer, via the via 701. In the other parts than the first cross part, the wiring of the balanced inductor 402b is connected to the first layer via the via 701. Raised.

  As described above, DC power is supplied to the terminal (center tap terminal) T5, and a positive-phase signal and a negative-phase signal are output from the terminal T3 and the terminal T4, respectively.

  The minimum diameter of the unbalanced inductor 402a is larger than the maximum diameter of the balanced inductor 402b. In a plan view, the balanced inductor 402b is formed inside the unbalanced inductor 402a.

  With this configuration, since the asymmetric capacitive coupling between the balanced side and the unbalanced side can be reduced, the phase error of the output differential signal can be reduced, and the degree of freedom in design can be increased.

  Moreover, since the wiring of the unbalanced inductor 402a and the wiring of the balanced inductor 402b are formed in the first layer having the lowest resistance value except for the first cross portion of the wiring, a balun with a small loss can be realized.

  7A and 7B is an example in which the wiring of one inductor is dropped to the second layer via the via 701 and is raised to the first layer except for the first cross portion. In the first cross portion, the wiring of one inductor may be raised to a layer above the first layer through a via.

  In a high frequency band such as the millimeter wave band, virtual grounding at the connection point between the center tap terminal T5 and the balanced inductor 402b is not sufficient. Therefore, the power amplification distribution circuit 401 may oscillate due to the influence of the inductance of the center tap terminal T5. Therefore, the thickest metal layer (see FIG. 7A) until the distance between the center tap terminal T5 connected to the connection point and the wiring of the balanced-side inductor 402b or the unbalanced-side inductor 402a becomes, for example, the minimum pitch in the design rule. 7B, and is then lowered to the second layer via the via 701, and the wiring for the center tap terminal T5 in the first layer except for the second cross portion (frame W2 in FIG. 7A) And the distance between the balanced-side inductor 402b and the unbalanced-side inductor 402a are increased to the first layer, for example, at a location where the design rule has a minimum pitch.

  The center tap terminal T5 may be raised from the first layer to the upper layer via the via at the second cross portion, and may be lowered to the first layer via the via other than the second cross portion. Further, the center tap terminal T5 may be configured to be stacked over all layers and to delete the crossing layer (the first layer in FIGS. 7A and 7B) at a place other than the second crossing portion.

  Next, a second configuration example of the transformer type balun 402 having a turns ratio of 1: 2 will be described with reference to FIGS. 8A and 8B.

  FIG. 8A is a plan view showing a second configuration example of the transformer type balun 402 having a turns ratio of 1: 2. 8B is a cross-sectional view taken along line X1-X2 in FIG. 8A. (A) to (g) in FIG. 8B correspond to (a) to (g) in FIG. 8A, respectively. 8A and 8B, the same reference numerals are assigned to the same components as those in FIG.

  The difference between the configuration shown in FIGS. 8A and 8B and the configuration shown in FIGS. 7A and 7B is that the layer on which the wiring of the balanced-side inductor 402b is formed is different.

  Specifically, in FIGS. 7A and 7B, the wiring of the balanced inductor 402b formed in the first layer is formed in the second layer in FIGS. 8A and 8B. 7A and 7B, the wiring of the balanced-side inductor 402b formed in the second layer is formed in the third layer in FIGS. 8A and 8B.

  Note that the order of the layers is reversed, for example, in FIG. 7A and FIG. 7B, the wiring of the balanced inductor 402b formed in the first layer is formed in the third layer, and in FIG. 7A and FIG. The wiring of the balanced inductor 402b formed in the layer may be formed in the second layer.

  As described above, since the degree of freedom increases with respect to the relationship between the diameter of the unbalanced inductor 402a and the diameter of the balanced inductor 402b, a more flexible design can be performed.

  As described above, in the power amplifying / distributing circuit 401 according to the first embodiment, the transformer type balun for converting one system signal into the differential signal is provided on the input side of the differential amplifier circuit, and the differential amplifier circuit is the transformer type. The differential signal output from the balun is amplified, and the amplified differential signal is output as two distribution signals.

  As described above, since the distribution signal can be output without providing the transformer type balun at the output of the differential amplifier circuit, the power of the signal can be amplified with high efficiency and distributed to a plurality of systems. In addition, it is possible to suppress the increase in circuit size and realize a small power amplification distribution circuit.

(Embodiment 2)
In the second embodiment, an example in which a configuration for controlling the phase of the distribution signal is provided at the output of the power amplification distribution circuit described in the first embodiment will be described.

  FIG. 9 is a diagram illustrating a configuration example of the power amplification distribution circuit 811 according to the second embodiment. In FIG. 9, the same components as those in FIGS. 4 and 5 are denoted by the same reference numerals, and description thereof is omitted.

The power amplification distribution circuit 811 shown in FIG. 9 has phase shifters (φ) 801-1 to 801-x and directional couplers 802-1 to 802-1 on the output side of the power amplification distribution circuit 411 shown in FIG. 802-x, detectors (DET) 803-1 to 803- (x-1), terminations (Z _term ) 804-1 and 804-2, and a phase controller 805 are provided.

In the following description, the phases of the x system output signals output from the power amplification / distribution circuit 411 will be described as θ _{1 to} θ _x , respectively.

The phase shifter 801-i (i is an integer not less than 1 and not more than x) acquires a control signal indicating the phase amount to be adjusted (phase adjustment amount Δθ _i ) from the phase controller 805. Then, the phase shifter 801-i adjusts the phase θ _i of the i-th system output signal output from the power amplification distribution circuit 411 to the phase θ _{i_ad} based on the control signal. Here, θ _{i_ad} = θ _i + Δθ _i . Then, the phase shifter 801-i outputs the signal after phase adjustment of the i-th system to the directional coupler 802-i.

  The directional coupler 802-i has one input port and three output ports, and branches and outputs a signal acquired from the input port to the three output ports.

The directional coupler 802-1 outputs the first system phase-adjusted signal acquired from the phase shifter 801-1 to the terminal 804-1 and the detector 803-1. Also, the signal after the phase adjustment of the first system is, as the output signal V _out1 from the remaining one output port of the directional coupler 802-1, for example, frequency conversion, (not shown) signal processing unit for performing a demodulation process Is output.

The directional coupler 802-j outputs the jth system phase-adjusted signal acquired from the phase shifter 801-j to the detector 803- (j-1) and the detector 803-j. Further, the signal after the phase adjustment of the j-th system is output from the remaining one output port of the directional coupler 802-j as an output signal _Voutj , for example, a signal processing unit (not shown) that performs frequency conversion and demodulation processing. Is output.

The directional coupler 802-x outputs a signal after phase adjustment of the x-th system acquired from the phase shifter 801-x to the detector 803- (x-1) and the terminal 804-2. In addition, the signal after phase adjustment of the x-th system is output from the remaining one output port of the directional coupler 802-x as an output signal _Voutx , for example, a signal processing unit (not shown) that performs frequency conversion and demodulation processing. Is output.

Detectors 803-k (k is an integer of 1 to x-1) are acquired from the k-system phase-adjusted signal acquired from the directional coupler 802-k and the directional coupler 802- (k + 1). The phase difference from the phase-adjusted signal of the (k + 1) th system is calculated, and a signal V _dck indicating the calculated phase difference is output to the phase controller 805. A configuration example of the detectors 803-1 to 803- (j-1) will be described later.

  The end 804-1 is provided to improve the operation accuracy of the directional coupler 802-1. Terminator 804-1 terminates the signal after phase adjustment of the first system output from directional coupler 802-1.

  The end 804-2 is provided in order to increase the operation accuracy of the directional coupler 802-x. The termination 804-2 terminates the x-th system phase-adjusted signal output from the directional coupler 802-x.

Phase controller 805, based on each detector 803-1～803- signal output (x-1) from the _{V dc1 ~V dc (x-1} ), to adjust the phase shifters 801-1~801-x The phase amount (phase adjustment amount Δθ _{1 to} Δθ _x ) is determined, and a control signal indicating the phase adjustment amount is output.

  Details of the phase control method will be described later.

  Next, taking the detector 803-k as an example, the configuration of the detectors 803-1 to 803- (j-1) will be described.

  FIG. 10 is a diagram illustrating a first example of the configuration of the detector 803-k according to the second embodiment. The detector 803-k includes an adder 901 and a non-linear circuit (nonliner) 902.

  The adder 901 outputs the k-th system phase-adjusted signal output from the directional coupler 802-k and the k + 1-th system phase-adjusted signal output from the directional coupler 802- (k + 1). to add. The adder 901 outputs the added signal to a non-linear circuit (nonliner) 902.

The nonlinear circuit 902 calculates a DC component signal V _dck indicating a phase difference between the k-th system phase-adjusted signal and the k + 1-th system phase-adjusted signal, using the second-order distortion of the added signal. And output to the phase controller 805 (see FIG. 9).

Specifically, when the signal after phase adjustment of the k-th system and the signal after phase adjustment of the (k + 1) -th system are in-phase signals (that is, the phase difference is zero), the amplitude of the signal added by the adder 901 is Since it becomes the maximum, V _dck calculated from the secondary distortion becomes the maximum.

On the other hand, when the signal after phase adjustment of the k-th system and the signal after phase adjustment of the (k + 1) -th system are opposite in phase (that is, the phase difference is 180 °), the amplitude of the signal added by the adder 901 is minimum. Therefore, V _dck calculated from the secondary distortion is minimum.

In the case where the signal after the phase adjustment of the k-th system and the signal after the phase adjustment of the (k + 1) -th system are opposite in phase, the amplitude of the signal added by the adder 901 is zero, that is, input to the nonlinear circuit 902. This is equivalent to zero signal. In such a case, the nonlinear circuit 902 outputs a constant bias voltage V _sta as a DC component signal V _dck .

That is, when the signal after phase adjustment of the k-th system and the signal after phase adjustment of the (k + 1) _-th system are in-phase signals (that is, the phase difference is zero), V _dck −V _sta becomes maximum, and the k-th system When the signal after the phase adjustment and the signal after the phase adjustment of the (k + 1) _-th system are opposite in phase (that is, the phase difference is 180 °), V _dck −V _sta becomes zero.

  FIG. 11 is a diagram illustrating a second example of the configuration of the detector 803-k according to the second embodiment. The detector 803-k includes a multiplier 1001 and a low-pass filter (hereinafter referred to as LPF) 1002.

  The multiplier 1001 outputs the k-th system phase-adjusted signal output from the directional coupler 802-k and the k + 1-th system phase-adjusted signal output from the directional coupler 802- (k + 1). Multiply. Multiplier 1001 outputs the multiplied signal to LPF 1002. The multiplied signal includes a direct current component and a harmonic component of the frequency of the signal after phase adjustment.

The LPF 1002 removes harmonic components contained in the multiplication signal output from the multiplier 1001 and outputs a DC component. Then, the LPF 1002 outputs a signal V _dck obtained by adding a constant bias voltage V _sta to the calculated DC component to the phase controller 805 (see FIG. 9).

Specifically, when the signal after phase adjustment of the k-th system and the signal after phase adjustment of the (k + 1) -th system are in-phase signals (that is, the phase difference is zero), the DC component of the signal multiplied by the multiplier 1001 Since _Vdck is maximum, the calculated V _dck is maximum.

When the signal after the phase adjustment of the k-th system and the signal after the phase adjustment of the (k + 1) -th system are opposite in phase (that is, the phase difference is 180 °), the DC component of the signal multiplied by the multiplier 1001 is the minimum. _Therefore , the calculated V _dck is minimum.

When the phase difference between the signal after phase adjustment of the k-th system and the signal after phase adjustment of the (k + 1) -th system is 90 ° or 270 °, the direct current component of the signal multiplied by the multiplier 1001 is zero, so that the calculation is performed. V _dck becomes V _sta .

  As described above, with the configuration of the detector 803-k shown in FIGS. 10 and 11, a DC component signal indicating the phase difference between the two signals input to each detector is calculated and output to the phase controller 805.

The V _dck output from the detector 803-k shown in FIG. 10 and FIG. 11 is a signal in which the signal after phase adjustment of the k-th system and the signal after phase adjustment of the (k + 1) _-th system are in phase (that is, the level). When the phase difference is zero), the maximum is obtained, and when the signal after phase adjustment of the k-th system and the signal after phase adjustment of the (k + 1) -th system are opposite in phase (that is, the phase difference is 180 °), the signal is minimized. .

Furthermore, V _dck output from the detector 803-k shown in FIG. 11 is when the phase difference between the k-th phase adjusted signal and the (k + 1) th phase adjusted signal is 90 ° or 270 °. The bias voltage is V _sta .

  Note that although an example in which the detector 803-k includes the LPF 1002 is shown in FIG. 11, the present disclosure is not limited to this. For example, the phase controller 805 may include an LPF, and the LPF of the phase controller 805 may remove harmonic components included in the signal output from the detector 803-k.

  Next, a phase control method according to the second embodiment will be described. In the following, a control method for increasing or decreasing an amount (phase adjustment amount Δθ) of changing the phase of the output signal of the k-th system so that the phases of the k-th system output signal and the (k + 1) -th system output signal are in phase. Is described as an example.

FIG. 12 is a flowchart illustrating a first example of the phase control method according to the second embodiment. In the flowchart shown in FIG. 12, the V _dck output from the detector 803-k is a signal in which the signal after phase adjustment of the k-th system and the signal after phase adjustment of the (k + 1) _-th system are in phase (that is, the phase difference is Zero) is the maximum, and when the signal after the phase adjustment of the k-th system and the signal after the phase adjustment of the (k + 1) -th system are opposite in phase (that is, the phase difference is 180 °), the signal is minimum. It is a flowchart based on this. For this reason, the flowchart shown in FIG. 12 is a flowchart that can operate with any of the configurations of the detectors 803-k in FIGS.

  In the flowchart illustrated in FIG. 12, after the initial flow 1101 is performed, the process proceeds to the second flow 1102 or the third flow 1103 depending on the determination result in the initial flow 1101.

In step 101 (S101), the phase controller 805 holds the V _dck output from the detector 803-k as a signal V _{dc_old} indicating a phase difference before adjusting the phase in S102 described later.

At S102, the phase controller 805 outputs a control signal to the phase theta _k adjusting [Delta] [theta] = .delta..theta of the output signal of the k-th line to the phase shifters 801-k. The phase shifter 801-k adjusts the output signal of the k-th system by Δθ based on the control signal, and outputs a signal after the phase adjustment of the k-th system having the phase θ _{k_ad} = θ _k + Δθ.

In step S103, the phase controller 805 holds the V _dck output from the detector 803-k as a signal V _{dc_new} indicating the adjusted phase difference. The phase controller 805 maintains the phase adjustment amount [Delta] [theta] at the present time as a [Delta] [theta] _o.

At S104, the phase controller 805 _determines whether _{V Dc_new} is greater than _{V dc_old.} If V _{dc_new} is larger than V _{dc_old} (YES in S104), the flow proceeds to S105. If V _{dc_new} is _{equal to} or lower than V _{dc_old} (NO in S104), the flow _proceeds to S110.

At S105, the phase controller _805, a _{V Dc_new,} held as a signal _{V Dc_old} indicating a phase difference before adjusting the phase in S106 to be described later.

At S106, the phase controller 805 outputs a phase θ control _{signal k} adjusts the Δθ = Δθo + δθ of the output signal of the k-th line to the phase shifters 801-k. The phase shifter 801-k adjusts the output signal of the k-th system by Δθ based on the control signal, and outputs a signal after the phase adjustment of the k-th system having the phase θ _{k_ad} = θ _k + Δθ. That is, the phase shifter 801-k further adjusts the phase θ _{k_ad} of the signal after phase adjustment by δθ.

In S107, the phase controller 805 holds the V _dck output from the detector 803-k as a signal V _{dc_new} indicating the phase difference after performing the phase adjustment in S106. The phase controller 805 maintains the phase adjustment amount [Delta] [theta] at the present time as a [Delta] [theta] _o.

At S108, the phase controller 805 _determines whether _{V Dc_new} is greater than _{V dc_old.} If V _{dc_new} is larger than V _{dc_old} (YES in S108), the flow returns to S105. If V _{dc_new} is _{equal to} or lower than V _{dc_old} (NO in S108), the flow _proceeds to S109.

At S109, the phase controller 805 outputs a phase θ control _{signal k} adjusts the Δθ = Δθo-δθ of the output signal of the k-th line to the phase shifters 801-k. The phase shifter 801-k adjusts the output signal of the k-th system by Δθ based on the control signal, and outputs a signal after the phase adjustment of the k-th system having the phase θ _{k_ad} = θ _k + Δθ. Then, the flow ends.

If V _{Dc_new} is below _{V Dc_old} at (NO in S104), S110, phase controller _805, a _{V Dc_new,} held as a signal _{V Dc_old} indicating a phase difference before adjusting the phase at S111 to be described later .

At S111, the phase controller 805 outputs a phase θ control _{signal k} adjusts the Δθ = Δθo + δθ of the output signal of the k-th line to the phase shifters 801-k. The phase shifter 801-k adjusts the output signal of the k-th system by Δθ based on the control signal, and outputs a signal after the phase adjustment of the k-th system having the phase θ _{k_ad} = θ _k + Δθ. That is, the phase shifter 801-k further adjusts the phase θ _{k_ad} of the signal after phase adjustment by δθ.

In S112, phase controller 805 holds V _dck output from detector 803-k as signal V _{dc_new} indicating the phase difference after performing phase adjustment in S111. The phase controller 805 maintains the phase adjustment amount [Delta] [theta] at the present time as a [Delta] [theta] _o.

At S113, the phase controller 805 _determines whether _{V Dc_new} is less than _{V dc_old.} If V _{dc_new} is smaller than V _{dc_old} (YES in S113), the flow returns to S110. If V _{dc_new} is _{equal to} or higher than V _{dc_old} (NO in S113), the flow proceeds to S114.

In step S114, the phase controller 805 outputs a control signal for adjusting the phase θ _k of the output signal of the k-th system by Δθ = Δθ _o −δθ + 180 ° to the phase shifter 801-k. The phase shifter 801-k adjusts the phase of the output signal of the k-th system based on the control signal, and outputs the signal after the phase adjustment of the k-th system having the phase θ _{k_ad} = θ _k + Δθ. Then, the flow ends.

As described above, V _dck output from the detector 803-k is a signal in which the signal after phase adjustment of the k-th system and the signal after phase adjustment of the (k + 1) _-th system are in phase (that is, the phase difference is zero). The signal after the phase adjustment of the k-th system and the signal after the phase adjustment of the (k + 1) -th system are opposite in phase (that is, the phase difference is 180 °).

Based on the magnitude relationship between the phase difference and V _dck , the phase control method shown in FIG. 12 adjusts the phase by Δθ in S102 of the initial flow 1101, and shows the phase difference after phase adjustment in S104. V _{dc_new} is compared with V _{dc_old} indicating the phase difference before phase adjustment.

_{When V Dc_new} is greater than _{V dc_old} (YES at S104), the phase adjustment in _S102, the _{direction V dck} increases, that is, indicates that the phase difference is a phase adjustment in a direction approaching zero. Therefore, in the second flow 1102, the phase adjustment amount Δθ is increased by δθ until V _dck becomes the maximum, that is, until the phase difference becomes zero.

On the other hand, when V _{dc_new} is _{equal to} or lower than V _{dc_old} (NO in S104), it indicates that the phase adjustment in S102 is a phase adjustment in a direction in which V _dck decreases, that is, in a direction in which the phase difference increases. Therefore, in the third flow 1103, the phase adjustment amount Δθ is increased by δθ until V _dck becomes the minimum, that is, until the phase difference reaches 180 °. In S114, the phase difference is made zero by adding 180 ° to the phase adjustment amount Δθ.

  Next, a phase control method different from that in FIG. 12 will be described.

  FIG. 13 is a flowchart illustrating a second example of the phase control method according to the second embodiment. In FIG. 13, the same processes as those in FIG. The flow chart shown in FIG. 13 is a flow chart that can be operated with any of the configurations of the detectors 803-k in FIGS. 10 and 11 in the same manner as the flow shown in FIG.

  The flowchart shown in FIG. 13 is a flowchart in which the third flow 1103 in FIG. Hereinafter, each step of the third flow 1203 will be described.

If V _{Dc_new} is less than _{V dc_old} (NO at S104), at S210, the phase controller _805, a _{V Dc_new,} held as a signal _{V Dc_old} indicating the phase difference before performing phase adjustment in S211.

At S211, the phase controller 805 outputs a phase θ control _{signal k} to adjust Δθ = Δθ _o -δθ of the output signal of the k-th line to the phase shifters 801-k. The phase shifter 801-k adjusts the output signal of the k-th system by Δθ based on the control signal, and outputs a signal after the phase adjustment of the k-th system having the phase θ _{k_ad} = θ _k + Δθ.

In S212, the phase controller 805 holds the V _dck output from the detector 803-k as a signal V _{dc_new} indicating the phase difference after performing the phase adjustment in S211. The phase controller 805 maintains the phase adjustment amount [Delta] [theta] at the present time as a [Delta] [theta] _o.

At S213, the phase controller 805 _determines whether _{V Dc_new} is greater than _{V dc_old.} If V _{dc_new} is larger than V _{dc_old} (YES in S213), the flow returns to S210. If V _{dc_new} is _{equal to} or lower than V _{dc_old} (NO in S213), the flow _proceeds to S214.

At S214, the phase controller 805 outputs a phase θ control _{signal k} adjusts the Δθ = Δθ _o + δθ of the output signal of the k-th line to the phase shifters 801-k. The phase shifter 801-k adjusts the output signal of the k-th system by Δθ based on the control signal, and outputs a signal after the phase adjustment of the k-th system having the phase θ _{k_ad} = θ _k + Δθ. Then, the flow ends.

In the flowchart of FIG. 13, as in FIG. 12, when V _{dc_new} is _{equal to} or less than V _{dc_old} (NO in S _<b> 104), the phase adjustment in S _<b> 102 decreases V _dck , that is, increases the phase difference. This indicates that the phase adjustment is performed.

Then, in the third flow 1103 of FIG. 12, the phase adjustment amount is increased by δθ until V _dck becomes the minimum, that is, until the phase difference reaches 180 °, and in S114, the phase adjustment amount is set to 180 °. The phase difference was made zero by adding. In the third flow 1203 of FIG. 13, considering that the phase adjustment in S102 is a phase adjustment in a direction in which V _dck decreases, that is, in a direction in which the phase difference increases, the amount of change in the phase adjustment amount Δθ in S211. Is changed to −δθ. With this change, in S211, phase adjustment is performed in the direction opposite to the phase adjustment in S102, that is, the direction in which V _dck increases (that is, the direction in which the phase difference decreases).

As described above, the phase difference between the two signals can be adjusted by the phase control method shown in FIGS. 12 and 13, for example, an output signal having the same phase can be output. Further, in the phase control method shown in FIGS. 12 and 13, since the determination is made based on the maximum value of V _dck output from the detector 803-k, high-precision phase control with a high signal-to-noise ratio is performed. It can be carried out.

  Next, a phase control method different from FIGS. 12 and 13 will be described.

FIG. 14 is a flowchart illustrating a third example of the phase control method according to the second embodiment. In the flowchart shown in FIG. 14, the V _dck output from the detector 803-k is a signal in which the signal after phase adjustment of the k-th system and the signal after phase adjustment of the (k + 1) _-th system (that is, the phase difference is Zero) is the maximum, and when the signal after the phase adjustment of the k-th system and the signal after the phase adjustment of the (k + 1) -th system are signals of opposite phases (that is, the phase difference is 180 °), the signal is minimum. It is a flowchart based on the point that when the phase difference between the phase-adjusted signal of the system and the signal after the phase adjustment of the (k + 1) -th system is 90 ° or 270 °, the bias voltage becomes V _sta . Therefore, the flowchart shown in FIG. 14 is a flow that can be operated with the configuration of the detector 803-k in FIG.

  In the flowchart illustrated in FIG. 14, after the initial flow 1301 is performed, the process proceeds to one of the second flow 1302, the third flow 1303, and the fourth flow 1304 according to the determination result in the initial flow.

In step S301, the phase controller 805 determines whether V _dck output from the detector 803-k is equal to V _sta . If V _dck is equal to V _sta (YES in S301), the flow _proceeds to S303 of the second flow 1302. If V _dck is not equal to V _sta (NO in S301), the flow proceeds to S302.

If V _dck is not equal to V _sta (NO in S301), in S302, phase controller 805 determines whether V _dck is greater than V _sta or not. If V _dck is greater than V _sta (YES in S302), the flow proceeds to S306 of the third flow 1303. If V _dck is equal to or lower than V _sta (NO in S302), the flow proceeds to S310 of the fourth flow 1304.

If V _dck is equal to _{V sta} (YES at S301), at S303, the phase controller 805, control signals 90 ° for adding the phase theta _k of the output signal of the k lines, i.e., the [Delta] [theta] = 90 ° The control signal shown is output to the phase shifter 801-k. The phase shifter 801-k adjusts the output signal of the k-th system by 90 ° based on the control signal, and outputs the signal after the phase adjustment of the k-th system having the phase θ _{k_ad} = θ _k + 90 °.

In step S304, the phase controller 805 determines whether V _dck is greater than V _sta .

If V _dck is greater than V _sta (YES in S304), the flow ends. If V _dck is less than _{V sta} (NO at S304), at S305, the phase controller 805, a control signal to 270 ° added to the phase theta _k of the output signal of the k lines, i.e., the [Delta] [theta] = 270 ° The control signal shown is output to the phase shifter 801-k. The phase shifter 801-k adjusts the output signal of the k-th system by + 270 ° based on the control signal, and outputs the signal after the phase adjustment of the k-th system having the phase θ _{k_ad} = θ _k + 270 °.

Second flow 1302 is a flow _executed when V _dck is equal to V _sta (YES in S301), that is, when the phase difference is 90 ° or 270 °. Therefore, in S303, by adjusting the phase by 90 °, the phase difference becomes zero or 180 °. In step S304, it is determined whether V _dck is greater than V _sta . The _case where V _dck is larger than V _sta (YES in S304) indicates that the phase difference can be adjusted to zero. Therefore, the subsequent processing is not performed and the flow ends. On the other hand, the case where V _dck is equal to or lower than V _sta (NO in S304) indicates a case where the phase difference is adjusted to 180 °. Therefore, in S305, the phase difference can be adjusted to zero by adjusting the phase by 270 °.

If V _dck is greater than V _sta (YES in S302), in S306, phase controller 805 outputs a control signal for adjusting phase θ _k of the output signal of the k-th system by Δθ = Δθ _o + δθ as phase shifter 801. Output to -k. The phase shifter 801-k adjusts the output signal of the k-th system by Δθ based on the control signal, and outputs a signal after the phase adjustment of the k-th system having the phase θ _{k_ad} = θ _k + Δθ. Note that Δθ _o holds 0 as an initial value.

At S307, the phase controller 805 maintains the phase adjustment amount [Delta] [theta] at the present time as a [Delta] [theta] _o.

In step S308, the phase controller 805 determines whether V _dck is greater than V _sta . If V _dck is greater than V _sta (YES in S308), the flow returns to S306. If V _dck is equal to or lower than V _sta (NO in S308), the flow _proceeds to S309.

At S309, the phase controller 805 outputs a phase θ control _{signal k} adjusts the Δθ = Δθ _o -90 ° of the output signal of the k-th line to the phase shifters 801-k. The phase shifter 801-k adjusts the phase of the output signal of the k-th system based on the control signal, and outputs the signal after the phase adjustment of the k-th system having the phase θ _{k_ad} = θ _k + Δθ. Then, the flow ends.

When V _dck is equal to or lower than V _sta (NO in S302), in S310, the phase controller 805 outputs a control signal for adjusting the phase θk of the output signal of the k-th system by Δθ = Δθ _o + δθ. output to k. The phase shifter 801-k adjusts the output signal of the k-th system by Δθ based on the control signal, and outputs a signal after the phase adjustment of the k-th system having the phase θ _{k_ad} = θ _k + Δθ.

At S311, the phase controller 805 maintains the phase adjustment amount [Delta] [theta] at the present time as a [Delta] [theta] _o.

In step S312, the phase controller 805 determines whether V _dck is smaller than V _sta . If V _dck is smaller than V _sta (YES in S312), the flow returns to S310. If V _dck is _equal to or higher than V _sta (NO in S312), the flow _proceeds to S313.

In step S313, the phase controller 805 outputs a control signal for adjusting the phase θ _k of the output signal of the k-th system by Δθ = Δθ _o + 90 ° to the phase shifter 801-k. The phase shifter 801-k adjusts the phase of the output signal of the k-th system based on the control signal, and outputs the signal after the phase adjustment of the k-th system having the phase θ _{k_ad} = θ _k + Δθ. Then, the flow ends.

As described above, the phase difference between the two signals can be adjusted by the phase control method shown in FIG. 14, for example, an output signal having the same phase can be output. In the phase control method shown in FIG. 14, the phase is adjusted in accordance with the comparison between V _dck output from the detector 803-k and the bias voltage V _sta , so that the circuit configuration can be simplified. it can.

  In the phase control method illustrated in FIGS. 12 to 14, an example in which two signals are adjusted to the same phase has been described, but the present disclosure is not limited thereto. Since the signal output from the detector 803 corresponds to the phase difference between the two signals, the phase relationship other than the in-phase can be adjusted.

  Note that the phase control method shown in FIGS. 12 to 14 is a method of adjusting the two output signals of the k-th system and the (k + 1) -th system in phase (that is, the phase difference is zero). When the power amplification / distribution circuit 411 shown in FIG. 11 outputs x-system output signals, the phases of all the x-system output signals can be adjusted to the same phase by sequentially adjusting the phases of the two output signals to the same phase. .

  At that time, by controlling the order in which the phases are adjusted, the phases of all the x system output signals can be adjusted to the same phase efficiently. Below, the control method of the order which adjusts a phase is demonstrated.

  FIG. 15 is a flowchart illustrating an example of a phase adjustment order control method according to the second embodiment.

In step S401, the phase controller 805 adjusts (in-phases) the two output signals of the x / 2 system and the x / 2 + 1 system to the same phase. Specifically, the phase controller 805 is based on the signal V _{dc (x / 2)} output from the detector 803-(x / 2), and the phase shifter 801-(x / 2) or the phase shifter 801 -1. By outputting the control signal to (x / 2 + 1), the two output signals of the x / 2 system and the x / 2 + 1 system are in-phased. When the in-phase of the two output signals of the x / 2 system and the x / 2 + 1 system is completed, the flow proceeds to S402 and S403. S402 and S403 are processes executed in parallel.

In step S402, the phase controller 805 adjusts (in-phases) the two output signals of the x / 2-1 system and the x / 2 system to the same phase. At this time, the phase controller 805 adjusts the phase of the output signal of the x / 2-first system with reference to the output signal of the x / 2 system that has been in-phased in S401. Specifically, the phase controller 805 is based on the signal V _{dc (x / 2-1)} output from the detector 803-(x / 2-1), and the phase shifter 801-(x / 2-1). ), The two output signals of the x / 2-first system and the x / 2 system are in-phase with the output signal of the x / 2 system as a reference.

In step S403, the phase controller 805 adjusts (in-phases) the two output signals of the x / 2 + 1 system and the x / 2 + 2 system to the same phase. The phase controller 805 adjusts the phase of the output signal of the x / 2 + 2 system based on the output signal of the x / 2 + 1 system for which the in-phase operation has been completed in S401. Specifically, the phase controller 805 outputs a control signal to the phase shifter 801- (x / 2 + 2) based on the signal V _{dc (x / 2 + 1)} output from the detector 803- (x / 2 + 1). Thus, the two output signals of the x / 2 + 1 system and the x / 2 + 2 system are in-phase with the output signal of the x / 2 + 1 system as a reference.

  The illustration of the processing flow after S402 and after S403 is omitted except for S404 and S405, but as with S402 and S403, the phase controller 805 is based on the output signal of the system that has completed in-phase, By adjusting the phase of the output signal of the system that is not in-phased, the output signal is in-phased in order. Then, the flow goes to S404 and S405.

In S404, phase controller 805 adjusts (in-phases) the two output signals of the first system and the second system to the same phase. At that time, the phase controller 805 adjusts the phase of the output signal of the first system on the basis of the output signal of the second system that has been in-phased in the process before S404 (not shown). . Specifically, the phase controller 805, based on a signal _{V dc1} output from the detector 803-1, by outputting a control signal to the phase shifter 801-1, based on the output signal of the second system Thus, the two output signals of the first system and the second system are made in phase.

In S405, the phase controller 805 adjusts (in-phases) the two output signals of the x-1 system and the x system to the same phase. The phase controller 805 adjusts the phase of the output signal of the x-th system on the basis of the output signal of the x-1 system that has been in-phased in the process (not shown) before S405. Specifically, the phase controller 805 outputs a control signal to the phase shifter 801-x based on the signal V _{dc (x-1)} output from the detector 803- (x-1). Based on the output signal of the x-1 system, the two output signals of the x-1 system and the x system are in-phased.

  When the processes of S404 and S405 are completed, the flow ends.

  The phase adjustment order control method shown in FIG. 15 will be described by taking as an example the case where the power amplification distribution circuit 411 outputs eight output signals (that is, when x = 8).

  First, the phase controller 805 performs in-phase between the output signals of the fourth system and the fifth system among the eight systems of output signals (S401). Next, the phase controller 805 performs in-phase operation of the output signals of the third system and the fourth system on the basis of the output signal of the fourth system that has been in-phased (S402). The fifth system and the sixth system output signals are in-phased with reference to the output signal of the fifth system that has been completed (S403). Next, the phase controller 805 makes the output signal of the second system and the third system in-phase with reference to the output signal of the third system that has completed in-phase (not shown), and the in-phase operation is completed. Based on the output signal of the sixth system, the output signals of the sixth system and the seventh system are made in phase (not shown). Then, the phase controller 805 performs the in-phase operation of the output signals of the first system and the second system on the basis of the output signal of the second system in which the in-phase is completed (S404), and the seventh in-phase is completed. Based on the output signal of the system, the output signals of the seventh system and the eighth system are made in-phase (S405).

  As described above, the phase adjustment order control method shown in FIG. 15 allows the output signals to be in-phased in parallel with reference to the two output signals that have been in-phased. Can be made in-phase.

  Note that the phase control order control method illustrated in FIG. 15 is an example in which all output signals are in-phase, but the present disclosure is not limited thereto. Since the signal output from the detector 803 corresponds to the phase difference of the signal of the system to which the detector 803 is connected, the phase relationship other than the in-phase can be adjusted.

  Further, the phase control order control method shown in FIG. 15 is a control method for the configuration of the power amplification distribution circuit 811 shown in FIG. 9, but for example, by changing the system to which the detector 803 is connected, Efficient control can be performed.

  A case where the power amplification / distribution circuit 411 outputs eight systems of output signals (that is, when x = 8) will be described as an example.

  First, the phase controller 805 performs in-phase between the output signals of the fourth system and the sixth system among the eight systems of output signals. Next, the phase controller 805 performs in-phase operation of the output signals of the second system and the fourth system on the basis of the output signal of the fourth system for which the in-phase operation has been completed, and the sixth system for which the in-phase operation has been completed. Based on the output signal, the output signals of the sixth system and the eighth system are made in-phase. Next, the phase controller 805 performs in-phase operation of the output signals of the first system and the second system on the basis of the output signal of the second system that has completed in-phase, and the fourth controller of the fourth system that has completed in-phase processing. Based on the output signal, the third system and the fourth system output signals are in-phased, and the phase controller 805 uses the sixth system output signal that has been in-phased as a reference, and the fifth system and the fourth system. Six systems of output signals are in-phased, and the output signals of the seventh system and the eighth system are in-phased with reference to the output signal of the eighth system that has been in-phased.

  As described above, the power amplification distribution circuit 811 according to the second embodiment controls the phase of the distribution signals of a plurality of systems with respect to the power amplification distribution circuit 411. With this configuration, the phase of multiple systems can be adjusted to an arbitrary phase, so a suitable output signal can be obtained by a system that performs signal processing of multiple systems such as beam forming and MIMO (Multiple-Input Multiple-Output). Can do.

  In the above-described second embodiment, the example in which the configuration for controlling the phase of the distribution signal is provided on the output side of the power amplification distribution circuit 411 shown in FIG. The phase of the distribution signal may be controlled.

  In the first and second embodiments described above, N is described as an integer of 2 or more in the N-shaped annular inductor, but the present invention is not limited to this. For example, if N is a number larger than 1, it is not limited to an integer. For example, N = 1.5 may be sufficient.

  For example, FIG. 16 is a plan view showing a configuration example of a transformer type balun 408 having a turns ratio of 1: 1.5. The number of turns of the balanced inductor 402b of the transformer type balun 402 shown in FIGS. 7A and 7B is 2 (N = 2), whereas the number of turns of the balanced side inductor 402b of the transformer type balun 408 shown in FIG. .5 (N = 1.5). Further, the wiring parts of the balanced-side inductor 402b are formed in the first layer and the second layer as in FIG. 7B. Since the wiring arrangement is the same as that in FIG. 7B, description thereof is omitted here.

  The center tap terminal T5 is installed at a position where the self-inductance of the balanced-side inductor 402b is 1: 0.5, but this is not a limitation.

  FIG. 16 illustrates an example in which the balanced inductor 402b is formed in the first layer and the second layer, but the present disclosure is not limited to this. For example, similarly to the balanced-side inductor 402b shown in FIGS. 8A and 8B, the balanced-side inductor 402b of FIG. 16 may be formed in the second layer and the third layer.

  While various embodiments have been described above with reference to the drawings, it goes without saying that the present disclosure is not limited to such examples. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present disclosure. Understood. In addition, the constituent elements in the above embodiments may be arbitrarily combined within the scope not departing from the spirit of the disclosure.

<Summary of this disclosure>
The power amplification distribution circuit according to the present disclosure outputs a first-phase annular inductor provided with a first terminal to which an input signal is input and a second terminal connected to a first power supply, and a positive phase signal. A third terminal, a fourth terminal for outputting a reverse phase signal, and a fifth terminal connected to the second power source are provided, and N windings (N is a number greater than 1) shaped along a part of the first inductor. ), A conversion element that converts the input signal into the positive phase signal and the negative phase signal, a source connected to a third power source, and the positive phase signal input to the gate. A first transistor; a second transistor whose source is connected to a fourth power supply; and the negative phase signal is input to a gate; and a second transistor connected between a gate of the first transistor and a drain of the second transistor. A first impedance circuit and the second A second impedance circuit connected between the gate of the transistor and the drain of the first transistor; and a first output terminal and a second output terminal connected to the drain of the first transistor and the drain of the second transistor. Output matching circuits for outputting the first distribution signal and the second distribution signal, respectively.

  In the power amplification distribution circuit according to the present disclosure, the output matching circuit performs impedance conversion between the output of the drain of the first transistor and the output of the drain of the second transistor, so that the impedance of the first terminal and the first The impedance of one output terminal is made equal to the impedance of the second output terminal.

  In the power amplification distribution circuit according to the present disclosure, each of the first impedance circuit and the second impedance circuit includes a capacitor.

  In the power amplification distribution circuit according to the present disclosure, each of the first impedance circuit and the second impedance circuit has a resistor connected in series to the capacitor.

  The power amplification distribution circuit according to the present disclosure is connected to the first output terminal, and is connected to the first phase shifter that outputs a first phase adjustment signal in which the phase of the first distribution signal is adjusted, and the first phase shifter. A first directional coupler for branching and outputting the first phase adjustment signal; and a second directional coupler connected to the second output terminal for outputting a second phase adjustment signal obtained by adjusting the phase of the second distribution signal. A phase shifter, a second directional coupler connected to the second phase shifter for branching and outputting the second phase adjustment signal, the first directional coupler, and the second directional coupler; Connected to a detector that outputs a signal indicating a phase difference between the first phase adjustment signal and the second phase adjustment signal; and connected to the detector, the first phase shifter, and the second phase shifter. , Based on the phase difference, the first phase shifter and Or further comprising: a phase controller, wherein the second phase shifter to control the phase adjustment amount to be adjusted.

  The power amplification distribution circuit of the present disclosure is connected to the first directional coupler, and is connected to the first termination element that terminates a part of the output of the first phase adjustment signal, and the second directional coupler. And a second termination element that terminates a part of the output of the second phase adjustment signal.

  A multistage power amplification distribution circuit according to the present disclosure is a multistage power amplification distribution circuit that connects a plurality of power amplification distribution circuits, and each of the plurality of power amplification circuits receives a first input signal. A one-turn annular first inductor provided with a terminal and a second terminal connected to the first power source, a third terminal that outputs a positive phase signal, a fourth terminal that outputs a negative phase signal, and a second power source A fifth terminal connected to the first inductor, and a second inductor having an N winding (N is a number greater than 1) having a shape along a part of the first inductor, the input signal being the positive phase A signal and a conversion element for converting to a negative phase signal; a source connected to a third power source; a first transistor having the positive phase signal input to a gate; a source connected to a fourth power source; A second transistor input to the gate, and the first transistor A first impedance circuit connected between the gate of the transistor and the drain of the second transistor; a second impedance circuit connected between the gate of the second transistor and the drain of the first transistor; An output matching circuit connected to the drain of the first transistor and the drain of the second transistor, and outputting a first distribution signal and a second distribution signal from the first output terminal and the second output terminal, respectively. The first output terminal of the power amplification distribution circuit is connected to the first terminal of the second power amplification distribution circuit, and the second output terminal of the first power amplification distribution circuit is the third power amplification. From X output terminals connected to the first terminal of the distribution circuit and not connected to the first terminals of the plurality of power amplification distribution circuits (X is an integer of 2 or more), And it outputs a delivery issue.

  The power amplification distribution circuit according to the present disclosure is connected to each of the X output terminals, and outputs X phase shift signals from a first phase adjustment signal obtained by adjusting the phase of the distribution signal of each system. X directional couplers connected to each of the X phase shifters and branching and outputting the X phase adjustment signal from the first phase adjustment signal, and an i th directional coupler (i is 1). And an i-th detector connected to the (i + 1) th directional coupler and outputting a signal indicating a phase difference between the i-th phase adjustment signal and the (i + 1) th phase adjustment signal, A phase controller connected to the detector, the i-th phase shifter, and the i + 1-th phase shifter, and controls a phase adjustment amount adjusted by the i-th phase shifter and / or the i + 1-th phase shifter based on the phase difference And further comprising.

  The power amplification distribution circuit according to the present disclosure is connected to the first directional coupler, and is connected to the first termination element that terminates a part of the output of the first phase adjustment signal, the Xth directional coupler, and the Xth directional coupler. And a second termination element that terminates a part of the output of the phase adjustment signal.

  In the power amplification / distribution circuit of the present disclosure, the phase controller includes the i-th phase shifter based on a signal indicating a phase difference output from the i-th detector (i is an integer not less than 2 and not more than X-2). And / or controlling the phase adjustment amount adjusted by the (i + 1) th phase shifter, determining the phase adjustment amount adjusted by the i-th phase shifter and / or the (i + 1) th phase shifter, and then outputting from the i-1 detector The phase adjustment amount adjusted by the i−1th phase shifter is controlled based on the signal indicating the phase difference to be adjusted, and the i + 2 phase shifter adjusts based on the signal indicating the phase difference output from the i + 1th detector. Control the amount of phase adjustment to be performed.

  The power amplification distribution circuit according to the present disclosure is useful for high-resolution radar and high-speed communication.

100, 401, 411, 811 Power amplification distribution circuit 101 Amplification circuit 102-1 to 102-n Wilkinson power distribution circuit 200 Differential amplification circuit 201, 202, 403, 404 Transistor 203, 204 Capacitor 300, 402, 408 Transformer type balun 301, 302, 304, 305, 306 Terminal 303, 402a Unbalanced inductor 307, 402b Balanced inductor 405, 406 Impedance circuit 407 Output matching circuit 801-1 to 801-x Phase shifter (φ)
802-1 to 802-x directional couplers
803-1 to 803- (x-1) detector (DET)
804-1 to 804-2 Termination 805 Phase Controller
901 Adder 902 Non-linear circuit (nonlinear)
1001 Multiplier 1002 Low-pass filter (LPF)

Claims (10)

A one-turn annular first inductor provided with a first terminal to which an input signal is input and a second terminal connected to the first power source, and a third terminal for outputting a positive phase signal and a negative phase signal are output. A fourth terminal and a fifth terminal connected to the second power source, and an N-shaped second inductor having an N winding shape (N is a number greater than 1) having a shape along a part of the first inductor. A conversion element for converting the input signal into the positive phase signal and the negative phase signal;
A first transistor having a source connected to a third power source and the positive-phase signal input to a gate;
A second transistor, the source of which is connected to a fourth power source and the negative phase signal is input to the gate;
A first impedance circuit connected between the gate of the first transistor and the drain of the second transistor;
A second impedance circuit connected between the gate of the second transistor and the drain of the first transistor;
An output matching circuit connected to the drain of the first transistor and the drain of the second transistor and outputting a first distribution signal and a second distribution signal from the first output terminal and the second output terminal, respectively;
A power amplification distribution circuit comprising: The output matching circuit performs impedance conversion between the output of the drain of the first transistor and the output of the drain of the second transistor, whereby the impedance of the first terminal, the impedance of the first output terminal, and the second output terminal. Make the impedance of the output terminal equal,
The power amplification distribution circuit according to claim 1. The first impedance circuit and the second impedance circuit each have a capacitor.
The power amplification distribution circuit according to claim 1. Each of the first impedance circuit and the second impedance circuit has a resistor connected in series to the capacitor.
The power amplification distribution circuit according to claim 3. A first phase shifter connected to the first output terminal and outputting a first phase adjustment signal obtained by adjusting a phase of the first distribution signal;
A first directional coupler connected to the first phase shifter for branching and outputting the first phase adjustment signal;
A second phase shifter connected to the second output terminal and outputting a second phase adjustment signal obtained by adjusting a phase of the second distribution signal;
A second directional coupler connected to the second phase shifter for branching and outputting the second phase adjustment signal;
A detector connected to the first directional coupler and the second directional coupler for outputting a signal indicating a phase difference between the first phase adjustment signal and the second phase adjustment signal;
A phase adjustment amount that is connected to the detector, the first phase shifter, and the second phase shifter and that is adjusted by the first phase shifter and / or the second phase shifter is controlled based on the phase difference. A phase controller;
A power amplification distribution circuit according to claim 1. A first termination element connected to the first directional coupler and terminating a part of the output of the first phase adjustment signal;
A second termination element connected to the second directional coupler and terminating a part of the output of the second phase adjustment signal;
The power amplification distribution circuit according to claim 5, further comprising: A multi-stage power amplification distribution circuit connecting a plurality of power amplification distribution circuits,
Each of the plurality of power amplifier circuits is
A one-turn annular first inductor provided with a first terminal to which an input signal is input and a second terminal connected to the first power source, and a third terminal for outputting a positive phase signal and a negative phase signal are output. A fourth terminal and a fifth terminal connected to the second power source, and an N-shaped second inductor having an N winding shape (N is a number greater than 1) having a shape along a part of the first inductor. A conversion element for converting the input signal into the positive phase signal and the negative phase signal;
A first transistor having a source connected to a third power source and the positive-phase signal input to a gate;
A second transistor, the source of which is connected to a fourth power source and the negative phase signal is input to the gate;
A first impedance circuit connected between the gate of the first transistor and the drain of the second transistor;
A second impedance circuit connected between the gate of the second transistor and the drain of the first transistor;
An output matching circuit connected to the drain of the first transistor and the drain of the second transistor and outputting a first distribution signal and a second distribution signal from the first output terminal and the second output terminal, respectively;
With
The first output terminal of the first power amplification distribution circuit is connected to the first terminal of the second power amplification distribution circuit;
The second output terminal of the first power amplification distribution circuit is connected to the first terminal of a third power amplification distribution circuit;
X distribution signals are output from X (X is an integer of 2 or more) output terminals not connected to the first terminals of the plurality of power amplification distribution circuits.
Multi-stage power amplification distribution circuit. X phase shifters connected to the X output terminals, respectively, for outputting the X-th phase adjustment signal from the first phase adjustment signal obtained by adjusting the phase of the distribution signal of each system,
X directional couplers connected to each of the X phase shifters and branching and outputting the Xth phase adjustment signal from the first phase adjustment signal;
Connected to the i-th directional coupler (i is an integer between 1 and X-1) and the i + 1-th directional coupler, and outputs a signal indicating the phase difference between the i-th phase adjustment signal and the i + 1-th phase adjustment signal. An i-th detector,
The i-th detector, i-th phase shifter, and i + 1-th phase shifter are connected to control the phase adjustment amount adjusted by the i-th phase shifter and / or the i + 1-th phase shifter based on the phase difference. A phase controller;
Comprising
The multistage power amplification distribution circuit according to claim 7. A first termination element connected to the first directional coupler and terminating a part of the output of the first phase adjustment signal;
A second termination element connected to the Xth directional coupler and terminating a part of the output of the Xth phase adjustment signal;
The multistage power amplification distribution circuit according to claim 8, further comprising: The phase controller is
A phase adjustment amount adjusted by the i-th phase shifter and / or the i + 1-th phase shifter based on a signal indicating a phase difference output from the i-th detector (i is an integer of 2 or more and X-2 or less). Control
After determining the phase adjustment amount to be adjusted by the i-th phase shifter and / or the i + 1-th phase shifter, the i-1th phase shifter is based on a signal indicating the phase difference output from the i-1 detector. Controlling the amount of phase adjustment to be adjusted, and controlling the amount of phase adjustment adjusted by the i + 2 phase shifter based on the signal indicating the phase difference output from the (i + 1) th detector;
The multistage power amplification distribution circuit according to claim 8.

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