JP2018155687A - Radio correction clock - Google Patents

Abstract

Provided is a technique capable of performing a second synchronization process even when a plurality of pulses are included in a signal per second of a standard radio wave. A radio-controlled timepiece includes a sampling unit that samples a time code output (TCO) signal, a detection unit that receives a TCO signal from the sampling unit, a counter that measures time, and a TCO signal from the first to the first. The detection unit is controlled to detect the first change that changes to the level of 2, and the counter is controlled to measure the elapsed time from the first change to determine whether the elapsed time exceeds the first time. And a control unit that controls the detection unit to detect a second change in which the TCO signal changes from the first to the second level after the elapsed time exceeds the first time, and a second change from the first change to the second change. A determination unit that determines whether or not the time until the change is within a predetermined allowable range so as to include one second, and a time data acquisition unit. [Selection] Figure 3

Description

  The present invention relates to a radio-controlled timepiece.

  A radio-controlled timepiece that corrects the internal time based on time data acquired by receiving a standard radio wave is known. In order to acquire time data from the standard radio wave, a second synchronization process, which is a synchronization process for a time code output (TCO) signal included in the standard radio wave, is performed. In the second synchronization process, a period of 1 second is acquired based on the TCO signal. The TCO signal includes one signal per second (hereinafter referred to as a signal per second), and constitutes one frame in 60 seconds (1 minute).

  In Patent Document 1, the time from the rise of a certain pulse in a TCO signal to the rise of a pulse adjacent to the pulse is counted, and a plurality of timing results obtained in this way are averaged for 1 second. A technique for acquiring the period is disclosed.

Japanese Patent No. 4882610

  By the way, as will be described in detail later, according to the study of the inventor of the present application, a plurality of signals are included in a signal per second, such as a signal indicating Bit A = 0 and Bit B = 1 of MSF which is a standard radio wave in the UK It was found that a period of 1 second could not be acquired by the method disclosed in Patent Document 1 in the case where the number of pulses is included.

  The present invention has been made in view of the above-described circumstances, and provides a technique capable of performing second synchronization processing even when a plurality of pulses are included in a standard radio wave signal per second. This is one of the resolution issues.

  In order to solve the above problems, an aspect of the radio-controlled timepiece according to the present invention includes a sampling unit that samples a time code output signal acquired from a standard radio wave, and the time code output signal sampled by the sampling unit. Controlling the detection unit to detect a first change in which the input detection unit, a time counter, and the time code output signal change from a first level to a second level; The counter is controlled so as to time the elapsed time elapsed from the first change, it is determined whether the elapsed time exceeds a predetermined first time, and the elapsed time is the first time. The detection unit is controlled so that the second change in which the time code output signal changes from the first level to the second level after the time is exceeded. A control unit that determines whether the time from the first change to the second change is within a predetermined allowable range including 1 second, and A time data acquisition unit that acquires time data based on the time code output signal based on the first change or the second change when the determination result is a time within the allowable range;

  According to the above aspect, the second change is detected after the first time is exceeded from the first change, the time from the first change to the second change is counted, and the allowable range including 1 second Even if a plurality of pulses are included in a signal per second like a signal indicating Bit A = 0 and Bit B = 1 of the MSF, for example, A period of seconds can be acquired, and a second synchronization process can be performed.

  In one aspect of the radio-controlled timepiece described above, the control unit includes the time code output signal from the first level to the second level, which is included before the first time elapses from the first change. The detection unit is controlled so as to detect a third change that changes to a level, and the determination unit determines a time within the allowable range with respect to a time from the first change to the third change. It is determined whether the time is within the allowable range with respect to the time from the first change to the second change. According to this aspect, the third change included in the first time is detected, but the time from the first change to the third change is within an allowable range including 1 second. Do not judge. In this way, it is possible to appropriately determine whether the time from the first change to the second change detected after exceeding the first time is within an allowable range including 1 second. Can do.

  In one aspect of the radio-controlled timepiece described above, the control unit includes the time code output signal from the first level to the second level, which is included before the first time elapses from the first change. The detection unit is controlled so as not to detect the third change that changes to the level. According to this aspect, the third change included in the first time does not detect a change. In this way, it is appropriately determined whether the time from the first change to the second change detected after exceeding the first time is within the allowable range including 1 second. be able to.

  In one aspect of the radio-controlled timepiece described above, the control unit stops sampling the time code output signal until the first time has elapsed from the first change, and the first change from the first change When the time of 1 elapses, the sampling unit is controlled to resume sampling of the time code output signal. According to this aspect, the third change included in the first time is not detected by stopping the sampling during the first time. In this way, it is appropriately determined whether the time from the first change to the second change detected after exceeding the first time is within the allowable range including 1 second. be able to. In addition, the power consumption required for sampling can be reduced compared to a mode in which sampling is always performed.

  In one aspect of the radio-controlled timepiece described above, the control unit is configured such that, in the time code output signal sampled by the sampling unit, the time that the first level continues or the time that the second level continues, It is determined whether it is a predetermined second time or more, and the detection unit is controlled to detect a change from the first level to the second level based on a result of the determination. According to this aspect, even in an environment where the electric field intensity of the standard radio wave is low, changes due to noise can be prevented from being detected by the detection unit, and the accuracy of detection of changes can be improved.

It is a block diagram which shows the structure of the radio wave correction timepiece which concerns on one Embodiment of this invention. It is a flowchart which shows a reception process. It is a flowchart which shows a second synchronization process. It is a flowchart which shows a rise confirmation process. It is a flowchart which shows the second synchronization process by 2nd Embodiment. It is a flowchart which shows the rising confirmation process by 2nd Embodiment. It is a flowchart which shows the second synchronization process by 3rd Embodiment. It is the table | surface which put together the kind of signal for every second in the time code output signal of MSF. It is a timing chart which shows the condition where the signal of Bit B = 0 of MSF and Bit B = 1 are continuing. It is a timing chart which shows the situation where the signal which has a pulse width of 800 ms of WWVB, and the signal which has a pulse width of 200 ms are continuing.

  Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. However, in each figure, the size and scale of each part are appropriately changed from the actual ones. Further, since the embodiments described below are preferable specific examples of the present invention, various technically preferable limitations are attached thereto. However, the scope of the present invention is particularly limited in the following description. Unless otherwise stated, the present invention is not limited to these forms.

<First Embodiment>
[Schematic configuration of radio-controlled clock]
FIG. 1 is a block diagram showing the configuration of a radio-controlled timepiece 1 according to an embodiment of the present invention. The radio-controlled timepiece 1 receives a long-wave standard radio wave (hereinafter abbreviated as “standard radio wave”), acquires time data included in the standard radio wave, and determines the internal time being measured based on the acquired time data. Correct it.

  The radio-controlled timepiece 1 includes a receiving unit 2, a processing unit 3, a storage unit 4, an oscillation circuit 5, a frequency dividing circuit 6, a display unit 7, and an operation unit 8. The receiving unit 2 includes an antenna 2a and a receiving circuit 2b. The antenna 2a receives the standard radio wave and outputs a reception signal corresponding to the received standard radio wave to the reception circuit 2b. The receiving circuit 2b causes the antenna 2a to receive a radio wave of a specific frequency, and demodulates a binarized TCO (Time Code Out) signal based on the received signal input from the antenna 2a. The TCO signal is output to the processing unit 3.

  The reception circuit 2b includes, for example, a tuning circuit, a first amplification circuit, a local oscillation signal generation unit, a frequency conversion unit, a BPF (Band-pass filter), a second amplification circuit, a detection circuit, a binarization circuit, and a decoding circuit. . The decoding circuit decodes the control signal input from the processing unit 3, and outputs the control content indicated by the control signal to these functional units included in the receiving circuit 2b.

  The processing unit 3 performs various processes for controlling the operation of the radio-controlled timepiece 1. The storage unit 4 stores various data and programs necessary for the control of the radio-controlled timepiece 1 by the processing unit 3. The processing unit 3 controls the operation of the receiving circuit 2b by outputting a control signal to the receiving circuit 2b. As will be described in detail later, the processing unit 3 performs second synchronization processing on the TCO signal input from the receiving circuit 2b, decodes the TCO signal, generates a TC (Time Code), and is included in the TC. Get time data. The processing unit 3 also corrects the internal time based on the time data acquired from the standard radio wave, and causes the display unit 7 to display the internal time. Hereinafter, the time data acquired from the standard radio wave may be referred to as reception time data in order to distinguish it from the internal time.

  The TCO signal is a signal that includes one signal every second and forms one frame in 60 seconds (1 minute). Hereinafter, in order to distinguish a signal included every second from a TCO signal of one frame, it may be referred to as a signal per second. One frame includes data of items such as year, month, day, hour, and the like, and the data of a certain item is indicated by the signal value per second of the period allocated to the item in one frame. A marker indicating the start of one frame is assigned to the first second of one frame. The allocation method of the data of each item in one frame differs depending on the standard radio wave of each country. In the second synchronization process, the start timing of the signal per second in the TCO signal is acquired, and the period of 1 second in the TCO signal is acquired.

  The oscillation circuit 5 has a crystal resonator and outputs a reference signal having a predetermined reference clock frequency (for example, 32.768 kHz) oscillated by the crystal resonator. The reference signal output from the oscillating circuit 5 is input to the frequency dividing circuit 6 and is divided by the frequency dividing circuit 6 into a 1 Hz signal.

  The display unit 7 displays the internal time counted by the processing unit 3. As a configuration of the display unit 7, for example, a liquid crystal panel can be adopted, and for example, a configuration including a dial plate and a pointer, a step motor and a gear for rotating the pointer can be adopted.

  The operation unit 8 is configured by a crown, a button, or the like that outputs an operation signal according to an operation by the user to the processing unit 3 and is exposed to the outside of the radio wave correction watch 1. The operation unit 8 is used for an operation or the like in which the user selects the type of standard radio wave received by the antenna 2a (Japanese standard radio wave JJY, US standard radio wave WWVB, UK standard radio wave MSF, etc.)

[Configuration of processing section]
The processing unit 3 is configured using a microcontroller (microcomputer), and includes a sampling unit 31, a transition detection unit 32, a second determination unit 33, a counter 34, a time data acquisition unit 35, a time measurement unit 36, and a control unit 37. The receiving process described later is performed using these units. Note that the processing unit 3 may include other functional blocks as necessary.

  The sampling unit 31 samples the TCO signal input from the receiving circuit 2b, and outputs a high (H) level or a low (L) level to the transition detection unit 32 as the signal level of the TCO signal.

  The transition detection unit 32 (detection unit) receives the TCO signal from the sampling unit 31, and detects a transition (change) from the first level to the second level of the TCO signal. The transition detection unit 32 detects, for example, a transition (change, rise) from the L level to the H level, and detects, for example, a transition (change, fall) from the H level to the L level. In the present embodiment, a case where the transition detection unit 32 detects the rising edge of the TCO signal is illustrated.

  The second determination unit 33 determines whether a 1-second period of the TCO signal is acquired in the second synchronization processing. The counter 34 measures the time used for the second synchronization process.

  The time data acquisition unit 35 decodes the TCO signal input from the reception circuit 2b, extracts TC from the TCO signal, and acquires reception time data. The time data acquisition unit 35 can decode TCs of a plurality of types of standard radio waves such as JJY, WWVB, and MSF.

  The timer 36 updates the internal time based on the 1 Hz signal generated by the frequency divider 6 and measures the current date and time. The timer 36 also corrects the internal time based on the reception time data acquired by the time data acquisition unit 35. The timer 36 also controls the drive of the display unit 7 to display the internal time on the display unit 7.

  The control unit 37 is configured by using a CPU (Central Processing Unit), and the CPU executes the control program stored in the storage unit 4 so as to control the radio-controlled timepiece 1 in a reception process described later. It functions as the control unit 37. The control unit 37 is driven based on the reference signal input from the oscillation circuit 5.

[Receive processing]
Hereinafter, with reference to FIG. 2 to FIG. 4, FIG. 8, and FIG. FIG. 2 is a flowchart showing the reception process. In step S1, the control unit 37 performs a reception start process. In the reception start process, a process of turning on the power of the reception circuit 2b is performed.

  Next, in step S2, second synchronization processing is performed. FIG. 3 is a flowchart showing the second synchronization processing. In step S10 of the second synchronization process, the control unit 37 determines whether a predetermined time (10 minutes in this example) has elapsed from the reception start timing. When 10 minutes have elapsed, in step S23b, the control unit 37 sets a “second synchronization failure” flag. When step S23b is performed, the second synchronization process ends.

  If 10 minutes has not elapsed, in step S11, the control unit 37 determines whether or not the signal width is equal to or longer than a predetermined time (in this example, 10 ms, the second time). The signal width is the time for which the H level continues or the time for which the L level continues in the TCO signal sampled by the sampling unit 31. As the predetermined time used for determining the signal width, a time shorter than the shortest pulse width of the pulse included in the TCO signal (in this example, 100 ms as described later with reference to FIG. 8) is set.

  If the signal width is less than 10 ms, step S10 is performed again. When the signal width is 10 ms or more, the control unit 37 controls the sampling unit 31 to input the sampled TCO signal to the transition detection unit 32. In step S <b> 12, the control unit 37 controls the transition detection unit 32 to perform the rising confirmation process.

  When the signal width is extremely short (in this example, less than 10 ms), it is considered that an H level signal caused by noise is mixed with a signal that is originally continuous in L level. Alternatively, it is considered that an L level signal caused by noise is mixed with a signal that is originally continuous at an H level. When the H level or the L level is mixed in this way, a portion where the L level and the H level are adjacent to each other, which does not exist in the original signal, occurs, and the rising occurs. is not. By performing the process of step S11, it is possible to prevent the rise (change, transition) caused by noise from being detected by the transition detection unit 32 (detection unit) even in an environment where the electric field intensity of the standard radio wave is low. ), The accuracy of detection is improved.

  FIG. 4 is a flowchart showing the rising confirmation process. In step S30 of the rising confirmation process, the transition detection unit 32 determines whether the signal level is the L level. When the signal level is the L level, the transition detection unit 32 sets an “L signal ON” flag in step S31, and sets a “rising OFF” flag in step S32. When step S32 is performed, the rising confirmation process ends.

  When the signal level is not L level (H level), the transition detection unit 32 determines whether or not the “L signal ON” flag is set in step S33. When the “L signal ON” flag is set, the transition detecting unit 32 sets the “L signal OFF” flag in step S34, and in step S35, sets the “rising ON” flag. When step S35 is performed, the rising confirmation process ends. When the “L signal ON” flag is not set, step S34 and step S35 are skipped, and the rising confirmation process ends.

  As described above, when the signal level is L level, the “L signal ON” flag is set. After that, when the “L signal ON” flag is set and the signal level becomes H level, “rise ON” ”Flag is set and a rising edge is detected.

  When the rising confirmation process ends, step S13 is performed in the second synchronization process shown in FIG. In step S <b> 13, the control unit 37 determines whether or not the “rising ON” flag is set. If the “rise ON” flag is not set, the process returns to step S10, and the rise confirmation process is performed again in step S12 through steps S10 and S11.

  If the “rise ON” flag is set, in step S14, the control unit 37 determines whether the “rise acquisition completed ON” flag is set. When the “rising acquisition completed ON” flag is not set, in step S15, the control unit 37 sets the “rising acquisition acquired ON” flag. Moreover, in step S15, the control part 37 controls the counter 34, sets a period counter to 0, and starts time-measurement. After step S15, the process returns to step S10, and through steps S10 and S11, the rising confirmation process is performed again in step S12.

  If the “startup acquired ON” flag is set, step S16 is performed. The “rising acquired ON” flag is a flag indicating that the first rising is detected after the second synchronization processing is started.

  In step S16, the control unit 37 determines whether or not the period counter exceeds a predetermined standby time (in this example, 500 ms, the first time). If the cycle counter does not exceed 500 ms, the process returns to step S10, and the rising confirmation process is performed again in step S12 through steps S10 and S11.

  When the cycle counter exceeds 500 ms, in step S17, the second determination unit 33 determines whether the time counted by the cycle counter is 1000 ms (1 second) ± time within a tolerance range (including 1 second). It is determined whether or not the time is within a predetermined allowable range. The tolerance is, for example, 60 ms.

  If the time counted by the period counter is not 1000 ms ± the time within the tolerance range, the control unit 37 sets the number of consecutive acquisitions of one second period to 0 in step S19b. When the time measured by the cycle counter is within the range of 1000 ms ± tolerance, the control unit 37 stores the time measurement result by the cycle counter in the storage unit 4 and stores it in step S18, and in step S19a, 1 Add the number of consecutive acquisitions per second.

  If step S19a or step S19b is performed, in step S20, the control part 37 will control the counter 34, will set a period counter to 0, and will start time-measurement again.

  Next, in step S <b> 21, the control unit 37 determines whether or not the number of consecutive acquisitions of 1 second period is equal to a preset threshold value (10 in this example) (whether or not the threshold value is reached). When the number of consecutive acquisitions of 1 second period has not reached 10, the process returns to step S10, and the rising confirmation process is performed again in step S12 through steps S10 and S11.

  When the number of consecutive acquisitions per second reaches 10, the control unit 37 calculates the average value of the timing results stored in step S18 in step S22, and sets the “second synchronization success” flag in step S23a. . When step S23a is performed, the second synchronization process ends.

  When the second synchronization process ends, in step S3 shown in FIG. 2, the control unit 37 succeeds in the second synchronization process based on the “second synchronization success” flag or the “second synchronization failure” flag set in the second synchronization process. Determine whether or not. When the second synchronization process fails, the control unit 37 sets a “reception failure” flag in step S8b. When the second synchronization process is successful, in step S4, the time data acquisition unit 35 acquires a marker of the TCO signal.

  Next, in step S5, the control unit 37 determines whether or not a predetermined time has elapsed from the reception start timing. The predetermined time is, for example, 15 minutes. When the predetermined time has elapsed, in step S8b, the control unit 37 sets a “reception failure” flag. When step S8b is performed, the reception process ends.

  If the predetermined time has not elapsed, in step S6, the time data acquisition unit 35 acquires reception time data. Next, in step S7, the time data acquisition unit 35 determines whether or not the reception time data is consistent. If the reception time data is not consistent, the process returns to step S5 to determine whether a predetermined time has elapsed. If the reception time data is consistent, in step S8a, the control unit 37 sets a “reception successful” flag. When step S8a is performed, the reception process ends.

  The consistency of the reception time data is determined, for example, by the fact that the parity of the TC corresponding to the acquired reception time data matches, or the values that can be taken from “minute”, “hour”, and “year / month / day”. Is done. The consistency of the reception time data is also determined, for example, by appropriate intervals between the acquired reception time data of a plurality of frames.

  Next, the second synchronization processing will be described more specifically by taking as an example the case of receiving an MSF which is a British standard radio wave. First, an MSF TCO signal will be described with reference to FIG. FIG. 8 is a table summarizing signal types per second in the MSF TCO signal. The signal per second in the MSF TCO signal is a 2-bit signal including Bit A and Bit B, excluding the marker. The signal of Bit A = 0 and Bit B = 0 transitions from the L level to the H level (changes and rises) at the start timing of the signal, the H level continues for 100 ms, and transitions from the H level to the L level ( It is a signal that changes and falls) and then continues at the L level.

  The signal of Bit A = 0 and Bit B = 1 rises at the start timing of the signal, H level continues for 100 ms, falls, L level continues for 100 ms, rises again, H level continues for 100 ms, and rises again It is a signal that goes down and then continues at the L level.

  A signal of Bit A = 1 and Bit B = 0 is a signal that rises at the start timing of the signal, continues for H ms for 200 ms, falls, and then continues for L level. A signal with Bit A = 1 and Bit B = 1 is a signal that rises at the start timing of the signal, H level continues for 300 ms, falls, and then the L level continues. The marker signal rises at the start timing of the signal, and is a signal in which the H level continues for 500 ms, falls, and thereafter the L level continues.

  As described above, any signal per second in the TCO signal of the MSF is a signal having a rise at the start timing. Of these, Bit A = 0 and Bit B = 0 signal, Bit A = 1 and Bit B = 0 signal, Bit A = 1 and Bit B = 1 signal, and Marker signal are each in seconds. The signal has only one rising edge and only one pulse. On the other hand, the signal of Bit A = 0 and Bit B = 1 has two (plural) rising edges in the signal per second and has two (plural) pulses.

  The second synchronization processing will be described by taking as an example a case where the signal of Bit A = 0 and Bit B = 1 is continuous. FIG. 9 is a timing chart showing a situation in which Bit A = 0 and Bit B = 1 are continuous. FIG. 9 shows continuous signals sig1 to sig3 every second.

  In this example, the rising confirmation process in step S12 of the second synchronization process is started from timing t0 shown in FIG. Timing t0 is a timing included in a period in which the signal level is L level between the first pulse p11 and the second pulse p12 of the signal sig1.

  Since the signal level at the timing t0 is the L level, the determination result in step S30 of the rising confirmation process is “YES”, the “ON in L signal” flag is set in step S31, and the “rising OFF” flag is set in step S32. Is set. Since the “rise ON” flag is not set, the determination result in step S13 of the second synchronization process is “NO”, and the rise confirmation process in step S12 is performed again. During the period until the pulse p12 rises, the signal level is the L level, and such processing is repeated.

  In order to avoid complicated description, the determination result in step S10 of the second synchronization process is “NO” (10 minutes have not elapsed), and the determination result in step S11 is “YES” (the signal width is 10 ms or more).

  At the timing t1 when the pulse p12 rises, the signal level changes to the H level. Since the signal level has become H level, the determination result in step S30 of the rising confirmation process is “NO”. Since the “L signal ON” flag is set, the determination result is “YES” in step S33, the “L signal OFF” flag is set in step S34, and the “rising ON” flag is set in step S35. Is set. In this way, the “rising ON” flag is set, and the rising is detected.

  Since the “rising ON” flag is set, the determination result in step S13 of the second synchronization process is “YES”. Since the “rising acquisition completed ON” flag is not set, the determination result in step S14 is “NO”. In step S15, the “rising acquisition completed ON” flag is set, the cycle counter is set to 0, and the time is counted. Be started. Thereafter, the rising confirmation process in step S12 is performed again.

  During the period of the pulse p12, the signal level is H level, and the determination result in step S30 of the rising confirmation process is “NO”. Since the “L signal ON” flag is not set, the determination result is “NO” in step S33, and the processes in steps S34 and S35 are skipped.

  Since the “rising ON” flag is set, the determination result in step S13 of the second synchronization process is “YES”. Furthermore, since the “rising acquired ON” flag is set, the determination result in step S14 is also set. “YES”.

  Since the value of the cycle counter does not exceed 500 ms during the period of the pulse p12, the determination result in step S16 is “NO”, and the rising confirmation process in step S12 is performed again. During the period of the pulse p12, the signal level is H level, and such processing is repeated.

  At the timing t2 when the pulse p12 falls, the signal level changes to the L level. Since the signal level is L level during the period until the first pulse p21 of the signal sig2 rises, the determination result in step S13 is “NO”, and the rising confirmation process in step S12 is repeated.

  At the timing t3 when the pulse p21 rises, the signal level changes to the H level. Similarly to the rising edge of the pulse p12, the “rising ON” flag is set in the rising confirmation process, and the rising edge is detected. Then, the determination result in step S13 is “YES”, and the determination result in step S14 is also “YES”.

  At the timing t3 when the pulse p21 rises, since the value of the cycle counter exceeds 500 ms, the determination result in step S16 is “YES”. In step S17, the time counted by the period counter from the rise of the second pulse p12 of the signal sig1 (from timing t1) to the rise of the first pulse p21 of the signal sig2 (until timing t3). Is a time within the range of 1000 ms ± tolerance.

  Since the time from timing t1 to timing t3 is 800 ms, the determination result in step S17 is “NO”. Therefore, in step S19b, the number of consecutive acquisitions of 1 second period is set to 0. In step S20, the cycle counter is set to 0 and the time measurement is started again. Since the number of 1-second continuous acquisitions is 0, the determination result in step S21 is “NO”, the process returns to step S12 again, and the rising confirmation process is performed.

  Since the signal level is H level during the period of the pulse p21, the determination result in step S13 is “YES” and the determination result in step S14 is “YES” in the same manner as the period of the pulse p12. Since the value of the cycle counter does not exceed 500 ms, the determination result in step S16 is “NO”, and the rising confirmation process in step S12 is repeated.

  At the timing t4 when the pulse p21 falls, the signal level changes to the L level. Thereafter, since the signal level is L level during the period until the second pulse p22 of the signal sig2 rises, the determination result in step S13 is “NO”, and the rising confirmation process in step S12 is repeated.

  At the timing t5 when the pulse p22 rises, the signal level changes to the H level. Similarly to the rising edge of the pulse p12, the “rising ON” flag is set in the rising confirmation process, and the rising edge is detected. Thereafter, since the signal level is H level during the period until the pulse p22 falls, the determination result in step S13 is “YES” and the determination result in step S14 is “YES” in the same manner as the period of the pulse 21. " Since the value of the cycle counter does not exceed 500 ms, the determination result in step S16 is “NO”, and the rising confirmation process in step S12 is repeated.

  Thus, although the rising edge of the pulse p22 is detected, since the value of the period counter does not exceed 500 ms, the determination result of step S16 is “NO”, and step S17 is not performed. Therefore, it is not determined whether the time from the rise of the pulse p12 (from timing t3) to the rise of the pulse p22 (until timing t5) is within a range of 1000 ms ± tolerance.

  At the timing t6 when the pulse p22 falls, the signal level transitions to the L level. Thereafter, since the signal level is L level during the period until the first pulse p31 of the signal sig3 rises, the determination result in step S13 is “NO”, and the rising confirmation process in step S12 is repeated.

  At the timing t7 when the pulse p31 rises, the signal level changes to the H level. Similarly to the rising edge of the pulse p12, the “rising ON” flag is set in the rising confirmation process, and the rising edge is detected.

  At the timing t7 when the pulse p31 rises, since the value of the cycle counter exceeds 500 ms, the determination result in step S16 is “YES”. In step S17, the time counted from the rising edge of the first pulse p21 of the signal sig2 (from timing t3) to the rising edge of the first pulse p31 of the signal sig3 (until timing t7) is counted by the period counter. Is a time within the range of 1000 ms ± tolerance.

  Since the time from timing t3 to timing t7 is 1000 ms, the determination result in step S17 is “YES”. Therefore, in step S18, the time measured by the cycle counter is stored, and in step S19a, the number of consecutive acquisitions of 1 second cycle is set to 1 by adding 1 to 0. In step S20, the cycle counter is set to 0 and the time measurement is started again. Since the number of 1-second continuous acquisitions is 1, the determination result in step S21 is “NO”, the process returns to step S12 again, and the rising confirmation process is performed.

  Thereafter, 1000 ms, which is the time from the rise of the first pulse of the signal per second to the rise of the first pulse of the signal per second immediately after the signal per second, is continuously acquired. Therefore, the number of consecutive acquisitions of 1 second period is sequentially added.

  When the number of 1-second continuous acquisitions reaches 10, the determination result in step S21 is “YES”, and in step S22, the average value of the 10 stored timing results is calculated. When the average value of the timing results is calculated in step S22, the “second synchronization success” flag is set in step S23a, and the second synchronization processing ends.

  The rise timing and pulse width of the pulse in the received TCO signal include an error from the original due to the influence of noise. For this reason, by acquiring a plurality (10 in this example) of time measurement results allowed as 1 second and calculating the average value thereof, the influence of noise is suppressed and a period of 1 second is acquired. be able to. In addition, from the viewpoint that it is possible to acquire a 1-second period (1-second interval) with respect to the following comparison form, one time measurement result may be used.

  Here, the following comparative forms are considered. The comparative form is an aspect in which a period of 1 second is acquired by measuring the time from the rise of the pulse in the TCO signal to the rise immediately after the rise. In the comparative form, first, a rising edge is detected at timing t1. Then, the next rising edge is detected at timing t3, and the time from timing t1 to timing t3 is measured. Since the time from timing t1 to timing t3 is 800 ms, a period of 1 second cannot be acquired.

  Thereafter, the next rising edge is detected at timing t5, and the time from timing t3 to timing t5 is measured. The time from timing t3 to timing t5 is 200 ms, and a period of 1 second cannot be acquired. Thereafter, the next rising edge is detected at timing t7, and the time from timing t5 to timing t7 is measured. The time from timing t5 to timing t7 is again 800 ms. As described above, in the comparative mode, the time measurement of 800 ms and the time measurement of 200 ms are repeated, and a period of 1 second cannot be acquired.

  On the other hand, in the present embodiment, it is determined whether the elapsed time from the rise exceeds a predetermined standby time (500 ms in this example), and the time until the rise detected after the elapsed time exceeds the standby time is counted. doing. In this way, the timing from the timing t3, which is the start timing of the signal per second, to the timing t7, which is the start timing of the signal per second immediately after the signal per second, can be measured, and a period of 1 second is obtained. Can be acquired.

  The waiting time is set to a time of less than 1 second. The waiting time is set to a length such that no rising edge exists in the signal per second after the waiting time has elapsed since the rising edge at the start timing of the signal per second.

  As described above, after the standby time (first time) is exceeded from the first detected rising edge (first change or transition), the next rising edge (second change or transition) is detected. By measuring the time from the detected rising edge to the next rising edge and determining whether the time is within an allowable range including 1 second, for example, the signal indicating Bit A = 0 and Bit B = 1 of the MSF Thus, even when a plurality of pulses are included in a signal per second, a period of 1 second can be acquired and a second synchronization process can be performed. If the determination result whether the time is within the allowable range including 1 second is affirmative (when the time is within the allowable range), the first detected rising edge (first change or transition) or the The time data acquisition unit 35 acquires time data based on the TCO signal based on the next rising edge (second change or transition).

  In contrast to the second and third embodiments described later, the first embodiment detects other rising edges (third change, transition) included in the standby time (first time). It is not determined whether the time from the rising edge (first change or transition) detected in step 1 to the other rising edge (third change or transition) is within an allowable range including 1 second (see step S16). ). In the first embodiment, in this way, the next rising edge (second change, which is detected after the standby time (first time) is exceeded after the first rising edge (first change, transition) is detected. It is possible to appropriately determine whether the time until (transition) is within an allowable range including one second.

Second Embodiment
Next, the radio-controlled timepiece 1 according to the second embodiment will be described. The second embodiment differs from the first embodiment in the second synchronization processing and the rising confirmation processing. FIG. 5 is a flowchart showing the second synchronization processing according to the second embodiment, and FIG. 6 is a flowchart showing the rising confirmation processing according to the second embodiment.

  In the flowchart of the second synchronization process according to the second embodiment, step S24 is performed instead of step S16 in the flowchart of the second synchronization process according to the first embodiment, the determination result of step S21 is “NO”, and the process returns to step S10. In the middle, step S25 is added. In the flowchart of the rising confirmation process according to the second embodiment, the process in the case where the determination result in step S30 is “YES” is different from the flowchart of the rising confirmation process according to the first embodiment.

  From the start of the reception process to the step S11 in the second synchronization process of step S2 through the reception process of step S1, the same process as in the first embodiment is performed. In step S30 in the rising confirmation process in step S12, the transition detection unit 32 determines whether the signal level is the L level. When the signal level is the L level, in step S36, the transition detection unit 32 determines whether or not the “rising acquisition completed ON” flag is set.

  If the “rising acquisition completed ON” flag is not set, the control unit 37 sets an “L signal ON” flag in step S31, and sets a “rising OFF” flag in step S32. When step S32 is performed, the rising confirmation process ends.

  When the “rising acquisition completed ON” flag is set, in step S37, the control unit 37 determines whether or not the cycle counter exceeds 500 ms (the above-described standby time). If the period counter does not exceed 500 ms, step S31 is skipped and the “rising signal ON” flag is not set, but the “rising OFF” flag is set in step S32. When step S32 is performed, the rising confirmation process ends.

  When the period counter exceeds 500 ms, in step S38, the control unit 37 sets an “L acquisition ON” flag. In step S31, an “L signal ON” flag is set, and in step S32, a “rising OFF” flag is set. When step S32 is performed, the rising confirmation process ends. The processing when the signal level is not L level (H level) in step S30 is performed in the same manner as in the first embodiment.

  When the rising confirmation process is completed, steps S13 to S15 are performed in the second synchronization process in the same manner as in the first embodiment. If the “start-up acquired ON” flag is set in step S14, step S24 is performed.

  In step S24, the control unit 37 determines whether or not the “L acquisition ON” flag is set. If the “L acquisition ON” flag is not set, the process returns to step S10, and the rising confirmation process is performed again in step S12 through steps S10 and S11. If the “L acquisition ON” flag is set, it is determined in step S17 whether or not the time counted by the period counter is within a range of 1000 ms (1 second) ± tolerance.

  Step S18, step S19a, step S19b, step S20 and step S21 are performed in the same manner as in the first embodiment. If the number of consecutive acquisitions per 1 second period does not reach 10 in step S21, step S25 is performed. In step S25, the control unit 37 sets an “L acquisition OFF” flag. When step S25 is performed, the process returns to step S10, and after step S10 and step S11, the rising confirmation process is performed again in step S12.

  Step S22, step S23a, and step S23b are performed in the same manner as in the first embodiment, and when step S23a or step S23b is performed, the second synchronization processing ends. The processes after step S3 in the reception process are performed in the same manner as in the first embodiment. In this way, the reception process in the second embodiment is performed.

  Next, referring again to FIG. 9, the second synchronization processing according to the second embodiment will be described more specifically. As in the first embodiment, a case where the rising confirmation process in step S12 is started from timing t0 is illustrated.

  Since the signal level at the timing t0 is the L level, the determination result in step S30 of the rising confirmation process is “YES”, and the determination result in step S36 is “NO” because the “rise acquired already” flag is not set. " In step S31, an “L signal ON” flag is set, and in step S32, a “rising OFF” flag is set. Since the “rise ON” flag is not set, the determination result in step S13 of the second synchronization process is “NO”, and the rise confirmation process in step S12 is performed again. During the period until the pulse p12 rises, the signal level is the L level, and such processing is repeated.

  At the timing t1 when the pulse p12 rises, the signal level changes to the H level. Since the signal level has become H level, the determination result in step S30 of the rising confirmation process is “NO”. Since the “L signal ON” flag is set, the determination result is “YES” in step S33, the “L signal OFF” flag is set in step S34, and the “rising ON” flag is set in step S35. Is set. In this way, the “rising ON” flag is set, and the rising is detected.

  Since the “rising ON” flag is set, the determination result in step S13 of the second synchronization process is “YES”. Since the “rising acquisition completed ON” flag is not set, the determination result in step S14 is “NO”. In step S15, the “rising acquisition completed ON” flag is set, the cycle counter is set to 0, and the time is counted. Be started. Thereafter, the rising confirmation process in step S12 is performed again.

  During the period of the pulse p12, the signal level is H level, and the determination result in step S30 of the rising confirmation process is “NO”. Since the “L signal ON” flag is not set, the determination result is “NO” in step S33, and the processes in steps S34 and S35 are skipped.

  Since the “rising ON” flag is set, the determination result in step S13 of the second synchronization process is “YES”. Furthermore, since the “rising acquired ON” flag is set, the determination result in step S14 is also set. “YES”.

  Since the “L acquisition ON” flag is not set during the period of the pulse p12, the determination result in step S24 is “NO”, and the rising confirmation process in step S12 is performed again. During the period of the pulse p12, the signal level is H level, and such processing is repeated.

  At the timing t2 when the pulse p12 falls, the signal level changes to the L level. At the timing t2, since the “rising acquisition completed ON” flag is set, the determination result in step S36 is “YES”, and since the value of the cycle counter does not exceed 500 ms, the determination result in step S37 is “NO”. In step S32, the “rise OFF” flag is set.

  Since the signal level is L level during the period until the first pulse p21 of the signal sig2 rises, the determination result in step S13 is “NO”, and the rising confirmation process in step S12 is repeated.

  In the middle of the period until the pulse p21 rises, the value of the period counter exceeds 500 ms. After the value of the cycle counter exceeds 500 ms, the determination result in step S37 is “YES”, the “L acquisition ON” flag is set in step S38, and the “L signal ON” flag is set in step S31. In step S32, the “rise OFF” flag is set.

  At the timing t3 when the pulse p21 rises, the signal level changes to the H level. Similarly to the rising edge of the pulse p12, the “rising ON” flag is set in the rising confirmation process, and the rising edge is detected. Then, the determination result in step S13 is “YES”, and the determination result in step S14 is also “YES”.

  At the timing t3 when the pulse p21 rises, since the “L acquisition ON” flag is set, the determination result in step S24 is “YES”. In step S17, the time counted by the period counter from the rise of the second pulse p12 of the signal sig1 (from timing t1) to the rise of the first pulse p21 of the signal sig2 (until timing t3). Is a time within the range of 1000 ms ± tolerance.

  Since the time from timing t1 to timing t3 is 800 ms, the determination result in step S17 is “NO”. Therefore, in step S19b, the number of consecutive acquisitions of 1 second period is set to 0. In step S20, the cycle counter is set to 0 and the time measurement is started again. Since the 1-second period continuous acquisition number is 0, the determination result in step S21 is “NO”. Then, the “L acquisition OFF” flag is set in step S25, the process returns to step S12 again, and the rising confirmation process is performed.

  Since the signal level is H level during the period of the pulse p21, the determination result in step S13 is “YES” and the determination result in step S14 is “YES” in the same manner as the period of the pulse p12. Since the “L acquisition ON” flag is not set, the determination result in step S24 is “NO”, and the rising confirmation process in step S12 is repeated.

  At the timing t4 when the pulse p21 falls, the signal level changes to the L level. At timing t4, since the “rising acquisition completed ON” flag is set, the determination result in step S36 is “YES”, and since the value of the cycle counter does not exceed 500 ms, the determination result in step S37 is “NO”. " Accordingly, the “L acquisition ON” flag is not set in step S38, the “L signal ON” flag is not set in step S31, and the “rising OFF” flag is set in step S32.

  Thereafter, since the signal level is at the L level until the second pulse p22 of the signal sig2 rises, the determination result at step S13 indicates that the determination result at step S13 is “L” until the pulse p12 rises. "NO", the rising confirmation process in step S12 is repeated.

  At the timing t5 when the pulse p22 rises, the signal level changes to the H level. The determination result in step S30 is “NO”, but the “L signal ON” flag is not set. Therefore, the “L signal OFF” flag is not set in step S34, the “rise ON” flag is not set in step S35, and the rise confirmation process ends.

  As described above, for the rising at the timing t5, the “rising ON” flag is not set in the rising confirmation process, and the rising is not detected. Thereafter, during the period until the pulse p22 falls, the signal level is H level, but since the “rise ON” flag is not set, the determination result in step S13 is “NO”, and the rise confirmation in step S12 The process is repeated.

  At the timing t6 when the pulse p22 falls, the signal level transitions to the L level. Thereafter, since the signal level is L level during the period until the first pulse p31 of the signal sig3 rises, the determination result in step S13 is “NO”, and the rising confirmation process in step S12 is repeated.

  In the middle of the period until the pulse p31 rises, the value of the period counter exceeds 500 ms. After the value of the cycle counter exceeds 500 ms, the determination result in step S37 is “YES”, the “L acquisition ON” flag is set in step S38, and the “L signal ON” flag is set in step S31. In step S32, the “rise OFF” flag is set.

  At the timing t7 when the pulse p31 rises, the signal level changes to the H level. Similarly to the rising edge of the pulse p12, the “rising ON” flag is set in the rising confirmation process, and the rising edge is detected. Then, the determination result in step S13 is “YES”, and the determination result in step S14 is also “YES”.

  At the timing t7 when the pulse p31 rises, since the “L acquisition ON” flag is set, the determination result of step S24 is “YES”. In step S17, the time counted from the rising edge of the first pulse p21 of the signal sig2 (from timing t3) to the rising edge of the first pulse p31 of the signal sig3 (until timing t7) is counted by the period counter. Is a time within the range of 1000 ms ± tolerance.

  Since the time from timing t3 to timing t7 is 1000 ms, the determination result in step S17 is “YES”. Therefore, in step S18, the time measured by the cycle counter is stored, and in step S19a, the number of consecutive acquisitions of 1 second cycle is set to 1 by adding 1 to 0. In step S20, the cycle counter is set to 0 and the time measurement is started again. Since the number of 1-second continuous acquisitions is 1, the determination result in step S21 is “NO”, the process returns to step S12 again via step S25, and the rising confirmation process is performed.

  Thereafter, 1000 ms, which is the time from the rise of the first pulse of the signal per second to the rise of the first pulse of the signal per second immediately after the signal per second, is continuously acquired. Therefore, the number of consecutive acquisitions of 1 second period is sequentially added. Similar to the first embodiment, when the average value of the time measurement results is calculated, the second synchronization process ends.

  Also in the second embodiment, similarly to the first embodiment, after the first detected rising edge (first change, transition) exceeds the standby time (first time), the next rising edge (second change). , Transition) is detected, the time from the first detected rising to the next rising is counted, and a period of 1 second is obtained by determining whether the time is within an allowable range including 1 second. Second synchronization processing can be performed.

  In contrast to the first embodiment and the third embodiment described later, in the second embodiment, other rising edges (third change, transition) included in the standby time (first time) are rising edges (changes, (Transition) is not detected (see step S24 and step S37). In the second embodiment, the next rising edge (second change, detected after exceeding the waiting time (first time) from the first rising edge (first change, transition) thus detected. It is possible to appropriately determine whether the time until (transition) is within an allowable range including one second.

<Third Embodiment>
Next, the radio-controlled timepiece 1 according to the third embodiment will be described. The third embodiment is different from the first embodiment in the second synchronization processing. FIG. 7 is a flowchart showing the second synchronization processing according to the third embodiment. The rising confirmation process according to the third embodiment is the same as the rising confirmation process according to the first embodiment shown in FIG.

  In the flowchart of the second synchronization process according to the third embodiment, step S16 in the flowchart of the second synchronization process according to the first embodiment is omitted. Further, step S26 is added on the way to return to step S10 after step S15 and on the way to step S10 after step S21.

  After the reception process is started, the “rising ON” flag is set in the rising confirmation process in step S12 in the second synchronization process, the determination result in step S13 is “YES”, and the determination result in step S14 is “NO”. In step S15, the process is performed in the same manner as in the first embodiment until the “start-up acquired ON” flag is set, the period counter is set to 0, and the time measurement is started.

  When step S15 is performed, in step S26, the control unit 37 controls the sampling unit 31 to stop sampling until the value of the cycle counter exceeds 500 ms (the above-described standby time). In step S26, when the value of the period counter exceeds 500 ms, the control unit 37 controls the sampling unit 31 to resume sampling.

  When the sampling is resumed, the process returns to step S10, and the rising confirmation process is performed again in step S12 through steps S10 and S11. When the “rising ON” flag is set in the rising confirmation process in step S12, the determination result in step S13 is “YES”, and since the “rising acquisition completed ON” flag is set, the determination result in step S14 is "YES" is determined, and Step S17 is performed.

  Step S17, Step S18, Step S19a, Step S19b, Step S20 and Step S21 are performed in the same manner as in the first embodiment. If the number of consecutive acquisitions of 1 second period does not reach 10 in step S21, step S26 is performed again. In step S26, sampling is stopped until the value of the period counter exceeds 500 ms, and sampling is resumed when the value of the period counter exceeds 500 ms. In step S20, the cycle counter is set to 0, and time measurement is started again.

  When the number of 1-second continuous acquisitions reaches 10 in step S21, step S22 and step S23a are performed in the same manner as in the first embodiment. Step S23b is performed in the same manner as in the first embodiment. When step S23a or step S23b is performed, the second synchronization process ends. The processes after step S3 in the reception process are performed in the same manner as in the first embodiment. In this way, the reception process in the third embodiment is performed.

  Next, referring again to FIG. 9, the second synchronization processing according to the third embodiment will be described more specifically. As in the first embodiment, a case where the rising confirmation process in step S12 is started from timing t0 is illustrated.

  During the period from the timing t0 to the timing t1 when the pulse p12 rises, the signal level is L level, the “rising ON” flag is not set, and the determination result in step S13 of the second synchronization processing is “NO”. The rising confirmation process in step S12 is performed again.

  At the timing t1 when the pulse p12 rises, the signal level transits to the H level, and the “rise ON” flag is set. Since the “rising ON” flag is set, the determination result in step S13 of the second synchronization process is “YES”. Since the “rising acquisition completed ON” flag is not set, the determination result in step S14 is “NO”. In step S15, the “rising acquisition completed ON” flag is set, the cycle counter is set to 0, and the time is counted. Be started.

  In step S26, sampling is stopped until the period counter exceeds 500 ms, and when the period counter exceeds 500 ms, sampling is resumed. At the timing when sampling is resumed, the signal level is L level.

  Since the signal level is L level during the period from when sampling is resumed to when the pulse p21 rises, the determination result at step S13 is “NO”, and the rise confirmation process at step S12 is repeated.

  At the timing t3 when the pulse p21 rises, the signal level changes to the H level. Similarly to the rising edge of the pulse p12, the “rising ON” flag is set in the rising confirmation process, and the rising edge is detected. Then, the determination result in step S13 is “YES”, and the determination result in step S14 is also “YES”.

  In step S17, the time counted by the period counter from the rise of the second pulse p12 of the signal sig1 (from timing t1) to the rise of the first pulse p21 of the signal sig2 (until timing t3). Is a time within the range of 1000 ms ± tolerance.

  Since the time from timing t1 to timing t3 is 800 ms, the determination result in step S17 is “NO”. Therefore, in step S19b, the number of consecutive acquisitions of 1 second period is set to 0. In step S20, the cycle counter is set to 0 and the time measurement is started again. Since the 1-second period continuous acquisition number is 0, the determination result in step S21 is “NO”. In step S26, sampling is stopped until the period counter exceeds 500 ms, and when the period counter exceeds 500 ms, sampling is resumed. Thereafter, the process returns to step S12 again, and the rising confirmation process is performed.

  While the sampling is stopped, the period of the pulse p21, the period between the pulse p21 and the pulse p22, and the period of the pulse p22 are finished. Therefore, the rising edge of the pulse p22 is not detected. Since the signal level is L level during the period from when the sampling is resumed until the pulse p31 rises, the determination result at step S13 is “NO”, and the rising confirmation process at step S12 is repeated.

  At the timing t7 when the pulse p31 rises, the signal level changes to the H level. Similarly to the rising edge of the pulse p12, the “rising ON” flag is set in the rising confirmation process, and the rising edge is detected. Then, the determination result in step S13 is “YES”, and the determination result in step S14 is also “YES”.

  In step S17, the time counted from the rising edge of the first pulse p21 of the signal sig2 (from timing t3) to the rising edge of the first pulse p31 of the signal sig3 (until timing t7) is counted by the period counter. Is a time within the range of 1000 ms ± tolerance.

  Since the time from timing t3 to timing t7 is 1000 ms, the determination result in step S17 is “YES”. Therefore, in step S18, the time measured by the cycle counter is stored, and in step S19a, the number of consecutive acquisitions of 1 second cycle is set to 1 by adding 1 to 0. In step S20, the cycle counter is set to 0 and the time measurement is started again. Since the number of 1-second continuous acquisitions is 1, the determination result in step S21 is “NO”, the process returns to step S12 again, and the rising confirmation process is performed.

  Thereafter, 1000 ms, which is the time from the rise of the first pulse of the signal per second to the rise of the first pulse of the signal per second immediately after the signal per second, is continuously acquired. Therefore, the number of consecutive acquisitions of 1 second period is sequentially added. Similar to the first embodiment, when the average value of the time measurement results is calculated, the second synchronization process ends.

  Also in the third embodiment, similarly to the first embodiment, after the first detected rise (first change, transition) exceeds the standby time (first time), the next rise (second change). , Transition) is detected, the time from the first detected rising to the next rising is counted, and a period of 1 second is obtained by determining whether the time is within an allowable range including 1 second. Second synchronization processing can be performed.

  In contrast to the first embodiment and the second embodiment, in the third embodiment, the sampling is stopped during the waiting time (first time), so that other samples included in the waiting time (first time) are included. A rise (third change, transition) is not detected (see step S26). In the third embodiment, the next rising edge (second change, detected after exceeding the waiting time (first time) from the first rising edge (first change, transition) thus detected. It is possible to appropriately determine whether the time until (transition) is within an allowable range including one second. Further, in the third embodiment, power consumption required for sampling can be reduced as compared with a mode in which sampling is always performed.

<Modification>
The present invention is not limited to the above-described embodiments, and various modifications as described below are possible, for example. Moreover, the aspect and embodiment of a deformation | transformation described below can also combine suitably arbitrarily selected 1 or several.

  In the above-described embodiment, the UK MSF is exemplified as the received standard radio wave. However, the technology of the above-described embodiment may be applied to reception of other standard radio waves such as WWVB in the United States. FIG. 10 illustrates a received WWVB TCO signal, and is a timing chart showing a situation in which a signal siga having a pulse width of 800 ms and a signal sigb having a pulse width of 200 ms are continuous. In this example, a signal siga per second that originally has one pulse pa with a pulse width of 800 ms is received by being divided into two pulses pa1 and pa2 due to the influence of noise. The pulse pa1 rises at the start timing of the signal siga, and the pulse pa2 rises 300 ms after the start timing of the signal siga. The signal sigb has one pulse pb.

  In such a situation, when the method of the above-mentioned comparative form (method of measuring the time from the rising edge to the rising edge adjacent to each other) is applied, the time from the rising edge of the pulse pa1 to the rising edge of the pulse pa2 is 300 ms, or Since 700 ms, which is the time from the rising edge of the pulse pa2 to the rising edge of the pulse pb, is timed, one second cannot be acquired.

  On the other hand, by applying the method of the above-described embodiment, 1 second, which is the time from the rising edge of the pulse pa1 to the rising edge of the pulse pb, can be acquired. Since no rise occurs after 800 ms in the signal siga, a value between 800 ms and 1000 ms, for example, 900 ms is set as the waiting time. In addition, even when a single pulse pa is received without being divided into two pulses pa1 and pa2 because the influence of noise is small, it is the same that the rising edge of the pulse pb is detected after the standby time. 1 second, which is the time from the rising edge to the rising edge of the pulse pb, can be acquired.

  In the above-described embodiment, the transition from the first level to the second level detected by the transition detection unit 32 with the first level being a relatively low level and the second level being a relatively high level. A case where (change) is a rise is illustrated. If necessary, the transition (change) from the first level to the second level detected by the transition detection unit 32 with the first level set as a relatively high level and the second level as a relatively low level. , It may be falling.

DESCRIPTION OF SYMBOLS 1 ... Radio wave correction clock, 2a ... Antenna, 2b ... Reception circuit, 2 ... Reception part, 3 ... Processing part, 4 ... Memory | storage part, 5 ... Oscillation circuit, 6 ... Frequency division circuit, 7 ... Display part, 8 ... Operation part , 31... Sampling unit, 32... Transition detection unit, 33... Second determination unit, 34.

Claims (5)

A sampling unit for sampling a time code output signal acquired from a standard radio wave;
A detection unit to which the time code output signal sampled by the sampling unit is input;
A counter that keeps time,
The detection unit is controlled to detect the first change in which the time code output signal changes from the first level to the second level, and the elapsed time elapsed from the first change is counted. , Control the counter, determine whether the elapsed time exceeds a predetermined first time, and after the elapsed time exceeds the first time, the time code output signal is the first time A control unit that controls the detection unit to detect a second change that changes from a level to the second level;
A determination unit that determines whether the time from the first change to the second change is within a predetermined allowable range including 1 second;
When the determination result of the determination unit is a time within the allowable range, a time data acquisition unit that acquires time data based on the time code output signal with reference to the first change or the second change;
Radio correction watch with The controller is
The time code output signal included from the first change until the first time elapses is detected to detect a third change in which the time code output signal changes from the first level to the second level. Control the detector,
The determination unit
It is not determined whether the time is within the allowable range with respect to the time from the first change to the third change,
Determining whether the time is within the allowable range with respect to the time from the first change to the second change;
The radio wave correction watch according to claim 1. The controller is
The time code output signal included before the first time elapses from the first change so that the third change from the first level to the second level is not detected. Control the detector,
The radio wave correction watch according to claim 1. The controller is
The sampling of the time code output signal is stopped until the first time elapses from the first change, and when the first time elapses from the first change, the sampling of the time code output signal is performed. Controlling the sampling unit to resume,
The radio wave correction watch according to claim 1. The controller is
In the time code output signal sampled by the sampling unit, it is determined whether the time that the first level continues or the time that the second level continues is equal to or longer than a predetermined second time. ,
Controlling the detection unit to detect a change from the first level to the second level based on a result of the determination;
The radio wave correction timepiece according to any one of claims 1 to 4.

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