JP2018147260A - Recording and reproducing device, control method of recording and reproducing device, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure reliability of high-speed writing without retuning when card accesses occur continuously. In a recording/reproducing apparatus, clock supply means for supplying a clock for transmitting and receiving data to a storage medium, and for transmitting data to the storage medium according to the clock, the storage medium is the clock. Transmitting/receiving means for receiving the data transmitted according to the clock supplied by the supplying means according to the clock, and supplying the first clock when the transmitting/receiving means receives the data from the storage medium, and transmitting/receiving means When the data is transmitted to the storage medium, the control means controls to supply a second clock that is faster than the first clock. [Selection diagram] Figure 1

Description

  The present invention relates to a recording / reproducing apparatus, a control method for the recording / reproducing apparatus, and a program.

  When data is read from the SD memory card, the delay amount of data transmission from the card with respect to the clock given from the host to the card is a prescribed fixed delay amount. Therefore, the host side can perform card access without any problem by performing data latch at a predetermined amount of delay timing with respect to transmission clock transmission.

  However, in recent years, the above-mentioned delay amount cannot be defined as a fixed value due to an increase in clock speed accompanying an increase in the access speed of the memory card. For this reason, in UHS-I (Ultra High Speed-1), which is a high-speed standard for SD memory cards, a variable delay amount is required when a clock faster than a predetermined speed is used, and the data latch timing needs to be adjusted. It is prescribed. This adjustment operation of the latch timing is called tuning or calibration, and is generally performed when the memory card is mounted. However, since the delay amount described above varies depending on external factors such as the card temperature, even if tuning is performed, the delay amount changes as the card temperature changes due to repeated card access, and data transfer is not possible. There is a possibility of failure. On the other hand, since the card data cannot be transferred during tuning, frequent tuning leads to a decrease in transfer efficiency.

  Patent Document 1 proposes a solution to this problem. In the proposed method, when data output from the card is received (card reading), data acquisition timings of three phases different from each other within the phase range where data can be accurately received obtained by calibration (tuning) are set. Set. In addition, data is captured using three clocks having the same frequency and different phases for one data. Here, when a predetermined size (512 bytes, etc.) is received in three phases, the number of differences in each data obtained in the previous phase and the subsequent phase is counted with respect to the data taken in the center phase. To do. If there is a phase whose number differs from the total number by a predetermined number or more, the phase is shifted in the opposite direction of the phase to follow the change in the delay amount.

  However, when recording is started after the calibration has been performed, the delay amount may change during that time. In addition, the timing intervals of the three phases change depending on the temperature characteristics of the delay elements for making a timing difference, and for example, a phase in which data cannot be correctly received may enter between the phases. In these cases, the data reception by the center phase is performed in the very vicinity of the phase where the data cannot be correctly received, and the data transfer cannot be normally performed with a slight change in the delay amount. Therefore, even if the proposed method of Patent Document 1 is implemented, it is not possible to eliminate a decrease in transfer efficiency due to the occurrence of retuning during card access.

JP 2011-134209 A

  Therefore, the present invention provides a technique that can ensure the reliability of high-speed writing without performing retuning when card accesses occur continuously.

The present invention for solving the above problems is a recording / reproducing apparatus,
Clock supply means for supplying a clock for transmitting and receiving data to the storage medium;
Transmitting / receiving means for transmitting data to the storage medium in accordance with the clock, and receiving data transmitted in accordance with the clock supplied by the clock supply means in accordance with the clock;
A first clock is supplied when the transmission / reception means receives data from the storage medium, and a second clock faster than the first clock is supplied when the transmission / reception means transmits data to the storage medium. And control means for controlling as described above.

  According to the present invention, it is possible to provide a technique capable of ensuring the reliability of high-speed writing without performing retuning when card accesses occur continuously.

The block diagram which shows the structural example of the recording / reproducing apparatus corresponding to embodiment of invention. The block diagram which shows the structural example of the host controller circuit 111 corresponding to embodiment of invention. The flowchart which shows an example of operation | movement of the recording / reproducing apparatus corresponding to embodiment of invention. The sequence chart which shows an example of operation | movement of the recording / reproducing apparatus corresponding to embodiment of invention. The timing chart which shows an example of the signal state at the time of operation | movement of the recording / reproducing apparatus corresponding to embodiment of invention. The figure for demonstrating the delay of the data with respect to the clock corresponding to embodiment of invention.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. In the embodiment described below, an example in which the present invention is applied to a digital camera capable of writing / reading data to / from a connected memory card will be described as an example of a recording / reproducing apparatus. However, the present invention can be applied to any device (host device) capable of writing / reading data to / from a recording medium, and is not limited to a digital camera, for example, a personal computer, a mobile phone, a smartphone, a PDA, a digital video It can also be implemented as an arbitrary host device such as a camera, a tablet terminal, or a portable media player, an information processing device, an imaging device, a data generation device, or the like.

  FIG. 1 is a block diagram showing an example of the configuration of the digital camera 100 according to the present embodiment. A photographing lens 101 captures a subject image, limits the amount of light to a predetermined amount by a diaphragm 102, and then places a subject on the image sensor 103. Form an image. The formed subject image is digitized by the A / D converter 104, and gamma correction, white balance correction, noise reduction processing, and the like are performed by the image processing unit 105. In the present embodiment, the configuration from the photographing lens 101 to the image processing unit 105 is referred to as the imaging unit 10. In the following embodiment, a case where image data output from the imaging unit 10 is written in a memory card 112 as a storage medium will be described. However, the object to which the present invention can be applied is not limited to image data, but audio data, multimedia data including moving image data and audio data, or any other object that can be written to the memory card 112. It may be the data. These types of data can be collectively referred to as information data. The recording / reproducing apparatus as an embodiment of the present invention can further include an audio generation unit including a microphone, an A / D converter, and an audio processing unit in addition to the imaging unit 10 in order to generate information data. .

  The imaging unit 10 outputs uncompressed image data and image display data to the data bus 106, and the data is stored in the memory 113. The memory 113 may be configured as a DRAM, for example. The display 109 is a display unit that displays images and various types of information, and is configured by a liquid crystal panel, for example. The display driver 110 converts the image display data stored (held) in the memory 113 into a display signal for the display 109 and sequentially transfers it to the display 109 for display. Thus, the display 109 functions as an electronic viewfinder and can display an image. The image size conversion unit 107 converts the image size of the uncompressed image data stored in the memory 113 according to the moving image resolution setting set in the main body. For example, when the setting is “720P”, the uncompressed image data of FULL-HD (1920 × 1080 pixels) is converted into 1280 × 720 pixels, and is stored again in the memory (DRAM) 113. When the setting is “FULL-HD”, the image size conversion unit 107 does not operate.

  The encoding processing unit 108 compresses and encodes the uncompressed image data stored in the memory 113 as a moving image, generates encoded moving image data, and stores the encoded moving image data in the memory 113 again. The memory 113 provides a space as the above-described working memory and a memory space as the stream buffer 113A. Specifically, the encoded moving image data generated by the encoding processing unit 108 is stored in the memory 113 and read out from the memory 113 in accordance with the transfer status to the memory card 112, whereby the memory card Arbitration with the recording speed of 112 can be performed.

  The memory card 112 can be configured as a storage medium composed of a NAND flash memory and a flash controller that can be attached to and detached from the digital camera 100 main body. The memory card 112 is formatted with a FAT (File Allocation Table) file system compatible with PC. The encoded moving image data is filed according to the format and recorded on the memory card 112. The host controller circuit 111 transmits a command signal to the memory card 112 based on an instruction from the control unit 115 to be described later, and executes recording of encoded moving image data that is data to be transmitted from the memory 113 to the memory card 112. To do. The host controller circuit 111 also controls a series of operations (transfer) for reading the encoded moving image data from the memory card 112 and writing the encoded moving image data to the memory 113.

  The operation unit 114 is a user interface that receives an operation performed by a user through an operation key (not illustrated). The operation unit 114 can include, for example, a trigger key for instructing to start and stop shooting a moving image, a mode switch for setting a camera mode such as a shooting mode and a playback mode, and setting keys for various setting items. The control unit 115 is configured by one or more processors such as a CPU, for example, and executes programs stored in a ROM 116 described later to realize each process of the present embodiment described later. Display control is also performed by controlling the display driver 110 and the like. The ROM 116 is an electrically erasable / recordable non-volatile memory, and stores the above-described program, setting contents of the main body, and the like. The ROM 116 may be configured as a data storage device such as a hard disk. The system clock generation unit 117 generates and supplies a clock used by each block such as the host controller circuit 111 and the control unit 115 at a frequency necessary for each block.

  Note that FIG. 1 shows a configuration including an imaging unit including the imaging lens 101 and the image processing unit 105 in consideration of the case where the present invention functions as a digital camera. However, as an embodiment of the invention, any device that controls the writing of data to the memory card 112 may be used. Therefore, a data recording device, a data writing device, a card reader / writer, or the like having a configuration that does not include an imaging unit. It can also be realized as.

  Next, the configuration and operation of the host controller circuit 111 will be described with reference to FIG. FIG. 2 is a block diagram illustrating an example of the configuration of the host controller circuit 111. In FIG. 2, a range indicated by a dotted line frame indicates the host controller circuit 111. Further, the memory card 112, the memory 113, and the control unit 115 also indicate blocks with the same symbols in FIG.

  The host controller 201 controls the data transmission / reception operation to / from the memory card 112 and controls the entire host controller circuit 111 in accordance with an instruction from the control unit 115. The buffer 202 ensures a signal driving capability necessary for distributing the operation clock from the system clock generation unit 117 to each block in the host controller circuit 111. The response determination unit 203 receives a response signal sent back to indicate that the memory card has responded after transmitting a command from the host controller 201 to the memory card 112, and determines the content thereof.

  The memory interface 204 is an interface for reading data to be written to the memory card 112 from the memory 113 and writing data read from the memory card 112 to the memory 113. A CRC (Cyclic Redundancy Check) status determination unit 205 transmits data from the memory 113 to the memory card 112, and then receives a CRC status signal sent back to indicate whether or not the data transfer is successful. The contents are determined.

  The read clock generation unit 206 generates and supplies a clock (first clock) that is a timing base in data reception from the memory card 112. The write clock generation unit 207 generates and supplies a clock (second clock) that is a timing base in data transmission to the memory card 112. At this time, the first clock and the second clock can be generated from the same clock source supplied from the system clock generation unit 117. In the present embodiment, the second clock can be a clock faster than the first clock. In other words, the frequency of the second clock can be higher than the frequency of the first clock.

  The command buffer 208 receives a command signal from the host controller 201 and sends a command signal (CMD) in accordance with the timing of the write clock signal from the write clock generation unit 207 in cooperation with the output D-flip flop 214. . The response buffer 209 captures the response signal from the memory card 112 at the timing of the read clock signal from the read clock generation unit 206 and sends the response signal to the response determination unit 203 in cooperation with the input D-flip flop 215. .

  Also, the write data buffer 210 sends data read from the memory 113 through the memory interface 204 as write data in accordance with the timing of the write clock signal from the write clock generation unit 207 by the cooperative operation with the output D-flip flop 216. (DAT). The Read data buffer 211 captures data from the memory card 112 at the timing of the read clock signal from the read clock generation unit 206 (DAT) by cooperative operation with the input D-flip flop 217, and the captured data is The data is sent to the memory 113 through the memory interface 204. The status buffer 212 fetches the CRC status signal from the memory card 112 at the timing of the read clock signal from the read clock generation unit 206 (DAT) by the cooperative operation with the input D-flip flop 218, and receives the CRC status signal. The data is sent to the determination unit 205. The clock switch 213 switches between outputting a clock signal from the read clock generation unit 206 or a clock signal from the write clock generation unit 207 as a card clock signal (CLK) to be sent to the memory card 112. The input / output buffer group 219 secures signal driving capability necessary for each signal communication between the host controller circuit 111 and the memory card 112, and switches the input / output direction of data based on an instruction from the host controller 201. .

  In the memory card 112 of the present embodiment, the clock used for access between the host and the card is supplied in one direction from the host to the card. When data is transmitted from the host to the card, data or signals are transmitted. Since the direction of the clock and the direction of the clock supply are the same, the host transmits data at a timing that satisfies the setup-hold period defined by the card-side standard with respect to the clock.

  On the other hand, when sending data from the card to the host, if the clock frequency is below the specified value, the card will send data at a timing within the delay amount specified by the card-side standard with respect to the clock sent from the host. To the host. Hereinafter, this is referred to as “fixed delay amount mode”. In addition, when the clock frequency is higher than the specified value, the data output timing from the card is not defined by the minimum delay or maximum delay from the rising or falling of the clock, and the clock is output to the card due to the influence of temperature, etc. The delay time from receiving data to receiving data changes. Hereinafter, this is referred to as “variable delay amount mode”.

  In the present embodiment, the first clock generated by the read clock generation unit 206 is a clock having a clock frequency for the “fixed delay amount mode”. The first clock has a frequency such that the delay of output data assumed when the memory card 112 is operated in accordance with the first clock falls within a predetermined period from the rise or fall of the first clock. Further, the second clock generated by the write clock generation unit 207 is a clock having a clock frequency at which the “variable delay amount mode” is set. In the second clock, the delay of output data assumed when the memory card 112 is operated according to the second clock is not defined by a predetermined delay time from the rise or fall of the second clock, and , Having a frequency that can vary depending on operating conditions. In the present embodiment, for example, as shown in FIG. 5 described later, the frequency of the first clock can be set to 100 MHz and the frequency of the second clock can be set to 200 MHz. However, these are only examples.

  Here, an example of the relationship between the clock and the data delay will be described with reference to FIG. FIG. 6A shows an example in which data is delayed with respect to the rising edge of the clock, and FIG. 6B shows an example in which data is delayed with respect to the falling edge of the clock.

  First, in FIG. 6A, the data 602 is delayed by Td1 with respect to the rising edge of the clock 601. In this case, data latch fails at timings 603 and 605, but latching succeeds at timing 604. In FIG. 6B, the data 607 is delayed by Td2 with respect to the falling edge of the clock 606. In this case, data latch fails at timings 608 and 610, but latching succeeds at timing 609. In the above-described fixed delay amount mode, the data delay amount from the rising edge or falling edge of the clock falls within a specified range, so that data can be received by latching at a predetermined position. On the other hand, in the variable delay amount mode, the delay amount changes depending on conditions, and therefore data cannot be received accurately even if latched at a fixed timing. However, the variable delay amount mode becomes a problem when reading data from the memory card 112 as described above. In this embodiment, the low-speed clock frequency of the fixed delay amount mode is used when reading data. Therefore, the problem that data reception fails due to the variable delay amount cannot occur.

  The operation in the camera shooting mode of the digital camera 100 of the present embodiment having the above configuration will be described. FIG. 3 is a flowchart showing an operation in the camera photographing mode of the digital camera 100 of the present embodiment. The processing corresponding to the flowchart is realized, for example, by one or more processors functioning as the control unit 115 executing a corresponding program (stored in the ROM 116 or the like) and controlling the operation of each block such as the host controller circuit 111 or the like. it can.

  First, when the power of the digital camera 100 is turned on and the operation mode of the digital camera 100 is set to the camera photographing mode, the memory interface 204 reads the file system information from the memory card 112 and records the memory card 112 in S301. Execute mount processing to make it possible. As described above, after the power is turned on, the mounting process is executed before the data recording to the memory card 112 is started. In subsequent S302, the control unit 115 determines whether or not a recording instruction given by the user operating the operation unit 114 has been received. If it is determined that the recording instruction has been accepted, the process proceeds to S303. On the other hand, if it is determined that the recording instruction has not been received, the process returns to S302 to monitor the reception of the instruction from the user. In step S <b> 303, the control unit 115 controls the imaging unit, starts recording a moving image in response to a recording instruction, and stores the generated uncompressed image data in the memory 113. In subsequent S <b> 304, the encoding processing unit 108 performs H.264 processing on the uncompressed image data stored in the memory 113. H.264, MPEG-2 or other interframe coding or intra coding is performed, and the coded stream data is accumulated in the area of the stream buffer 113A on the memory 113.

  In subsequent S305, the control unit 115 determines whether or not an instruction to stop recording performed by the user operating the operation unit 114 has been received. If it is determined that a recording stop instruction has been received, the process proceeds to S309. On the other hand, if it is determined that a recording stop instruction has not been received, the process proceeds to S306. First, in S306, the control unit 115 determines whether or not the amount of encoded stream data stored in the stream buffer 113 exceeds a predetermined amount (for example, 2 MB). When the control unit 115 determines that the accumulated amount exceeds the predetermined amount, the process proceeds to S307. On the other hand, when it is determined that the accumulated amount does not exceed the predetermined amount, the accumulated amount is continuously monitored. In subsequent S307, the control unit 115 instructs the host controller circuit 111 to issue a Write command for writing a predetermined amount of data to the memory card 112. The host controller circuit 111 writes encoded stream data from the stream buffer 113A on the memory 113 to the memory card 112. Details of the operation by the Write command will be described later. Thereafter, in S308, the host controller 201 executes FAT update, and the process returns to S305.

  Further, assuming that the recording stop instruction is accepted in S305, when the process proceeds to S309, in S309, the host controller 201 writes the encoded stream data remaining in the stream buffer 113A to the memory card 112. Thereafter, in S310, the host controller 201 performs FAT update, and recording is stopped in S311. Thereafter, the processing returns to S302, and the recording start operation waiting state from the user is awaited.

  Details of operations related to data write processing by the Write command will be described below. FIG. 4 is a sequence chart showing details of an operation related to a data writing process by the Write command. FIG. 5 is a timing chart showing the signal state between the host and the memory card along with the passage of time at the time of the Write command.

  In FIG. 4, the host controller 201, the memory card 112, and the control unit 115 show blocks with the same symbols in FIGS. 1 and 2, respectively. Shown along the course. When the control unit 115 instructs the host controller 201 to execute the write command in S401, the host controller 201 switches the clock switch 213 to the second clock side in S402. In step S403, the host controller 201 starts clock output to the memory card.

  The state of the clock at this time is as shown in FIG. In FIG. 5, the clock (CLK), command (CMD), and data (DAT), which are input / output lines of the memory card 112, are shown in correspondence with the passage of time. At timing 501, the host controller 201 switches the clock switch 213 to the second clock side, and the clock signal becomes a signal of 200 MHz.

  Returning to FIG. 4, in step S404, the host controller 201 controls the command buffer 208 and issues a write command to the memory card. When the host controller 201 completes the issuance of the write command, the host controller 201 sets the clock switch 213 to the first clock side in S405 and waits for a command response transmission from the memory card side.

  FIG. 5 shows that the Write command is issued from the host side to the card side on the CMD at timing 502 corresponding to the processing in S404. The Write command is issued between timings 502 to 503. When the Write command is completed, at timing 503, CLK is switched to a clock signal of 100 MHz. In this embodiment, the second clock is twice as fast as the first clock. However, the second clock only needs to be faster than the first clock, and is not necessarily limited to twice. In FIG. 5, the second clock is 200 MHz and the first clock is 100 MHz.

  Thereafter, in S406, a command response is transmitted from the memory card 112 to the host controller circuit 111. When the response buffer 209 completes the reception, the response determination unit 203 determines the content of the command response. If information indicating an error is included in the command response, an error interrupt is input from the host controller 201 to the control unit 115 in S407, and the content of the command response is notified. If the response determination unit 203 does not detect an error, the host controller 201 switches the clock switch 213 to the second clock side in S408. FIG. 5 shows that the host controller circuit 111 receives a response from the memory card 112 on the CMD after the clock signal is switched to 100 MHz at the timing 503. When the response reception is completed at timing 504, CLK is switched from 100 MHz to 200 MHz.

  In step S <b> 409, the host controller 201 starts transmission of data acquired from the memory 113 via the memory interface 204 to the memory card 112 via the write data buffer 210. Note that this data transmission is performed with a “block” of a predetermined size (for example, 512 bytes) as one unit, and each time the communication in the block unit is completed, the status relating to the operation performed by the memory card 112 on the received data for one block. For example, a CRC status indicating whether or not a communication error has occurred is returned from the memory card 112 to the host controller 201.

  Specifically, when the transmission of one block of data is completed, the host controller 201 switches the clock switch 213 to the first clock side in S410 and waits for CRC status transmission from the memory card 112 side. In step S411, the CRC status is transmitted from the memory card 112 to the host controller circuit 111, and the reception is completed in the status buffer 212. Thereafter, the CRC status determination unit 205 determines the contents of the CRC status. If error information indicating that block communication has failed is included, in step S412, the host controller 201 inputs an error interrupt indicating a transfer error to the control unit 115 and notifies the contents of the CRC status. In step S413, the host controller 201 switches the clock switch 213 to the second clock side.

  In FIG. 5, after the clock signal is switched to 200 MHz at timing 504, block data is transmitted on DAT, and when data transmission for one block is completed at timing 506, CLK is switched from 200 MHz to 100 MHz. Is shown. The status is transmitted from the memory card 112 to the host controller circuit 111 while CLK is 100 MHz. When transmission of status is completed at timing 507, CLK is switched from 100 MHz to 200 MHz.

  The operations from S409 to S413 described above are repeated as many times as the number of transfer blocks notified from the control unit 115 to the host controller 201 in accordance with the Write instruction in S401. When all the data transfers are completed, in S414, the host controller 201 issues an end interrupt indicating the end of the Write command to the control unit 115. Thereafter, in step S415, the control unit 115 instructs the host controller 201 to issue a Stop command for notifying the memory card 112 of the end of data transfer. In subsequent S 416, the host controller 201 controls the command buffer 208 and issues a Stop command to the memory card 112. When the issuance of the command is completed, the host controller 201 switches the clock switch 213 to the first clock side in S417 and waits for a command response transmission from the memory card 112 side.

  Thereafter, when a command response is transmitted from the memory card 112 to the host controller circuit 111 in S418, the response buffer 209 receives it. The content of the received command response is determined by the response determination unit 203. If the command response includes information indicating an error, the host controller 201 issues an error interrupt to the control unit 115 in S419 and the content of the command response. To be notified. If there is no error notification, the host controller 201 switches the clock switch 213 to the second clock side in S420, and the clock output stops in S421. Finally, in S422, the host controller 201 performs a write end interrupt indicating that the operation of a series of write instructions from S401 is completed to the control unit 115, and the series of operations ends.

  In the lower part of FIG. 5, writing of the final block data is completed, and after the CLK is switched from 200 MHz to 100 MHz, the status is transmitted from the memory card 112 to the host controller circuit 111. When the status transmission is completed at timing 508, CLK is switched from 100 MHz to 200 MHz, and at timing 509, a Stop command is transmitted from the host controller circuit 111 to the memory card 112 on the CMD. When command transmission is completed at timing 510, CLK is switched to 100 MHz, and response transmission from the memory card 112 is performed until timing 511. When the reception of the response is completed, CLK switches to 200 MHz again.

  In the configuration of the present embodiment described above, the high-speed clock frequency that is not affected by the variable delay amount and is in the “variable delay amount mode” at the time of command transmission from the host controller circuit 111 to the memory card 112 and at the time of write data transmission. Access by. On the other hand, when a command response or CRC status is received from the memory card 112 and when read data is received, the access is performed at a clock frequency at which the “fixed delay amount mode” is set. As a result, the use of a high-speed clock frequency is limited to writing to the card, so even if high-speed card writing occurs continuously for a long time, re-tuning is not required and high-speed writing reliability is ensured. be able to.

(Other examples)
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in the computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

10 shooting unit, 111 host controller circuit, 112 memory card, 113 memory, 115 control unit, 201 host controller

Claims (13)

Clock supply means for supplying a clock for transmitting and receiving data to the storage medium;
Transmitting / receiving means for transmitting data to the storage medium in accordance with the clock, and receiving data transmitted in accordance with the clock supplied by the clock supply means in accordance with the clock;
A first clock is supplied when the transmission / reception means receives data from the storage medium, and a second clock faster than the first clock is supplied when the transmission / reception means transmits data to the storage medium. And a control means for controlling the recording / reproducing apparatus.   2. The recording according to claim 1, wherein the control unit switches a speed of the clock supplied by the clock supply unit prior to transmission of data by the transmission / reception unit and reception of data by the transmission / reception unit. Playback device. The data transmitted by the transmission / reception means includes a command for writing data to the storage medium, and the data received by the transmission / reception means includes a response transmitted from the storage medium in response to the command. Included,
The control means controls to supply the second clock when the transmission / reception means transmits the command, and to supply the first clock when the transmission / reception means receives the response. The recording / reproducing apparatus according to claim 1 or 2.   The control means controls to switch the clock supplied from the clock supply means to the first clock after transmission of the command and to switch to the second clock after reception of the response. Item 4. The recording / reproducing apparatus according to Item 3. A memory for holding data recorded in the storage medium;
The data transmitted by the transmission / reception means includes the recorded data held by the memory, and the data received by the transmission / reception means relates to a status relating to operations performed by the storage medium on the recorded data. 5. The recording / reproducing apparatus according to claim 1, wherein data is included.   The transmission / reception means transmits the recorded data to the storage medium in units of blocks of a predetermined size, and receives the data related to the status each time data corresponding to one block is transmitted. 6. The recording / reproducing apparatus according to 5.   The control means controls the clock supplied from the clock supply means to be switched to the first clock after transmission of data corresponding to the one block, and to be switched to the second clock after reception of data relating to the status. The recording / reproducing apparatus according to claim 6.   The first clock is configured so that a delay of output data assumed when the storage medium operates according to the first clock falls within a predetermined period from the rising or falling edge of the first clock. 8. The recording / reproducing apparatus according to claim 1, wherein the recording / reproducing apparatus has an operating frequency.   In the second clock, the delay of output data assumed when the storage medium operates according to the second clock is not defined by a predetermined delay time from the rising or falling of the second clock, and 9. The recording / reproducing apparatus according to claim 1, wherein the recording / reproducing apparatus has a frequency that can vary depending on operating conditions.   10. The recording / reproducing apparatus according to claim 1, wherein the clock supply means supplies the first clock and the second clock using signals from the same clock source. .   The recording / reproducing apparatus according to claim 1, further comprising a generating unit that generates the data. A clock supply step for supplying a clock for transmitting and receiving data to the storage medium;
A transmission / reception step of transmitting data to the storage medium according to the clock, and receiving the data transmitted according to the clock supplied by the storage medium in the clock supply step according to the clock;
In the transmission / reception step, a first clock is supplied when data from the storage medium is received, and when a data is transmitted to the storage medium in the transmission / reception step, a second clock faster than the first clock is supplied. And a control process for controlling the recording / reproducing apparatus.   The program for functioning a computer as each means of the recording / reproducing apparatus of any one of Claim 1 to 11.

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