JP2018019040A - Photodetection device and photodetection system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To charge generated in a deep part of a semiconductor substrate when light is incident because it moves to a PN junction region by diffusion, and therefore, an electric charge generated in a deep part of the semiconductor substrate as compared with an electric charge generated in the first surface of the semiconductor substrate. May take a long time to be induced in the PN junction region after the electric charge is generated. SOLUTION: A photoelectric conversion unit having a PN junction composed of a first semiconductor region and a second semiconductor region of a first conductive type and an opposite conductive type, an electrode, and arranged between the electrode and a semiconductor substrate. An optical detection device having an embedded portion having a dielectric member in contact with the second semiconductor region, the second semiconductor region being arranged at a position deeper than the first semiconductor region with respect to the first surface, and the embedded portion. Is arranged from the first surface to a position deeper than the first semiconductor region with respect to the first surface, so that the inversion layer formed between the electrode and the second semiconductor region and the first semiconductor region are in contact with each other. It is characterized in that a potential is supplied to the first semiconductor region, the second semiconductor region, and the electrodes. [Selection diagram] Fig. 3

Description

  The present invention relates to a light detection device and a light detection system that perform photoelectric conversion.

  2. Description of the Related Art Conventionally, a photodetector that can detect weak light of a single photon level using avalanche (electron avalanche) doubling is known. Patent Document 1 discloses a pixel having a SPAD (Single Photo Avalanche Diode) in which a photo charge caused by a single photon causes avalanche amplification in a PN junction region of a semiconductor region constituting a photoelectric conversion unit. In addition, the SPAD of Patent Document 1 has a DTI structure that separates a photoelectric conversion unit and an annihilation circuit (quenching circuit), thereby downsizing one pixel and leaking between pixels when a plurality of pixels are arranged. Current is suppressed.

JP 2014-225647 A

  The SPAD described in Patent Document 1 has a PN junction region serving as a region for detecting charges near the surface of the semiconductor substrate. The charges generated in the deep part of the semiconductor substrate when light is incident are detected by moving to the PN junction region by diffusion. For this reason, the charge generated in the deep part of the semiconductor substrate may take longer to be detected from the generation of the charge than the charge generated on the surface of the semiconductor substrate.

  Therefore, the present invention provides a photodetection device that can reduce the time taken to detect charges generated in the deep part of a semiconductor substrate.

  The present invention relates to a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first semiconductor region having signal charges as majority carriers, and a charge of opposite conductivity type to the signal charges as majority carriers. Embedded with a photoelectric conversion part having a PN junction constituted by a second semiconductor region, an electrode embedded in the semiconductor substrate, and a dielectric member disposed between the electrode and the semiconductor substrate and in contact with the second semiconductor region The second semiconductor region is disposed deeper than the first semiconductor region with respect to the first surface, and the embedded portion extends from the first surface to the first surface. The first semiconductor region, the inversion layer formed between the electrode and the second semiconductor region, and the first semiconductor region are in contact with each other, It is characterized in that a potential is supplied to the electrode. .

  It is possible to reduce the time required to detect the charge generated in the deep part of the semiconductor substrate.

Photodetector block diagram Block diagram of pixel including equivalent circuit Cross-sectional schematic diagram of the photodetection device Energy band diagram for line segment CD Potential structure diagram in line segment EG Optical response performance diagram Plane schematic diagram and cross-sectional schematic diagram of the photodetection device Plane schematic diagram and cross-sectional schematic diagram of the photodetection device Plane schematic diagram of the photodetection device Plane schematic diagram of the photodetection device Plane schematic diagram of the photodetection device Photodetection system block diagram Photodetection system block diagram

  An embodiment of a photodetection device applicable to the present invention will be described with reference to FIGS. Parts denoted by the same reference numerals in the drawings indicate the same element or the same region.

  FIG. 1 is a block diagram of a photodetection device 10 according to an embodiment of the present invention. The light detection device 10 includes a pixel unit 106, a control pulse generation unit 109, a horizontal scanning circuit unit 104, a column circuit 105, a signal line 107, and a vertical scanning circuit unit 103.

  A plurality of pixels 100 are arranged in a matrix in the pixel portion 106. One pixel 100 includes a photoelectric conversion element 101 and a pixel signal processing unit 102. The photoelectric conversion element 101 converts light into an electric signal, and the pixel signal processing unit 102 outputs the converted electric signal to the column circuit 105.

  The vertical scanning circuit unit 103 receives the control pulse supplied from the control pulse generation unit 109 and supplies the control pulse to each pixel 100. For the vertical scanning circuit unit 103, a logic circuit such as a shift register or an address decoder is used.

  The signal line 107 supplies a signal output from the pixel 100 selected by the vertical scanning circuit unit 103 to a circuit subsequent to the pixel 100 as a potential signal.

  The column circuit 105 receives a signal of each pixel 100 via the signal line 107 and performs predetermined processing. The predetermined process is a process of removing noise from the input signal, amplifying it, etc., and converting it to a form to be output to the outside of the sensor. For example, the column circuit has a parallel-serial conversion circuit.

  The horizontal scanning circuit unit 104 supplies the column circuit 105 with a control pulse for sequentially outputting the signals processed by the column circuit 105 to the output circuit 108.

  The output circuit 108 includes a buffer amplifier, a differential amplifier, and the like, and outputs a signal output from the column circuit 105 to an external recording unit or signal processing unit of the photodetection device 10.

  In FIG. 1, the arrangement of the pixels 100 in the pixel portion 106 may be arranged in a one-dimensional manner, or may be composed of only a single pixel. Further, in the vertical scanning circuit unit 103, the horizontal scanning circuit unit 104, and the column circuit 105, the pixel unit 106 may be arranged for each block by dividing a plurality of pixel columns into blocks. Further, it may be arranged in each pixel column.

  The functions of the pixel signal processing unit 102 are not necessarily provided one by one for all the pixels. For example, one pixel signal processing unit 102 may be shared by a plurality of pixels 100 and signal processing may be sequentially performed. Further, the pixel signal processing unit 102 may be provided on a semiconductor substrate different from the photoelectric conversion element 101 in order to increase the aperture ratio of the photoelectric conversion element 101. In this case, the photoelectric conversion element 101 and the pixel signal processing unit 102 are connected via a connection wiring provided for each pixel. The vertical scanning circuit unit 103, the horizontal scanning circuit unit 104, the signal line 107, and the column circuit 105 may also be provided on different semiconductor substrates as described above.

  FIG. 2 shows an example of a block diagram including an equivalent circuit of the pixel 100 in the present embodiment. In FIG. 2, one pixel 100 includes a photoelectric conversion element 101 and a pixel signal processing unit 102. The photoelectric conversion element 101 includes a photoelectric conversion unit 201 and a control unit 202.

  The photoelectric conversion unit 201 generates a charge pair corresponding to incident light by photoelectric conversion. For example, a photodiode is used for the photoelectric conversion unit 201.

  A potential based on a potential VH higher than the potential VL supplied to the anode is supplied to the cathode of the photoelectric conversion unit 201. A potential is supplied to the anode and the cathode of the photoelectric conversion unit 201 so that a reverse bias is applied so that the photoelectric conversion unit 201 becomes an avalanche diode. By performing photoelectric conversion in a state where such a reverse bias potential is supplied, charges generated by incident light cause avalanche amplification and an avalanche current is generated.

  When a reverse bias potential is supplied and the potential difference between the anode and the cathode is larger than the breakdown voltage, the avalanche diode operates in a Geiger mode. SPAD is a photodiode that detects a weak signal of a single photon level at high speed using Geiger mode operation.

  Further, when the potential difference between the anode and the cathode of the photoelectric conversion unit 201 is equal to or higher than the potential difference at which the charge generated in the photoelectric conversion unit 201 causes avalanche amplification and is equal to or lower than the breakdown voltage, the avalanche diode is in a linear mode. . An avalanche photodiode that performs light detection in the linear mode is called an avalanche photodiode (APD). In the present embodiment, the photoelectric conversion unit 201 may operate as any avalanche diode. The potential difference that causes avalanche amplification will be described later.

  The control unit 202 is connected to a power supply voltage that supplies a high potential VH and the photoelectric conversion unit 201. The control unit 202 has a function of replacing a change in avalanche current generated in the photoelectric conversion unit 201 with a voltage signal. Further, the control unit 202 functions as a load circuit (quenching circuit) at the time of signal amplification by avalanche amplification, and functions to suppress avalanche amplification by suppressing the voltage supplied to the photoelectric conversion unit 201 (quenching operation). As the control unit 202, for example, a resistance element or an active quench circuit that actively suppresses avalanche amplification by performing feedback control by detecting an increase in avalanche current is used.

  The pixel signal processing unit 102 includes a waveform shaping unit 203, a time / digital conversion circuit 204 (Time to Digital Converter: TDC), a memory 205, and a selection circuit 206.

  The waveform shaping unit 203 shapes the voltage change obtained when detecting the photon level signal and outputs a pulse signal. For example, an inverter circuit is used as the waveform shaping unit 203. Moreover, although the example which used one inverter was shown as the waveform shaping part 203, the circuit which connected the some inverter in series may be used, and the other circuit which has a waveform shaping effect may be used.

  The generation timing of the pulse signal output from the waveform shaping unit 203 is converted into a digital signal by the TDC 204.

  A control pulse pREF (reference signal) is supplied to the TDC 204 via the drive line 207 from the vertical scanning circuit unit 103 of FIG. The TDC 204 acquires, as a digital signal, a signal when the input timing of the signal output from each pixel via the waveform shaping unit 203 is a relative time with the control pulse pREF as a reference.

  As the circuit of the TDC 204, for example, a delay line method in which a buffer circuit is connected in series to create a delay, a looped TDC method in which a delay line is connected in a loop shape, or the like is used. Other methods may be used, but a circuit method that can achieve a time resolution equal to or higher than the time resolution of the photoelectric conversion unit 201 is better.

  A digital signal representing the pulse detection timing obtained by the TDC 204 is held in one or more memories 205.

  The selection circuit 206 is supplied with a control pulse pSEL from the vertical scanning circuit unit 103 in FIG. 1 via the drive line 208, and switches between electrical connection and non-connection between the memory 205 and the signal line 107. As the selection circuit 206, for example, a transistor or a buffer circuit for outputting a signal outside the pixel is used.

  When a plurality of memories 205 are arranged, a plurality of signals are supplied to the selection circuit 206, so that when the digital signal held in the memory 205 is output to the signal line 107, the output to the signal line 107 for each memory. Can be controlled.

  Note that a switch such as a transistor may be provided between the control unit 202 and the photoelectric conversion unit 201 or between the photoelectric conversion element 101 and the pixel signal processing unit 102 to switch the electrical connection. Similarly, the supply of the high potential VH supplied to the control unit 202 or the low potential VL supplied to the photoelectric conversion element 101 may be electrically switched using a switch such as a transistor.

  FIG. 3 is a schematic cross-sectional view of the photodetecting device 10 of the present embodiment. In the present embodiment, the charge polarity used as the signal charge among the charge pairs generated in the photoelectric conversion unit 201 is referred to as a first conductivity type. The opposite conductivity type to the first conductivity type is referred to as the second conductivity type. In the present embodiment, as an example, the charge of the first conductivity type is assumed to be an electron, and the charge of the second conductivity type opposite to the first conductivity type is assumed to be a hole. However, the second conductivity type charge may be an electron, and the first conductivity type charge may be a hole.

  The semiconductor substrate 11 has a first surface and a second surface that face each other. For example, the first surface is the surface of the semiconductor substrate 11, and the second surface facing the first surface is the back surface of the semiconductor substrate 11. In the present embodiment, the depth direction is deep from the first surface toward the second surface.

  An N-type semiconductor region 1 (first semiconductor region) in which signal charges are majority carriers is disposed on the first surface side of the semiconductor substrate 11. The P-type semiconductor region 2 (second semiconductor region) is disposed deeper than the N-type semiconductor region 1 with respect to the first surface of the semiconductor substrate 11. The N-type semiconductor region 1 and the P-type semiconductor region 2 constitute a PN junction and constitute a photoelectric conversion unit 201. The N-type semiconductor region 1 is supplied with a potential that is reversely biased with respect to the potential supplied to the P-type semiconductor region 2. By supplying a reverse bias to the photoelectric conversion unit 201 in this way, an electric field is generated between the N-type semiconductor region 1 and the P-type semiconductor region 2 between the PN junctions.

  In the present embodiment, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 2 is set so that the electric field generated between the N-type semiconductor region 1 and the P-type semiconductor region 2 constituting the PN junction becomes sufficiently large. . Here, the term “sufficiently large” means that the electrons affected by the electric field cause avalanche amplification. That is, this is a potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 2 in which the photoelectric conversion unit 201 realizes an operation as an avalanche diode (APD or SPAD).

  The impurity concentration of the N-type semiconductor region 1 is set to an impurity concentration that does not deplete all the regions of the N-type semiconductor region 1 when a potential difference that causes avalanche amplification is supplied between the PN junctions.

Specifically, the impurity concentration of the N-type semiconductor region 1 is 6.0 × 10 ¹⁸ [atms / cm ³ ] or more, and the impurity concentration of the P-type semiconductor region 2 is 5.0 × 10 ¹⁶ [atms / cm ³ ]. That's it. This is because noise may occur on the first surface of the semiconductor substrate 11 if the depletion layer region expands so as to be in contact with the first surface of the semiconductor substrate 11. However, it is not restricted to these impurity concentrations.

  Note that the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 2 in which the above-described photoelectric conversion unit 201 realizes an operation as an avalanche diode (APD or SPAD) is specifically 6 V or more.

  Considering the above-described impurity concentration relationship, more preferably, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 2 is 10 V or more, and the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 2 is 30 V or less. . At this time, for example, a potential of 10 V to 30 V is supplied to the N-type semiconductor region 1, and a potential of −10 V to 0 V is supplied to the P-type semiconductor region 2. However, if the potential difference is 6 V or more, the potential is not limited to these.

  In FIG. 3, the P-type semiconductor region 2 is a region having the same impurity concentration as an example. However, the P-type semiconductor region 2 may have an impurity concentration gradient so as to have a potential structure in which charges move to the first surface side of the semiconductor substrate 11.

  For example, this is a case where the impurity concentration has a gradient in which the impurity concentration decreases from a deep position to a shallow position with respect to the first surface. At this time, for example, the P-type semiconductor region 2 includes the first region, the second region disposed deeper than the first region with respect to the first surface, and the first region and the second region with respect to the first surface. And a third region disposed deeper than the region. When the first region has the first impurity concentration, the second region has a second impurity concentration lower than the first impurity concentration. The third region has a third impurity concentration higher than the first impurity concentration and the second impurity concentration. However, the third region may have a third impurity concentration that is lower than the first impurity concentration and higher than the second impurity concentration.

  According to such a configuration, the P-type semiconductor region 2 has an impurity concentration gradient that has a potential structure in which charges move to the first surface side of the semiconductor substrate 11. In addition, the third region makes it possible to suppress leakage charges that may be generated in the pixels when a plurality of pixels are arranged on the same semiconductor substrate 11. Furthermore, the impurity concentration of the P-type semiconductor region 2 in the PN junction is higher than the impurity concentration in the region deeper than the PN junction with respect to the first surface of the semiconductor substrate 11. This makes it possible to increase the strength of the electric field generated between the PN junctions by narrowing the depletion layer width in the PN junction.

  It is preferable that the P-type semiconductor region is not disposed at a position shallower than the N-type semiconductor region 1 with respect to the first surface and overlapping the N-type semiconductor region 1 in plan view. According to such a configuration, it is possible to suppress avalanche amplification of unnecessary charges generated on the surface of the semiconductor substrate 11.

  The P-type semiconductor region 3 (fourth semiconductor region) is electrically connected to the P-type semiconductor region 2. The impurity concentration of the P-type semiconductor region 3 is higher than the impurity concentration of the P-type semiconductor region 2. As a result, it is possible to lower the contact resistance by connecting the P-type semiconductor region 3 and the contact plug 14 than by connecting the P-type semiconductor region 2 and the contact plug 14. However, the contact plug 14 may be provided in the P-type semiconductor region 2 without providing the P-type semiconductor region 3.

  The P-type semiconductor region 2 is preferably disposed between the dielectric member 7 and the P-type semiconductor region 3. This is because if the P-type semiconductor region 3 and the dielectric member 7 are in contact with each other, electric field concentration occurs between the P-type semiconductor region 3 and the electrode 6.

  An embedded portion 12 is formed by the electrode 6 and the dielectric member 7 embedded in the semiconductor substrate 11. The embedded portion 12 is disposed from the first surface of the semiconductor substrate 11 to a position deeper than the depth at which the N-type semiconductor region 1 is disposed. At this time, the buried portion 12 is formed at a position deeper than the depletion layer region formed by the PN junction between the N-type semiconductor region 1 and the P-type semiconductor region 2.

  The dielectric member 7 is disposed between the electrode 6 and the semiconductor substrate, and the dielectric member 7 is in contact with the P-type semiconductor region 2. The buried portion 12 is configured by, for example, a trench structure (DTI). The distance d between the N-type semiconductor region 1 and the dielectric member 7 is 0.1 μm or less. The N-type semiconductor region 1 and the dielectric member 7 are not necessarily separated from each other, and the N-type semiconductor region 1 and the dielectric member 7 may be in contact with each other.

  The electrode 6 is made of, for example, N-type or P-type doped polysilicon or a metal material. As the dielectric member 7, a silicon oxide film, a silicon nitride film, a dielectric film containing a fixed charge, or the like is used. Examples of the dielectric film containing fixed charges include hafnium oxide (HfO2), zircon oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), and tantalum oxide (Ta2O5).

  When the potential difference between the electrode 6 and the P-type semiconductor region 2 when a material containing a fixed charge is used for the dielectric member 7 and the potential difference between the electrode 6 and the P-type semiconductor region 2 when a material not containing a fixed charge is used Will be explained. At this time, if a material containing a fixed charge is used, the strength of the electric field applied between the electrode 6 and the P-type semiconductor region 2 can be further increased. In other words, when the electric field strength between the electrode 6 and the P-type semiconductor region 2 is set to a predetermined value, the potential difference between the electrode 6 and the P-type semiconductor region 2 can be reduced by using a material containing a fixed charge for the dielectric member 7. can do. That is, the voltage can be lowered.

  In addition, when a material that absorbs or reflects near-infrared light or visible light is used as the material of the electrode 6, it is possible to suppress intrusion of light into peripheral pixels that occurs when avalanche amplification occurs. .

  A higher potential than that of the P-type semiconductor region 2 is supplied to the electrode 6. As a result, an electric field is generated between the electrode 6 and the P-type semiconductor region 2. An inversion layer 26 is formed in a region in contact with the dielectric member 7 on the side surface of the electrode 6 (hereinafter referred to as a semiconductor region in the vicinity of the side surface of the buried portion 12), which is a region affected by the electric field between the electrode 6 and the P-type semiconductor region 2. Is done. The conditions for forming the inversion layer will be described later.

  Note that when the signal charge is a hole, the region corresponding to the P-type semiconductor region 2 is an N-type semiconductor region, so that a lower potential is supplied to the electrode 6 than the N-type semiconductor region corresponding to the P-type semiconductor region 2. To do.

  Due to this electric field, photocharges (electrons) generated in the deep part of the semiconductor substrate 11 move to the inversion layer 26 as indicated by the dotted arrows in FIG. The detailed reason will be described with reference to FIG. Note that the deep portion of the semiconductor substrate 11 is, for example, the P-type semiconductor region 2 below the N-type semiconductor region 1 and is a region (for example, the above-described second region) disposed deeper than the PN junction.

  Furthermore, the electrons moved to the inversion layer 26 cause avalanche amplification in the inversion layer 26. The reason will be described with reference to FIG.

  The contact plug 14 is connected to the P-type semiconductor region 3. The contact plug 15 is connected to the electrode 6. The contact plug 16 is connected to the N-type semiconductor region 1. The wiring unit 5 supplies a potential to the P-type semiconductor region 3 through the contact plug 14.

  The wiring portion 8 supplies a potential to the electrode 6 through the contact plug 15. The wiring portion 4 supplies a potential to the N-type semiconductor region 1 through the contact plug 16. The wiring unit 4 is connected to the control unit 202 in FIG. Here, the wiring part 4 electrically connected to the N-type semiconductor region 1 and the wiring part 8 electrically connected to the electrode 6 are different wiring parts, but by using the same wiring part, The number can be reduced.

  Here, the configuration in which the contact plug 16 is directly connected to the N-type semiconductor region 1 is shown. However, an N-type semiconductor region electrically connected to the N-type semiconductor region 1 is arranged, and the N-type semiconductor region is contacted. The plug 16 may be formed.

  FIG. 4 shows the energy band structure of the electrode 6, the dielectric member 7, and the P-type semiconductor region 2. The reason why electrons generated in the deep part of the semiconductor substrate 11 are attracted to the inversion layer 26 will be described with reference to FIG.

  FIG. 4A, FIG. 4B, and FIG. 4C are examples of energy band diagrams of regions along the line segment CD in FIG. 4A and 4B show energy band diagrams when the signal charge is an electron (electron amplification type), and FIG. 4C shows the case where the signal charge is a hole (hole amplification type). An energy band diagram is shown. In FIG. 4, the downward direction of the drawing is the positive direction of the potential V. In addition, when the signal charge has a reverse polarity, the inequality sign in the mathematical formula is reversed.

  The potential Vt indicates the potential supplied to the electrode 6, and the work function φt indicates the work function of the electrode 6. The potential V2 indicates the potential supplied to the P-type semiconductor region 2, and the work function φ2 indicates the work function of the P-type semiconductor region 2. Further, the difference ΔVeff = (φ2−φt) indicates a difference in vacuum level when the electrode 6 and the P-type semiconductor region 2 are in contact with each other.

FIG. 4A is an energy band diagram when the potential Vt and the potential V2 are the same. The condition for attracting electrons to the semiconductor region near the side surface of the buried portion 12 is that the difference ΔVeff between the vacuum level of the electrode 6 and the vacuum level of the P-type semiconductor region 2 becomes a positive value. Since there is a difference in work function between the P-type semiconductor region 2 and the electrode 6, a difference occurs in the vacuum level. The condition of the difference in vacuum level for attracting electrons to the semiconductor region near the side surface of the buried portion 12 is expressed by Equation 1.
(Φ2−φt) ≧ 0 Formula 1

  According to Equation 1, electrons generated in the semiconductor region near the side surface of the buried portion 12 are attracted to the semiconductor region near the side surface of the buried portion 12. However, in order to attract electrons generated in the deep portion of the semiconductor substrate 11 to the semiconductor region near the side surface of the buried portion 12, the potential of the electrode 6 should be higher than the potential of the P-type semiconductor region 2.

Next, FIG. 4B shows a configuration in which the potential of the electrode 6 is higher than the potential of the P-type semiconductor region 2. In FIG. 4B, the condition for attracting electrons generated in the deep portion of the semiconductor substrate 11 to the semiconductor region near the side surface of the buried portion 12 is Equation 2. Formula 3 is a modified version of Formula 2.
(Vt−φt) − (V2−φ2) ≧ 0 Equation 2
(V2−φ2) ≦ (Vt−φt) Equation 3

  When the conditions of Expressions 1 and 3 are satisfied, electrons are more likely to move to the semiconductor region near the side surface of the embedded portion 12 than when only Expression 1 is satisfied. This is because charges generated in a region away from the semiconductor region near the side surface of the buried portion 12 are also attracted by an electric field generated between the electrode 6 and the P-type semiconductor region 2.

  Next, the case where the signal charge is a hole will be described. When the signal charge is a hole, the region corresponding to the P-type semiconductor region 2 is an N-type semiconductor region. Therefore, the energy band diagram of the region along the line segment CD in FIG. 3 is FIG. 4C. In FIG. 4C, in order for the holes generated in the deep portion of the semiconductor substrate 11 to be attracted to the semiconductor region near the side surface of the buried portion 12, the potential supplied to the electrode 6 corresponds to the P-type semiconductor region 2. The potential is lower than the potential supplied to the N-type semiconductor region.

  A potential structure for explaining a movement path of signal charges generated in the deep part of the semiconductor substrate 11 will be described with reference to FIG. FIG. 5 is an example of a potential structure diagram along line EH in the schematic cross-sectional view shown in FIG. Here, the potential seen from the electron which is a signal charge is shown. When the signal charge is a hole, the potential direction is reversed. In FIG. 5, description will be made assuming that the condition of Equation 3 described above is satisfied. In the description of FIG. 5, the potential V <b> 1 indicates the potential supplied to the N-type semiconductor region 1, and the work function φ <b> 1 indicates the work function of the N-type semiconductor region 1.

FIG. 5 is an example of a potential structure in the line segment EG. In FIG. 5, the solid line 18 is the potential structure of the line segment EH when the condition of Expression 4 is satisfied. At this time, the potential Vt of the electrode 6 is higher than the potential V1 of the N-type semiconductor region 1, and the potential Vt of the electrode 6 and the potential V1 of the N-type semiconductor region 1 are higher than the potential V2 of the P-type semiconductor region 2. In other words, the potential difference between the electrode 6 and the P-type semiconductor region 2 becomes larger than the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 2. Under this bias condition, the inversion layer 26 is formed in the semiconductor region near the side surface of the buried portion 12.
(V2−φ2) <(V1−φ1) ≦ (Vt−φt) Equation 4

  Further, in FIG. 5, the definition of each position (E, F, G, H) and the definition of the height of each potential (XH level, L level, XL level) are shown below.

  The position E is a position belonging to the P-type semiconductor region 2 and an arbitrary position away from the side surface of the electrode 6. The position F is a position where the inversion layer 26 is formed. The position G is a position near the PN junction region between the P-type semiconductor region 2 and the N-type semiconductor region 1. The position H is a position belonging to the N-type semiconductor region 1.

  The height of the XH level potential indicates the height of the potential of the P-type semiconductor region 2. The height of the L level potential indicates the height of the potential of the inversion layer 26. The XL level indicates the height of the potential of the N-type semiconductor region 1.

  In the solid line 18, from the position E to before the position F, it gradually decreases from the height of the potential of the XH level. When approaching position F, the height of the potential decreases sharply and becomes the L-level potential. After the position F, the height of the L-level potential is lowered to the height of the XL-level potential. At positions G and H, the potential is at the XL level.

  When the condition of Formula 4 is satisfied as indicated by the solid line 18, the inversion layer 26 is formed in the P-type semiconductor region 2 disposed in the semiconductor region near the side surface of the buried portion 12. The inversion layer 26 formed at this time is electrically connected to the N-type semiconductor region 1. In particular, when the potential Vt supplied to the electrode 6 is sufficiently large and the potential difference from the P-type semiconductor region 2 is large and in a strong inversion state, a high concentration of electrons collects in the inversion layer 26.

  As described above, the distance d between the N-type semiconductor region 1 and the dielectric member 7 is preferably set to 0.1 μm or less. Then, the potential supplied to the N-type semiconductor region 1 and the potential supplied to the electrode 6 are controlled so that the width of the inversion layer 26 is not less than the distance d. Therefore, the inversion layer 26 and the N-type semiconductor region 1 are electrically connected to have the same potential, and the height of the potential of the inversion layer 26 is equal to the height of the potential of the N-type semiconductor region 1.

  Electrons generated at a position deep with respect to the first surface of the semiconductor substrate 11 on the solid line 18 are attracted from the P-type semiconductor region 2 (position E) away from the inversion layer 26 to the inversion layer 26 (position F). When approaching the inversion layer 26 (position F), the electric field receives an electric field stronger than the electric field at the position E, and the charge causes avalanche amplification. In other words, avalanche amplification occurs in the inversion layer 26 due to a strong electric field generated between the inversion layer 26 and the P-type semiconductor region 2. The avalanche current generated at this time flows into the N-type semiconductor region 1 through the inversion layer 26. And it outputs as a signal via the wiring part 4 connected to the control part 202 of FIG.

  From the above, when Expression 4 is satisfied, the strong electric field in which avalanche amplification occurs is not only the strong electric field of the PN junction on the first surface side of the semiconductor substrate 11 but also between the inversion layer 26 and the P-type semiconductor region 2. Arise. That is, according to the bias condition as shown in Equation 4, the inversion layer 26 and the N-type semiconductor region 1 are electrically connected, and the inversion layer 26 and the N-type semiconductor region 1 have the same potential. The avalanche amplification can be caused in the inversion layer 26 even if the charges generated in the deep part of the semiconductor substrate 11 do not move to the PN junction arranged near the first surface of the semiconductor substrate 11.

  In the case of the solid line 18, since a strong electric field is generated between the inversion layer 26 and the P-type semiconductor region 2, the dielectric member 7 does not depend on the potential V <b> 2, and between the electrode 6 and the P-type semiconductor region 2. The effective potential applied to the disposed dielectric member 7 is about (Vt−φt) − (V1−φ1). According to such a configuration, it is possible to generate a strong electric field while suppressing dielectric breakdown of the dielectric member 7.

  In the conventional configuration described in Japanese Patent Application Laid-Open No. 2014-225647, the N-type semiconductor region forming the PN junction and the dielectric member included in the embedded portion are not in electrical contact. In that case, even if an electric field is applied between the P-type semiconductor region constituting the PN junction and the buried portion, the charge generated in the deep portion of the semiconductor substrate cannot be detected efficiently. Furthermore, the strong electric field generated in the PN junction region on the first surface side of the semiconductor substrate is weakened in the deep part of the semiconductor substrate. For this reason, the signal charges generated in the deep part of the semiconductor substrate 11 randomly move around the semiconductor substrate not by drift but by diffusion, and it may take time to detect the charges.

  Next, using the light detection frequency distribution diagram of FIG. 6, the light detection device using the conventional configuration described in Japanese Patent Application Laid-Open No. 2014-225647 is compared with the light detection device 10 of the present embodiment. FIG. 6 shows the optical response performance (performance against time variation) indicating the charge detection amount with respect to the time until the charge generated in the semiconductor substrate 11 is detected. The horizontal axis in FIG. 6 indicates the time from when the photoelectric conversion element 101 receives a photon to when the signal detection is completed. The vertical axis represents the statistical probability distribution of the detected amount of charge with respect to the time of signal charge among the charge pairs generated when light is incident.

  A dotted line 19 indicates a signal charge detection frequency distribution of the photodetector using the above-described conventional configuration, and a solid line 20 indicates a signal detection frequency distribution of the photodetector 10 using the configuration of the present embodiment. In FIG. 6, the spread of the peak at the mode value includes an error of the pixel signal processing unit 102 that reads the signal timing.

  The dotted line 19 peaks at time T1. Thereafter, a portion where the gentle slope of the frequency distribution continues for a long time appears in the time-consuming direction (right side of the graph). This is generally called a diffusion tail (hereinafter referred to as DT). In DT, since the charge generated in the deep part of the semiconductor substrate reaches the PN junction disposed near the first surface of the semiconductor substrate over time, there is a large time lag with respect to the charge generated in the shallow part of the semiconductor substrate. Due to being detected.

  This DT becomes particularly prominent when detecting light in a wavelength band where charges are generated in the deep part (infrared light for the front-illuminated type and all short wavelengths to long wavelengths for the back-illuminated type). Here, it is assumed that light is incident from the first surface in the front surface irradiation type, and light is incident from the second surface in the back surface irradiation type.

  As described above, the dotted line 19 may take time to detect the signal charge generated in the deep part of the semiconductor substrate 11. For this reason, when receiving light with a wavelength that cannot be ignored in the depth of the semiconductor substrate, the time lag from when the light is received until the detection of the signal charge ends may increase. There is a risk that the time resolution of the will decrease.

  On the other hand, the frequency distribution indicated by the solid line 20 has a peak of the mode value at time T0, which is a time before time T1. Further, the mode peak is higher than the dotted line 19. In the solid line 20, the DT spreads little. In the case of the solid line 20, since the charge detection speed of the semiconductor substrate 11 is faster than that of the dotted line 19, the charge reaches the PN junction region arranged near the surface layer on the dotted line 19. This is because time can be reduced.

  Therefore, the charge detected after time T1 of the dotted line 19 can be detected near the time T0 on the solid line 20, and the amount of charge detected near the time T0 increases.

  Furthermore, the solid line 20 can reduce the time required to detect charges generated in the deep part of the semiconductor substrate 11 with respect to the dotted line 19 and suppress the spread of DT.

  As described above, by using the photodetection device 10 according to the present embodiment, it is possible to reduce the time taken to detect charges generated in the deep portion of the semiconductor substrate 11 as compared with the conventional photodetection device. . Then, it is possible to suppress variation in time until the charge is detected by the charge generated on the first surface of the semiconductor substrate 11 and the charge generated in the deep part of the semiconductor substrate 11.

  In this embodiment, either the front side irradiation type or the back side irradiation type may be used. In the case of the front-illuminated type, when infrared light is incident, variation in time until the charge between the charge generated on the first surface of the semiconductor substrate 11 and the charge generated in the deep part of the semiconductor substrate 11 is detected is detected. The suppression is significant. In the case of the back-illuminated type, when blue light is incident, variation in time until the charge is detected by the charge generated on the first surface of the semiconductor substrate 11 and the charge generated in the deep part of the semiconductor substrate 11 is detected. The suppression becomes remarkable.

Example 1
FIGS. 7A and 7B are a schematic plan view and a cross-sectional view of the light detection device 10 according to the first embodiment of the present invention. Parts having the same functions as those in FIGS. 1 to 6 are denoted by the same reference numerals, and detailed description thereof is omitted.

  Fig.7 (a) shows the plane schematic diagram of the photon detection apparatus 10 of a present Example. In the photodetector 10, an N-type semiconductor region 1, a dielectric member 7, an electrode 6, a P-type semiconductor region 2, and a P-type semiconductor region 3 are disposed on a semiconductor substrate 11.

  In plan view, the P-type semiconductor region 2 has a first region 2A and a second region 2B, and the N-type semiconductor region 1 is disposed so as to be included in the first region 2A. Further, in plan view, the first region 2A is disposed so as to be included in the embedded portion 12, and the embedded portion 12 is disposed so as to be included in the second region 2B.

  Here, in the plan view, the embedded portion 12 is arranged so as to surround the entire periphery of the N-type semiconductor region 1 with the first region 2A interposed therebetween, but it is sufficient that it surrounds at least a part. For example, the embedded portion 12 is not provided in a part between the first region 2A and the second region 2B, and the N-type semiconductor region 1 and the P-type semiconductor region 2 are not provided with the embedded portion 12. You may touch by part.

  In this case, electric field concentration may occur between the end of the N-type semiconductor region 1 and the P-type semiconductor region 2. For this reason, it is better to provide guard rings on the side surfaces and part of the bottom surface of the N-type semiconductor region 1 constituting the end portion of the N-type semiconductor region 1. By providing the guard ring, it is possible to suppress electric field concentration occurring at the end. For example, the guard ring is composed of an N-type semiconductor region or an element isolation portion having a lower impurity concentration than the N-type semiconductor region 1. The same applies to the following embodiments. In the embedded portion 12, the electrode 6 is disposed so as to be included in the two dielectric members 7 in plan view.

  The P-type semiconductor region 3 is arranged so as to be electrically connected to the P-type semiconductor region 2 in plan view. Further, the P-type semiconductor region 3 may be disposed on the second surface side of the semiconductor substrate 11 as long as it is electrically connected to the P-type semiconductor region 2.

  The N-type semiconductor region 1 should be arranged so that the corners are rounded in plan view as in this embodiment. According to such a shape, it is possible to suppress electric field concentration occurring at the corner.

  FIG. 7B is an example of a schematic cross-sectional view of the photodetector 10 along the line segment AB in FIG. 7A. In FIG. 7B, differences from FIG. 3 will be described.

  In FIG. 7B, the embedded portion 12 is disposed so as to surround the P-type semiconductor region 2 disposed in the depth direction of the semiconductor substrate 11 with respect to the N-type semiconductor region 1. According to such a configuration, the surface area where the dielectric member 7 of the embedded portion 12 and the P-type semiconductor region 2 are in contact with each other increases. In addition, the surface area of the inversion layer 26 that attracts charges generated in the deep part of the semiconductor substrate 11 is increased. Furthermore, when a plurality of photoelectric conversion elements 101 are arranged, the diffusion movement of electric charges to the surrounding photoelectric conversion elements 101 can be suppressed. At this time, it is possible to suppress charge mixture between pixels.

  Further, in FIG. 7B, the embedded portion 12 has a bottom portion 24 which is a region disposed at the deepest position with respect to the first surface, a side surface in contact with the P-type semiconductor region 2, and an end continuous with the bottom portion 24 and the side surface. Part 25. N-type semiconductor region 9 (third semiconductor region) is arranged so as to be in contact with bottom portion 24 and end portion 25.

  According to such a configuration, it is possible to suppress electric field concentration occurring at the end portion 25 when a potential is supplied to the electrode 6. Then, it is possible to suppress an increase in the dark signal due to an increase in a tunnel current or the like through the impurity level in the electric field concentration portion.

  Also in the configuration of the present embodiment, it is possible to reduce the time required to detect the charges generated in the deep part of the semiconductor substrate 11.

(Example 2)
FIG. 8 is a schematic plan view and a cross-sectional view of the light detection device 10 according to the second embodiment of the present invention. Parts having the same functions as those in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 8A is a schematic plan view of the photodetecting device of this embodiment. FIG. 8A differs from FIG. 7A in that the P-type semiconductor region 3 is not disposed on the first surface side of the semiconductor substrate 11.

  FIG. 8B is a schematic cross-sectional view taken along the line segment JK in FIG. FIG. 8B differs from FIG. 7B in that the embedded portion 12 extends from the first surface of the semiconductor substrate 11 to the second surface of the semiconductor substrate 11. In FIG. 8B, the electrode 6 and the dielectric member 7 are arranged from the first surface of the semiconductor substrate 11 to the second surface of the semiconductor substrate 11.

  According to such a configuration, it is possible to improve the separation performance for each photoelectric conversion element 101 when a plurality of photoelectric conversion elements 101 are arranged. Then, it is possible to suppress color mixture due to charge color mixture and avalanche light emission.

  Further, FIG. 8B shows that a P-type semiconductor region 3 for supplying a potential to the P-type semiconductor region 2 constituting the PN junction with the N-type semiconductor region 1 is arranged on the second surface side of the semiconductor substrate 11 and contacted. The plug 14 and the wiring part 5 are arranged on the second surface of the semiconductor substrate 11. The potential supplied to the P-type semiconductor region 2 and the P-type semiconductor region 3 is supplied from the second surface side of the semiconductor substrate 11.

  According to such a configuration, it is not necessary to arrange the P-type semiconductor region 3 on the first surface side of the semiconductor substrate 11 in order to connect a contact plug for supplying a potential to the P-type semiconductor region 2. In addition, the area of the photoelectric conversion element 101 can be reduced, and the degree of integration of the pixels 100 can be increased.

  Also in the configuration of the present embodiment, it is possible to reduce the time required to detect the charges generated in the deep part of the semiconductor substrate 11.

(Example 3)
FIG. 9 is a schematic plan view of the light detection device 10 according to the third embodiment of the present invention. Parts having the same functions as those in FIGS. 1 to 8 are denoted by the same reference numerals, and detailed description thereof is omitted.

  9 differs from FIG. 7A in the arrangement of the embedding part 12. In FIG. 9, the N-type semiconductor region 1 has a recess in plan view, and the N-type semiconductor region 1 is disposed so as to be included in the P-type semiconductor region 2. Further, in a plan view, the embedded portion 12 is disposed so as to be included in the P-type semiconductor region 2, and the P-type semiconductor region 2 and at least a part of the embedded portion 12 are disposed in the recess.

  In FIG. 9, if a part of the embedded portion 12 can be electrically connected to the N-type semiconductor region 1, the concave portion of the N-type semiconductor region 1 and the shape of the embedded portion 12 can be freely extended to form a wider planar region. It is possible to collect photocharges in the deep part of the semiconductor substrate 11 in FIG. In the present embodiment, a plurality of embedded portions 12 may be arranged.

  Also in the configuration of the present embodiment, it is possible to reduce the time required to detect the charges generated in the deep part of the semiconductor substrate 11. This embodiment can be applied to other embodiments.

Example 4
10 and 11 are schematic plan views of the light detection device 10 according to the fourth embodiment of the present invention. Parts having the same functions as those in FIGS. 1 to 9 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In FIG. 10, the P-type semiconductor region has a first region 2A and a second region 2B in plan view. In plan view, the embedded portion 12 is disposed so as to be included in the first region 2 </ b> A, and the first region 2 </ b> A is disposed so as to be included in the first semiconductor region 1. Furthermore, the first semiconductor region 1 is arranged so as to be included in the second region 2B in plan view.

  Also in the configuration of the present embodiment, it is possible to reduce the time required to detect the charges generated in the deep part of the semiconductor substrate 11. Furthermore, according to the configuration of the present embodiment, the planar area of the embedded portion 12 can be reduced.

  FIG. 11 is a modification of FIG. 10 and has a configuration in which a plurality of embedding parts shown in FIG. 10 are arranged. According to such a configuration, it is possible to reduce the time required to detect the electric charge generated in the deep part of the semiconductor substrate 11 as compared with FIG. This embodiment can be applied to other embodiments.

(Example 5)
In this embodiment, an example of a light detection system using the light detection device 10 of each embodiment will be described. An invisible light detection system, which is an example of a light detection system, and a medical diagnosis system such as PET will be described with reference to FIG. Parts having the same functions as those in FIGS. 1 to 11 are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 12 is a block diagram illustrating the configuration of the invisible light detection system. The invisible light detection system includes a wavelength conversion unit 1201 and a data processing unit 1207, and includes a plurality of light detection devices 10.

  The irradiated object 1200 irradiates light in a wavelength band that becomes invisible light. The wavelength conversion unit 1201 receives light in a wavelength band that is invisible light emitted from the irradiation object 1200 and emits visible light.

  The photoelectric conversion unit 201 to which the visible light irradiated from the wavelength conversion unit 1201 is incident is photoelectrically converted, and the photodetection device 10 converts the photoelectric conversion signal into a signal based on the photoelectrically converted charge via the control unit 202, the waveform shaping unit 203, and the TDC 204. The base digital signal is held in the memory 205. The plurality of light detection devices 10 may be formed as a single device or may be formed by arranging a plurality of devices.

  A plurality of digital signals held in the memories 205 of the plurality of photodetectors 10 are subjected to signal processing by the data processing unit 1207. Here, a composite process of a plurality of images obtained from a plurality of digital signals is performed as a signal processing means.

  Next, a configuration of a medical diagnostic system such as PET will be described as a specific example of the invisible light detection system.

  A subject who is the irradiated object 1200 emits a radiation pair from within the living body. The wavelength conversion unit 1201 constitutes a scintillator, and the scintillator emits visible light when a radiation pair emitted from the subject enters.

  The photoelectric conversion unit 201 to which the visible light irradiated from the scintillator is incident is photoelectrically converted, and the photodetection device 10 is a digital signal based on a signal based on the photoelectrically converted charge via the control unit 202, the waveform shaping unit 203, and the TDC 204. Is stored in the memory 205. That is, the light detection device 10 is arranged to detect the arrival time of the radiation pair emitted from the subject, detects visible light emitted from the scintillator, and holds the digital signal in the memory 205.

  The digital signals held in the memories 205 of the plurality of light detection devices 10 are processed by the data processing unit 1207. Here, a composition process such as image reconstruction is performed using a plurality of images obtained from a plurality of digital signals as signal processing means, and an in-vivo image of the subject is formed.

(Example 6)
In this embodiment, an example of a light detection system using the light detection device 10 of each embodiment will be described. In FIG. 13, a distance detection system as an example of a light detection system will be described in this embodiment. Parts having functions similar to those in FIGS. 1 to 12 are denoted by the same reference numerals, and detailed description thereof is omitted.

  An example of a block diagram of the distance detection system of the present embodiment will be described with reference to FIG. The distance detection system includes a light source control unit 1301, a light emitting unit 1302, an optical member 1303, the light detection device 10, and a distance calculation unit 1309.

  A light source control unit 1301 controls driving of the light emitting unit 1302. When the light emitting unit 1302 receives a signal from the light source control unit 1301, the light emitting unit 1302 emits light of a short pulse (row) with respect to the imaging direction.

  Light emitted from the light emitting unit 1302 is reflected by the subject 1304. The reflected light is received by the photoelectric conversion unit 201 of the light detection device 10 through the optical member 1303, and a signal based on the photoelectrically converted charge is input to the TDC 204 through the waveform shaping unit 203.

  The TDC 204 compares the signal obtained from the light source control unit 1301 with the signal input from the waveform shaping unit 203. Then, the time from when the light emitting unit 1302 emits the pulsed light to when the reflected light reflected by the subject 1304 is received is digitally converted with high accuracy. The digital signal output from the TDC 204 is held in the memory 205.

  The distance calculation unit 1309 calculates the distance from the light detection device to the subject based on the digital signal for a plurality of measurements held in the memory 205.

  This distance detection system can be applied to a vehicle, for example.

1 N-type semiconductor region 2 P-type semiconductor region 3 P-type semiconductor region 6 Electrode 7 Dielectric member 11 Semiconductor substrate 16 Contact plug

Claims (22)

A semiconductor substrate having a first surface and a second surface opposite to the first surface;
A photoelectric conversion unit having a PN junction composed of a first semiconductor region having a signal charge as a majority carrier and a second semiconductor region having a charge type opposite to the signal charge as a majority carrier;
A photodetecting device comprising: an electrode embedded in the semiconductor substrate; and a buried portion that is disposed between the electrode and the semiconductor substrate and has a dielectric member in contact with the second semiconductor region,
The second semiconductor region is disposed deeper than the first semiconductor region with respect to the first surface,
The buried portion is disposed from the first surface to a position deeper than the first semiconductor region with respect to the first surface,
A potential is supplied to the first semiconductor region, the second semiconductor region, and the electrode so that the inversion layer generated between the electrode and the second semiconductor region is in contact with the first semiconductor region. An optical detection device. A semiconductor substrate having a first surface and a second surface opposite to the first surface;
A photoelectric conversion unit having a PN junction composed of a first semiconductor region having a signal charge as a majority carrier and a second semiconductor region having a charge type opposite to the signal charge as a majority carrier;
An embedded portion having an electrode embedded in the semiconductor substrate, and a dielectric member disposed between the electrode and the semiconductor substrate and in contact with the second semiconductor region;
A photodetection device comprising:
A potential is supplied to the first semiconductor region and the second semiconductor region so that a potential difference between the first semiconductor region and the second semiconductor region is 6 V or more,
The photodetector is characterized in that a potential is supplied to the electrode such that a potential difference between the electrode and the second semiconductor region is equal to or greater than a potential difference between the first semiconductor region and the second semiconductor region.   The photodetection device according to claim 1, further comprising a contact plug that is connected to the first semiconductor region and supplies a potential to the first semiconductor region.   4. The device according to claim 1, wherein a potential difference between a potential supplied to the first semiconductor region and a potential supplied to the second semiconductor region is larger than a breakdown voltage. 5. The light detection device according to item.   5. The device according to claim 1, wherein a potential difference between a potential supplied to the first semiconductor region and a potential supplied to the second semiconductor region is equal to or less than a breakdown voltage. The photodetection device according to item 1.   6. The electrode according to claim 1, wherein a potential of 6 V or more is supplied to the electrode and the first semiconductor region, and a potential of 0 V or less is supplied to the second semiconductor region. Photodetector.   The light detection apparatus according to claim 1, wherein a distance between the first semiconductor region and the dielectric member is 0.1 μm or less.   The photodetection device according to claim 1, wherein the photoelectric conversion unit constitutes an avalanche diode. The embedded portion is
The photodetection device according to claim 1, wherein the photodetection device is disposed to a position deeper than a depletion layer region generated by the PN junction. The embedded portion is
A bottom portion which is a region disposed at a deepest position with respect to the first surface;
A side surface in contact with the second semiconductor region;
An end continuous with the bottom and the side surface,
10. The photodetection device according to claim 1, wherein the bottom portion and the end portion are in contact with a third semiconductor region having the same conductivity type as the first semiconductor region.   The photodetection device according to claim 1, wherein the embedded portion extends from the first surface to the second surface.   12. The second semiconductor region according to claim 1, wherein the second semiconductor region has an impurity concentration gradient in which the impurity concentration decreases from a deep position to a shallow position with respect to the first surface. The photodetection device according to item 1. The second semiconductor region is
A first region that is a region having a first impurity concentration;
A second region which is a region deeper than the first region with respect to the first surface and has a second impurity concentration lower than the first impurity concentration;
A third impurity concentration which is disposed deeper than the first region and the second region with respect to the first surface, and has a third impurity concentration lower than the first impurity concentration and higher than the second impurity concentration; 3 areas,
The light detection device according to claim 1, comprising: A potential V1 supplied to the first semiconductor region; a potential V2 supplied to the second semiconductor region; a potential Vt supplied to the electrode; a work function φ1 of the first semiconductor region; The work function φ2 of the semiconductor region and the work function φt of the electrode satisfy Formula A when the signal charge is an electron and Formula B when the signal charge is a hole. 14. The light detection device according to any one of 1 to 13.
V2-φ2 <Vt−φt ≦ Vt−φt Formula A
V2-φ2> V1-φ1 ≧ Vt−φt Formula B In plan view,
The second semiconductor region has a first region and a second region different from the first region,
The first semiconductor region is disposed so as to be included in the first region,
The first region is disposed so as to be included in the embedded portion,
The photodetection device according to claim 1, wherein the embedded portion is disposed so as to be included in the second region. In plan view,
The first semiconductor region has a recess;
The first semiconductor region is disposed so as to be included in the second semiconductor region,
The embedded portion is disposed so as to be included in the second semiconductor region,
The photodetection device according to claim 1, wherein the second semiconductor region and at least a part of the embedded portion are arranged in the recess. In plan view,
The second semiconductor region has a first region and a second region different from the first region,
The embedded portion is arranged to be included in the first region,
The first region is disposed so as to be included in the first semiconductor region, and the first semiconductor region is disposed so as to be included in the second region. The photodetection device according to any one of the above.   A fourth semiconductor region electrically connected to the second semiconductor region and having the same conductivity type as the second semiconductor region and having an impurity concentration higher than that of the second semiconductor region is the first surface or the second semiconductor region. The photodetection device according to claim 1, wherein the photodetection device is disposed so as to be in contact with a surface.   The photodetection device according to claim 1, wherein the dielectric member is made of a material containing a fixed charge.   20. The electrode according to claim 1, wherein the electrode is made of a material that absorbs or reflects at least a part of infrared light generated due to an avalanche current flowing in the semiconductor substrate. Photodetector. 21. A light detection system comprising a plurality of light detection devices according to claim 1, wherein the wavelength conversion converts light in a first wavelength band into light in a second wavelength band different from the first wavelength band. And
Signal processing means for synthesizing a plurality of images obtained from a plurality of digital signals held in the photodetector,
The light detection system, wherein the light of the second wavelength band output from the wavelength conversion unit is incident on the light detection device. A light detection system comprising the light detection device according to any one of claims 1 to 20, wherein a light emitting unit that emits light detected by the light detection device;
And a distance calculating means for calculating a distance using a digital signal held in the light detecting device.

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